CYRF89235 PRoC™ USB PRoC™ USB PRoC-USB Features ■ Single Device, Two Functions ❐ 8-bit, flash based USB peripheral MCU function and 2.4-GHz radio transceiver function in a single device RF Attributes ❐ Fully integrated 2.4-GHz radio on a chip ❐ 1-Mbps over-the-air data rate ❐ Transmit power typical: 0 dBm ❐ Receive sensitivity typical: –87 dBm ❐ 1 µA typical current consumption in sleep state ❐ Closed-loop frequency synthesis ❐ Supports frequency-hopping spread spectrum ❐ On-chip packet framer with 64-byte first in first out (FIFO) data buffer ❐ Built-in auto-retry-acknowledge protocol simplifies usage ❐ Built-in cyclic redundancy check (CRC), forward error correction (FEC), data whitening ❐ Supports DC ~ 12-MHz SPI bus interface ❐ Additional outputs for interrupt request (IRQ) generation ❐ Digital readout of received signal strength indication (RSSI) ■ MCU Attributes ❐ Powerful Harvard-architecture processor ❐ M8C processor speeds running up to 24 MHz ❐ Low power at high processing speeds ❐ Interrupt controller ❐ 1.9 V to 3.6V operating voltage without USB ❐ Operating voltage with USB enabled: • 3.15 V to 3.45 V when supply voltage is around 3.3 V ❐ Commercial temperature range: 0 °C to +70 °C ■ Flexible on-chip memory ❐ 32 KB flash program storage: • 50,000 erase and write cycles • Flexible protection modes ❐ Up to 2048 bytes SRAM data storage ❐ In-system serial programming (ISSP) ■ Complete development tools ❐ Free development tool PSoC Designer™ ❐ Full-featured, in-circuit emulator and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128-KB trace memory ■ Precision, programmable clocking ■ Cypress Semiconductor Corporation Document Number: 001-77748 Rev. *F Crystal-less oscillator with support for an external crystal or resonator ❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO): • 0.25% accuracy with oscillator lock to USB data, no external components required • Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep. The frequency range is 19 to 50 kHz with a 32-kHz typical value Programmable pin configurations. ❐ Up to 13 general-purpose I/Os (GPIOs) ❐ 25 mA sink current on all GPIO • 60 mA total sink current on Even port pins and 60 mA total sink current on Odd port pins • 120 mA total sink current on all GPIOs ❐ Pull-up, High Z, open drain, CMOS drive modes on all GPIO ❐ CMOS drive mode A –5 mA source current on ports 0 and 1 and 1 mA on port 2 • 20 mA total source current on all GPIOs ❐ Low dropout voltage regulator for Port 1 pins: • Programmable to output 3.0, 2.5, or 1.8 V ❐ Selectable, regulated digital I/O on Port 1 ❐ Configurable input threshold for Port 1 ❐ Hot-swappable Capability on Port 1 Full-Speed USB (12 Mbps) ❐ Eight unidirectional endpoints ❐ One bidirectional control endpoint ❐ USB 2.0-compliant ❐ Dedicated 512 bytes buffer ❐ No external crystal required Additional system resources ❐ Configurable communication speeds 2 ❐ I C slave: • Selectable to 50 kHz, 100 kHz, or 400 kHz • Implementation requires no clock stretching • Implementation during sleep modes with less than 100 A • Hardware address detection ❐ SPI master and SPI slave: • Configurable between 46.9 kHz and 12 MHz ❐ Three 16-bit timers ❐ 10-bit ADC used to monitor battery voltage or other signals with external components ❐ Watchdog and sleep timers ❐ Integrated supervisory circuit ❐ • ■ ■ ■ 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 15, 2013 CYRF89235 PRoC-USB Logical Block Diagram Port 2 Port 1 Port 0 Prog. LDO enCoRe V CORE System Bus SRAM 2048 Bytes SROM 32K Flash Sleep and Watchdog CPU Core (M8C) Interrupt Controller 6/12/24 MHz Internal Main Oscillator VIN VOUT WIRELESSUSB NL SYSTEM VDD_IO GFSK LDO Linear Regulator Modulator PKT FIFO RST_n Framer SPI Registers PA Synthesizer ANT ANTb VCO Pwr/ Reset BRCLK Receive GFSK Demodulator Xtal Osc X Image Rej . Mxr. XTALi LNA + BPF XTALo ADC 3 16-Bit Timers I2C Slave/SPI Master-Slave POR and LVD System Resets Full Speed USB SYSTEM RESOURCES Document Number: 001-77748 Rev. *F Page 2 of 45 CYRF89235 Contents Functional Overview ........................................................ 4 The enCoRe V Core .................................................... 4 Full-Speed USB ........................................................... 4 10-bit ADC ................................................................... 5 SPI ............................................................................... 5 I2C Slave ..................................................................... 6 WirelessUSB-NL Subsystem ....................................... 7 Transmit Power Control ............................................... 7 Power-on and Register Initialization Sequence ........... 7 Additional System Resources ..................................... 8 Getting Started .................................................................. 8 Application Notes ........................................................ 8 Development Kits ........................................................ 8 Training ....................................................................... 8 CYPros Consultants .................................................... 8 Solutions Library .......................................................... 8 Technical Support ....................................................... 8 Development Tools .......................................................... 9 PSoC Designer Software Subsystems ........................ 9 Designing with PSoC Designer ..................................... 10 Select User Modules ................................................. 10 Configure User Modules ............................................ 10 Organize and Connect .............................................. 10 Generate, Verify, and Debug ..................................... 10 Pin Configuration ........................................................... 11 Pin Definitions ................................................................ 12 Register Reference ......................................................... 13 Register Conventions ................................................ 13 Register Mapping Tables .......................................... 13 Electrical Specifications ................................................ 16 Absolute Maximum Ratings ....................................... 16 Operating Temperature ............................................. 16 DC Chip-Level Specifications .................................... 17 DC USB Interface Specifications ............................... 18 ADC Electrical Specifications .................................... 19 DC Analog Mux Bus Specifications ........................... 20 DC Low Power Comparator Specifications ............... 20 Document Number: 001-77748 Rev. *F Comparator User Module Electrical Specifications ... 20 DC GPIO Specifications ............................................ 21 DC POR and LVD Specifications .............................. 23 DC Programming Specifications ............................... 24 DC I2C Specifications ............................................... 25 DC Reference Buffer Specifications .......................... 25 DC IDAC Specifications ............................................ 25 AC Chip Level Specifications .................................... 26 AC USB Data Timings Specifications ........................ 27 AC USB Driver Specifications ................................... 27 AC General Purpose I/O Specifications .................... 28 AC Comparator Specifications .................................. 29 AC External Clock Specifications .............................. 29 AC Programming Specifications ................................ 30 AC I2C Specifications ................................................ 31 SPI Master AC Specifications ................................... 32 SPI Slave AC Specifications ..................................... 33 Electrical Specifications - RF Section .......................... 35 Initialization Timing Requirements ............................ 38 SPI Timing Requirements ......................................... 39 Packaging Information ................................................... 40 Packaging Dimensions .............................................. 40 Thermal Impedances ................................................. 41 Capacitance on Crystal Pins ..................................... 41 Solder Reflow Peak Temperature ............................. 41 Ordering Information ...................................................... 42 Ordering Code Definitions ......................................... 42 Acronyms ........................................................................ 43 Document Conventions ................................................. 43 Units of Measure ....................................................... 43 Numeric Naming ........................................................ 43 Document History Page ................................................. 44 Sales, Solutions, and Legal Information ...................... 45 Worldwide Sales and Design Support ....................... 45 Products .................................................................... 45 PSoC Solutions ......................................................... 45 Page 3 of 45 CYRF89235 Functional Overview Figure 1. USB Transceiver Regulator The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components with one, low cost single-chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. PS2 Pull Up VOLTAGE REGULATOR 5V 3.3V 1.5K The architecture for this device family, as illustrated in the PRoC-USB Logical Block Diagram on page 2, consists of three main areas: the CPU core, the WirelessUSB™ NL subsystem and the system resources. TEN DP TD DM RECEIVERS This product is an enhanced version of Cypress’s successful full speed-USB peripheral controllers. Enhancements include faster CPU at lower voltage operation, lower current consumption, twice the RAM and flash, hot-swappable I/Os, I2C hardware address recognition, new very low current sleep mode, and new package options. 5K TRANSMITTER PDN RD DPO RSE0 The enCoRe V Core The enCoRe V Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard architecture microprocessor. System resources provide additional capability, such as a configurable I2C slave and SPI master-slave communication interface and various system resets supported by the M8C. Full-Speed USB The enCoRe V USB system resource adheres to the USB 2.0 Specification for full-speed devices operating at 12 Mb/second with one upstream port and one USB address. enCoRe V USB consists of these components: ■ Serial interface engine (SIE) block. ■ PSoC memory arbiter (PMA) block. ■ ■ DMO At the enCoRe V system level, the full-speed USB system resource interfaces to the rest of the enCoRe V by way of the M8C's register access instructions and to the outside world by way of the two USB pins. The SIE supports nine endpoints including a bidirectional control endpoint (endpoint 0) and eight unidirectional data endpoints (endpoints 1 to 8). The unidirectional data endpoints are individually configurable as either IN or OUT. The USB serial interface engine (SIE) allows the enCoRe V device to communicate with the USB host at full-speed data rates (12 Mb/s). The SIE simplifies the interface to USB traffic by automatically handling the following USB processing tasks without firmware intervention: ■ Translates the encoded received data and formats the data to be transmitted on the bus. 512 bytes of dedicated SRAM. ■ A full-speed USB Transceiver with internal regulator and two dedicated USB pins. Generates and checks cyclical redundancy checks (CRCs). Incoming packets failing checksum verification are ignored. ■ Checks addresses. Ignores all transactions not addressed to the device. ■ Sends appropriate ACK/NAK/Stall handshakes. ■ Identifies token type (SETUP, IN, OUT) and sets the appropriate token bit once a valid token in received. ■ Identifies Start-of-Frame (SOF) and saves the frame count. ■ Sends data to or retrieves data from the USB SRAM, by way of the PSoC Memory Arbiter (PMA). Document Number: 001-77748 Rev. *F Page 4 of 45 CYRF89235 Firmware is required to handle various parts of the USB interface. The SIE issues interrupts after key USB events to direct firmware to appropriate tasks: ■ Fill and empty the USB data buffers in USB SRAM. ■ Enable PMA channels appropriately. ■ Coordinate enumeration by decoding USB device requests. ■ Suspend and resume coordination. ■ Verify and select data toggle values. input mux or the temperature sensor with an input voltage range of 0 V to VREFADC. In the ADC only configuration (the ADC MUX selects the Analog mux bus, not the default temperature sensor connection), an external voltage can be connected to the input of the modulator for voltage conversion. The ADC is run for a number of cycles set by the timer, depending upon the desired resolution of the ADC. A counter counts the number of trips by the comparator, which is proportional to the input voltage. The Temp Sensor block clock speed is 36 MHz and is divided down to 1 to 12 MHz for ADC operation. 10-bit ADC SPI The ADC on enCoRe V device is an independent block with a state machine interface to control accesses to the block. The ADC is housed together with the temperature sensor core and can be connected to this or the Analog mux bus. As a default operation, the ADC is connected to the temperature sensor diodes to give digital values of the temperature. The serial peripheral interconnect (SPI) 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. Figure 2. ADC System Performance Block Diagram VIN TEMP SENSOR/ ADC Figure 3. Basic SPI Configuration SPI Master SPI Slave Data is output by Data is registered at the both the Master input of both devices on the and Slave on opposite edge of the clock. one edge of the clock. SCLK MOSI MISO TEMP DIODES ADC SYSTEM BUS INTERFACE BLOCK COMMAND/ STATUS A device can be a master or slave. A master outputs clock and data to the slave device and inputs slave data. A slave device inputs clock and data from the master device and outputs data for input to the master. Together, the master and slave are essentially a circular Shift register, where the master generates the clocking and initiates data transfers. A basic data transfer occurs when the master sends eight bits of data, along with eight clocks. In any transfer, both master and slave transmit and receive simultaneously. If the master only sends data, the received data from the slave is ignored. If the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. Figure 4. SPI Block Diagram SPI Block MOSI, MISO SCLK DATA_IN DATA_OUT CLK_IN CLK_OUT SCLK INT SYSCLK Interface to the M8 C ( Processor ) Core MOSI, MISO SS_ Registers The ADC User Module contains an integrator block and one comparator with positive and negative input set by the MUXes. The input to the integrator stage comes from the analog global Document Number: 001-77748 Rev. *F CONFIGURATION[7:0] CONTROL[7:0] TRANSMIT[7:0] RECEIVE[7:0] Page 5 of 45 CYRF89235 SPI configuration register (SPI_CFG) sets master/slave functionality, clock speed, and interrupt select. SPI control register (SPI_CR) provides four control bits and four status bits for device interfacing and synchronization. The SPIM hardware has no support for driving the Slave Select (SS_) signal. The behavior and use of this signal is dependent on the application and enCoRe V device and, if required, must be implemented in firmware. There is an additional data input in the SPIS, Slave Select (SS_), which is an active low signal. SS_ must be asserted to enable the SPIS to receive and transmit. SS_ has two high level functions: ■ To allow for the selection of a given slave in a multi-slave environment. ■ To provide additional clocking for TX data queuing in SPI modes 0 and 1. I2C Slave The I2C slave enhanced communications block is a serial-to-parallel processor, designed to interface the enCoRe V device to a two-wire I2C serial communications bus. To eliminate the need for excessive CPU intervention and overhead, the block provides I2C-specific support for status detection and generation of framing bits. By default, the I2C slave enhanced module is firmware compatible with the previous generation of I2C slave functionality. However, this module provides new features that are configurable to implement significant flexibility for both internal and external interfacing. The basic I2C features include: ■ Slave, transmitter, and receiver operation. ■ Byte processing for low CPU overhead. ■ Interrupt or polling CPU interface. ■ Support for clock rates of up to 400 kHz. ■ 7- or 10-bit addressing (through firmware support). ■ SMBus operation (through firmware support). Enhanced features of the I2C Slave Enhanced Module include: ■ Support for 7-bit hardware address compare. ■ Flexible data buffering schemes. ■ A "no bus stalling" operating mode. ■ A low power bus monitoring mode. The I2C block controls the data (SDA) and the clock (SCL) to the external I2C interface through direct connections to two dedicated GPIO pins. When I2C is enabled, these GPIO pins are not available for general purpose use. The enCoRe V CPU firmware interacts with the block through I/O register reads and writes, and firmware synchronization is implemented through polling and/or interrupts. In the default operating mode, which is firmware compatible with previous versions of I2C slave modules, the I2C bus is stalled upon every received address or byte, and the CPU is required to read the data or supply data as required before the I2C bus continues. However, this I2C Slave Enhanced module provides new data buffering capability as an enhanced feature. In the EZI2C buffering mode, the I2C slave interface appears as a 32-byte RAM buffer to the external I2C master. Using a simple predefined protocol, the master controls the read and write pointers into the RAM. When this method is enabled, the slave never stalls the bus. In this protocol, the data available in the RAM (this is managed by the CPU) is valid. Figure 5. I2C Block Diagram I2C Plus Slave I2C Core To/From GPIO Pins SCL_IN CPU Port I2C Basic Configuration I2C_BUF I2C_CFG SDA_OUT SCL_OUT I2C_EN I2C_SCR 32 Byte RAM I2C_DR HW Addr Cmp I2C_ADDR Buffer Ctl I2C_BP Plus Features Document Number: 001-77748 Rev. *F System Bus SDA_IN Buffer Module SYSCLK I2C_CP I2C_XCFG MCU_BP I2C_XSTAT MCU_CP STANDBY Page 6 of 45 CYRF89235 Among the advantages of WirelessUSB-NL are its fast lock times and channel switching, along with the ability to transmit larger payloads. Use of longer payload packets, compared to multiple short payload packets, can reduce overhead, improve overall power efficiency, and help alleviate spectrum crowding. VIN VDD1 ...VDD7 VOUT VDD_IO LDO Linear Regulator GFSK Modulator PKT SPI_SS CLK MISO MOSI RST_n PA Framer WirelessUSB-NL, optimized to operate in the 2.4-GHz ISM band, is Cypress's third generation of 2.4-GHz low-power RF technology. WirelessUSB-NL implements a Gaussian frequency-shift keying (GFSK) radio using a differentiated single-mixer, closed-loop modulation design that optimizes power efficiency and interference immunity. Closed-loop modulation effectively eliminates the problem of frequency drift, enabling WirelessUSB-NL to transmit up to 255-byte payloads without repeatedly having to pay power penalties for re-locking the phase-locked loop (PLL) as in open-loop designs Figure 6. WirelessUSB-NL logic Block Diagram SPI Registers WirelessUSB-NL Subsystem Synthesizer Pwr/ Reset BRCLK Xtal Osc GFSK Demodulator XTALi XTALo With PRoC-USB, the WirelessUSB-NL transceiver can add wireless capability to a wide variety of full speed USB applications. Table 1. Transmit Power Control The low-IF receiver architecture produces good selectivity and image rejection, with typical sensitivity of –87 dBm or better on most channels. Sensitivity on channels that are integer multiples of the crystal reference oscillator frequency (12 MHz) may show approximately 5 dB degradation. Digital RSSI values are available to monitor channel quality. On-chip transmit and receive FIFO registers are available to buffer the data transfer with MCU. Over-the-air data rate is always 1 Mbps even when connected to a slow, low-cost MCU. Built-in CRC, FEC, data whitening, and automatic retry/acknowledge are all available to simplify and optimize performance for individual applications. For more details on the radio’s implementation details and timing requriements, please go through the WirelessUSB-NL datasheet in www.cypress.com. Document Number: 001-77748 Rev. *F LNA + BPF GND GND Transmit Power Control The product transmits GFSK data at approximately 0-dBm output power. Sigma-Delta PLL delivers high-quality DC-coupled transmit data path. X Image Rej. Mxr. Combined with Cypress's enCoRe V based full-speed USB controllers, WirelessUSB-NL also provides the lowest bill of materials (BOM) cost solution for sophisticated PC peripheral applications such as wireless keyboards and mice, as well as best-in-class wireless performance in other demanding applications, such as toys, remote controls, fitness, automation, presenter tools, and gaming. The WirelessUSB-NL is a fully-integrated CMOS RF transceiver, GFSK data modem, and packet framer, optimized for use in the 2.4-GHz ISM band. It contains transmit, receive, RF synthesizer, and digital modem functions, with few external components. The transmitter supports digital power control. The receiver uses extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. ANT ANTb VCO The following table lists recommended settings for register 9 for short-range applications, where reduced transmit RF power is a desirable trade off for lower current. Power Setting Description Typical Transmit Power (dBm) Value of Register 9 Silicon ID 0x1002 Silicon ID 0x2002 PA0 - Highest power +1 0x1820 0x7820 PA2 - High power 0 0x1920 0x7920 PA4 - High power –3 0x1A20 0x7A20 PA8 - Low power –7.5 0x1C20 0x7C20 PA12 - Lower power –11.2 0x1E20 0x7E20 Note: Silicon ID can be read from Register 31. Power-on and Register Initialization Sequence For proper initialization at power up, VIN must ramp up at the minimum overall ramp rate no slower than shown by TVIN specification in the following figure. During this time, the RST_n line must track the VIN voltage ramp-up profile to within approximately 0.2 V. Since most MCU GPIO pins automatically default to a high-Z condition at power up, it only requires a pull-up resistor. When power is stable and the MCU POR releases, and MCU begins to execute instructions, RST_n must then be pulsed low as shown in Figure 18 on page 39, followed by writing Reg 27 = 0x4200. During or after this SPI transaction, the State Machine status can be read to confirm FRAMER_ST = 1, indicating a proper initialization. Page 7 of 45 CYRF89235 Additional System Resources Development Kits System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low-voltage detection and power-on reset. The following statements describe the merits of each system resource. PSoC development kits are available online from Cypress at http://www.cypress.com and through a growing number of regional and global distributors, including Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. ■ Low-voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced power-on reset (POR) circuit eliminates the need for a system supervisor. ■ The 5 V maximum input, 1.8, 2.5, or 3 V selectable output, LDO regulator provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO. ■ Standard Cypress PSoC IDE tools are available for debugging the enCoRe V family of parts. Getting Started The quickest path to understanding the PRoC-USB silicon is by reading this data sheet and using the PSoC® Designer™ integrated development environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, see the enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx Technical Reference Manual (TRM) for this PSoC device. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at http://www.cypress.com. Training Free PSoC technical training (on demand, webinars, and workshops) is available online at http://www.cypress.com. The training covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to http://www.cypress.com and look for CYPros Consultants. Solutions Library Visit our growing library of solution-focused designs at http://www.cypress.com. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at http://www.cypress.com. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs and are available at http://www.cypress.com. Document Number: 001-77748 Rev. *F Page 8 of 45 CYRF89235 Development Tools of debugging tools. You can develop your design in C, assembly, or a combination of the two. PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog ■ Integrated source-code editor (C and assembly) ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. ■ PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for a given application. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Device Programmers Code Generation Tools Firmware needs to be downloaded to PRoC USB device only at 3.3 V using Miniprog3 Programmer. This Programmer kit can be purchased from Cypress Store using part# ‘CY8CKIT-002 MiniProg3’. It is a small, compact programmer which connects PC via a USB 2.0 cable (provided along with CY8cKIT-002) The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range Note: MiniProg1 Programmer should not be used as it does not support programming at 3.3 V. Document Number: 001-77748 Rev. *F Page 9 of 45 CYRF89235 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called user modules. User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a pulse-width modulator (PWM) user module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user Document Number: 001-77748 Rev. *F module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Page 10 of 45 CYRF89235 Pin Configuration The PRoC-USB device is available in a 40-pin QFN package, which is illustrated in the subsequent tables. Figure 7. 40-pin QFN pinout Document Number: 001-77748 Rev. *F Page 11 of 45 CYRF89235 Pin Definitions Pin No 1 2 Pin name P1/SCLK Pin Description Digital I/O, Analog I/O, SPI CLK P1/MOSI [1, 2] Digital I/O, Analog I/O, TC CLK, I2C SCL, SPI MOSI 3 GND Ground connection 4, 20, 25, 33, 34, 37 VDD Core power supply voltage. Connect all VDD pins to VOUT pin. 5 D+ USB PHY, Digital I/O 6 D- USB PHY, Digital I/O 7 FIFO FIFO status indicator bit 8, 21, 24 VIN Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator 9 P1 [1, 2] 10 VDD_IO 11 P1 Analog I/O, Digital I/O 12 P1 Analog I/O, Digital I/O, EXT CLK 13 XRES 14 SPI_SS Analog I/O, Digital I/O, TC DATA, I2C SDA VDD for the digital interface Active high external reset with internal pull-down Enable input for SPI, active low. Also used to bring device out of sleep state. 15 PKT 16 SPI_CLK Transmit/receive packet status indicator bit 17 SPI_MOSI Data input for the SPI bus 18 SPI_MISO Data output (tristate when not active) 19 RST_n Clock input for SPI interface RST_n Low: Chip shutdown to conserve power. Register values lost RST_n High: Turn on chip, registers restored to default value 22 VOUT 1.8 V output from on-chip LDO. Connect to all VDD pins, do not connect to external loads. 23 P0 Analog I/O, Digital I/O, VREF 26 XTALO Output of the crystal oscillator gain block 27 XTALI Input to the crystal oscillator gain block 28 P0 Analog I/O, Digital I/O,SPI CLK 29 P0 Analog I/O, Digital I/O, Integrating input 30 P0 Analog I/O, Digital I/O, Integrating input 31 P2 Analog I/O, Digital I/O, XTAL Out 32 P2 Analog I/O, Digital I/O, XTAL In 35 ANTb Differential RF input/output. Each of these pins must be DC grounded, 20 kΩ or less 36 ANT 38 P1/SS_N Digital I/O, Analog I/O, I2C SCL, SPI SS Differential RF input/output. Each of these pins must be DC grounded, 20 kΩ or less 39 P1/MISO Digital I/O, Analog I/O, I2C SDA, SPI MISO 40 VDD Core power supply voltage. Connect all VDD pins to VOUT pin. Notes 1. During power up or reset event, device P1 and P1 may disturb the I2C bus. Use alternate pins if issues are encountered. 2. These are the in-system serial programming (ISSP) pins that are not High Z at power-on reset (POR). Document Number: 001-77748 Rev. *F Page 12 of 45 CYRF89235 Register Reference The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order. Register Conventions Register Mapping Tables The register conventions specific to this section are listed in the following table. The enCoRe V device has a total register address space of 512 bytes. The register space is also referred to as I/O space and is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space). The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Table 2. Register Conventions Convention R Description Read register or bits W Write register or bits L Logical register or bits C Clearable register or bits # Access is bit specific Document Number: 001-77748 Rev. *F Page 13 of 45 CYRF89235 Table 3. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE Addr (0,Hex) Access Name 00 RW EP1_CNT0 01 RW EP1_CNT1 02 EP2_CNT0 03 EP2_CNT1 PRT1DR 04 RW EP3_CNT0 PRT1IE 05 RW EP3_CNT1 06 EP4_CNT0 07 EP4_CNT1 PRT2DR 08 RW EP5_CNT0 PRT2IE 09 RW EP5_CNT1 0A EP6_CNT0 0B EP6_CNT1 PRT3DR 0C RW EP7_CNT0 PRT3IE 0D RW EP7_CNT1 0E EP8_CNT0 0F EP8_CNT1 PRT4DR 10 RW PRT4IE 11 RW 12 13 14 15 16 17 18 PMA0_DR 19 PMA1_DR 1A PMA2_DR 1B PMA3_DR 1C PMA4_DR 1D PMA5_DR 1E PMA6_DR 1F PMA7_DR 20 21 22 23 24 PMA8_DR 25 PMA9_DR 26 PMA10_DR 27 PMA11_DR 28 PMA12_DR SPI_TXR 29 W PMA13_DR SPI_RXR 2A R PMA14_DR SPI_CR 2B # PMA15_DR 2C TMP_DR0 2D TMP_DR1 2E TMP_DR2 2F TMP_DR3 30 USB_SOF0 31 R USB_SOF1 32 R USB_CR0 33 RW USBIO_CR0 34 # USBIO_CR1 35 # EP0_CR 36 # EP0_CNT0 37 # EP0_DR0 38 RW EP0_DR1 39 RW EP0_DR2 3A RW EP0_DR3 3B RW EP0_DR4 3C RW EP0_DR5 3D RW EP0_DR6 3E RW EP0_DR7 3F RW Gray fields are reserved; do not access these fields. Document Number: 001-77748 Rev. *F Addr (0,Hex) Access 40 # 41 RW 42 # 43 RW 44 # 45 RW 46 # 47 RW 48 # 49 RW 4A # 4B RW 4C # 4D RW 4E # 4F RW 50 51 52 53 54 55 56 57 58 RW 59 RW 5A RW 5B RW 5C RW 5D RW 5E RW 5F RW 60 61 62 63 64 RW 65 RW 66 RW 67 RW 68 RW 69 RW 6A RW 6B RW 6C RW 6D RW 6E RW 6F RW 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. Name PT0_CFG PT0_DATA1 PT0_DATA0 PT1_CFG PT1_DATA1 PT1_DATA0 PT2_CFG PT2_DATA1 PT2_DATA0 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access Name I2C_XCFG I2C_XSTAT I2C_ADDR I2C_BP I2C_CP CPU_BP CPU_CP I2C_BUF CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR INT_CLR0 INT_CLR1 INT_CLR2 INT_MSK2 INT_MSK1 INT_MSK0 INT_SW_EN INT_VC RES_WDT RW RW RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW R RW R R RW R RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RC W RL # # Page 14 of 45 CYRF89235 Table 4. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 Addr (1,Hex) Access Name Addr (1,Hex) Access 00 RW PMA4_RA 40 RW 01 RW PMA5_RA 41 RW 02 PMA6_RA 42 RW 03 PMA7_RA 43 RW PRT1DM0 04 RW PMA8_WA 44 RW PRT1DM1 05 RW PMA9_WA 45 RW 06 PMA10_WA 46 RW 07 PMA11_WA 47 RW PRT2DM0 08 RW PMA12_WA 48 RW PRT2DM1 09 RW PMA13_WA 49 RW 0A PMA14_WA 4A RW 0B PMA15_WA 4B RW PRT3DM0 0C RW PMA8_RA 4C RW PRT3DM1 0D RW PMA9_RA 4D RW 0E PMA10_RA 4E RW 0F PMA11_RA 4F RW PRT4DM0 10 RW PMA12_RA 50 RW PRT4DM1 11 RW PMA13_RA 51 RW 12 PMA14_RA 52 RW 13 PMA15_RA 53 RW 14 EP1_CR0 54 # 15 EP2_CR0 55 # 16 EP3_CR0 56 # 17 EP4_CR0 57 # 18 EP5_CR0 58 # 19 EP6_CRO 59 # 1A EP7_CR0 5A # 1B EP8_CR0 5B # 1C 5C 1D 5D 1E 5E 1F 5F 20 60 21 61 22 62 23 63 24 64 25 65 26 66 27 67 28 68 SPI_CFG 29 RW 69 2A 6A 2B 6B 2C TMP_DR0 6C RW 2D TMP_DR1 6D RW 2E TMP_DR2 6E RW 2F TMP_DR3 6F RW USB_CR1 30 # 70 31 71 32 72 33 73 PMA0_WA 34 RW 74 PMA1_WA 35 RW 75 PMA2_WA 36 RW 76 PMA3_WA 37 RW 77 PMA4_WA 38 RW 78 PMA5_WA 39 RW 79 PMA6_WA 3A RW 7A PMA7_WA 3B RW 7B PMA0_RA 3C RW 7C PMA1_RA 3D RW 7D PMA2_RA 3E RW 7E PMA3_RA 3F RW 7F Gray fields are reserved; do not access these fields. # Access is bit specific. Document Number: 001-77748 Rev. *F Name Addr (1,Hex) Access Name 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 EC0_ENBUS 93 EC0_TRIM 94 95 96 97 98 MUX_CR0 99 MUX_CR1 9A MUX_CR2 9B MUX_CR3 9C IO_CFG1 9D OUT_P1 9E IO_CFG2 9F MUX_CR4 A0 OSC_CR0 A1 ECO_CFG A2 OSC_CR2 A3 VLT_CR A4 VLT_CMP A5 A6 A7 A8 IMO_TR A9 ILO_TR AA AB SLP_CFG AC SLP_CFG2 AD SLP_CFG3 AE AF B0 B1 B2 B3 B4 B5 B6 B7 CPU_F B8 B9 BA IMO_TR1 BB BC USB_MISC_CR BD RW BE BF Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW # RW RW R W W RW RW RW RL RW Page 15 of 45 CYRF89235 Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up-to-date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com Figure 8. Voltage versus CPU Frequency Figure 9. IMO Frequency Trim Options 3.6V 3.6 V Vdd Voltage V I N Voltage li d ng Va rati n e io Op Reg SLIMO Mode = 01 SLIMO Mode = 00 SLIMO Mode = 10 1.9V 1.9 V 750 kHz 3 MHz CPU 3 MHz 750 kHz 24 MHz 6 MHz 12 MHz 24 MHz IMO Frequency Frequency Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 5. Absolute Maximum Ratings Symbol TSTG Description Storage temperature VIN Conditions Min Typ Max Units Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrades reliability. –55 25 125 °C – 1.9 – 3.63 V – –0.5 – VIN + 0.5 V VIO DC input voltage VIOZ DC voltage applied to tristate – –0.5 – VIN + 0.5 V IMIO Maximum current into any port pin – –25 – +50 mA ESD Electrostatic discharge voltage Human body model ESD i) RF pins (ANT, ANTb) ii) Analog pins (XTALi, XTALo) iii) Remaining pins 500 500 2000 – – V LU Latch-up current In accordance with JESD78 standard – – 140 mA Min Typ Max Units 0 – 70 °C Operating Temperature Table 6. Operating Temperature Symbol TA Description Ambient temperature Conditions – Notes 3. Program the device at 3.3 V only. Hence use Miniprog3 only since Miniprog1 does not support programming at 3.3 V. 4. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VIN. Document Number: 001-77748 Rev. *F Page 16 of 45 CYRF89235 DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 7. DC Chip-Level Specifications Symbol Conditions Min Typ Max Units Supply voltage No USB activity. Refer the table DC POR and LVD Specifications on page 23 1.9 – 3.6 V VINUSB [5, 6, 7, 8] Operating voltage USB activity, USB regulator bypassed 3.15 3.3 3.45 V IDD24 Supply current, IMO = 24 MHz Conditions are VIN 3.0 V, TA = 25 °C, CPU = 24 MHz. no I/O sourcing current – 2.88 4.00 mA IDD12 Supply current, IMO = 12 MHz Conditions are VIN 3.0 V, TA = 25 °C, CPU = 12 MHz. no I/O sourcing current – 1.71 2.60 mA IDD6 Supply current, IMO = 6 MHz Conditions are VIN 3.0 V, TA = 25 °C, CPU = 6 MHz. no I/O sourcing current – 1.16 1.80 mA ISB0 Deep sleep current VIN 3.0 V, TA = 25 °C, I/O regulator turned off – 0.10 1.05 A ISB1 Standby current with POR, LVD and sleep timer VIN 3.0 V, TA = 25 °C, I/O regulator turned off – 1.07 1.50 A ISBI2C Standby current with I2C enabled Conditions are VIN = 3.3 V, TA = 25 °C and CPU = 24 MHz – 1.64 – A VIN [5, 6, 7, 8] Description Notes 5. If powering down in standby sleep mode, to properly detect and recover from a VIN brown out condition any of the following actions must be taken: Bring the device out of sleep before powering down. Assure that VIN falls below 100 mV before powering back up. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. Increase the buzz rate to assure that the falling edge of VIN is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the enCoRe V Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VIN brown out conditions to be detected for edge rates slower than 1 V/ms. 6. Always greater than 50 mV above VPPOR1 voltage for falling supply. 7. Always greater than 50 mV above VPPOR2 voltage for falling supply. 8. Always greater than 50 mV above VPPOR3 voltage for falling supply. Document Number: 001-77748 Rev. *F Page 17 of 45 CYRF89235 DC USB Interface Specifications Table 8. DC USB Interface Specifications Min Typ Max Units RUSBI Symbol USB D+ pull-up resistance Description With idle bus 900 – 1575 RUSBA USB D+ pull-up resistance While receiving traffic 1425 – 3090 VOHUSB Static output high – 2.8 – 3.6 V VOLUSB Static output low – – – 0.3 V VDI Differential input sensitivity – 0.2 – VCM Differential input common mode – range 0.8 – 2.5 V VSE Single ended receiver threshold – 0.8 – 2.0 V CIN Transceiver capacitance – – – 50 pF IIO High Z state data line leakage On D+ or D– line –10 – +10 A RPS2 PS/2 pull-up resistance – 3000 5000 7000 REXT External USB series resistor In series with each USB pin 21.78 22.0 22.22 Document Number: 001-77748 Rev. *F Conditions V Page 18 of 45 CYRF89235 ADC Electrical Specifications Table 9. ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units Input VIN Input voltage range – 0 – VREFADC V CIIN Input capacitance – – – 5 pF RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution ADC reference voltage – 1.14 – 1.26 V 2.25 – 6 MHz 1/(500fF × 1/(400fF × 1/(300fF × data clock) data clock) data clock) Reference VREFADC Conversion Rate FCLK Data clock Source is chip’s internal main oscillator. See AC Chip-Level Specifications for accuracy S8 8-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^Resolution/Data Clock) – 23.43 – ksps S10 10-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^resolution/data clock) – 5.85 – ksps DC Accuracy RES Resolution Can be set to 8-, 9-, or 10-bit 8 – 10 bits DNL Differential nonlinearity – –1 – +2 LSB INL Integral nonlinearity – –2 – +2 LSB EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB 10-bit resolution 0 12.80 76.80 LSB EGAIN Gain error For any resolution –5 – +5 %FSR IADC Operating current – – 2.10 2.60 mA PSRR Power supply rejection ratio PSRR (VIN > 3.0 V) – 24 – dB PSRR (VIN < 3.0 V) – 30 – dB Power Document Number: 001-77748 Rev. *F Page 19 of 45 CYRF89235 DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 10. DC Analog Mux Bus Specifications Symbol Description Conditions Min Typ Max Units RSW Switch resistance to common analog bus – – – 800 RGND Resistance of initialization switch – to GND – – 800 The maximum pin voltage for measuring RW and RGND is 1.8 V DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11. DC Comparator Specifications Symbol Description Conditions Min Typ Max Units 0.0 – 1.8 V VLPC Low power comparator (LPC) common mode Maximum voltage limited to VIN ILPC LPC supply current – – 10 40 A VOSLPC LPC voltage offset – – 3 30 mV Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: 0 °C TA 70 °C, 1.9 V VIN 3.6 V. Table 12. Comparator User Module Electrical Specifications Symbol Min Typ Max Units 50 mV overdrive – 70 100 ns Offset Valid from 0.2 V to VIN – 0.2 V – 2.5 30 mV Current Average DC current, 50 mV overdrive – 20 80 µA Supply voltage > 2 V Power supply rejection ratio – 80 – dB Supply voltage < 2 V Power supply rejection ratio – 40 – dB – 0 1.5 V tCOMP PSRR Description Comparator response time Input range Document Number: 001-77748 Rev. *F Conditions Page 20 of 45 CYRF89235 DC GPIO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and 0 °C TA 70 °C, or 1.9 V to 2.4 V and 0 °C TA °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design guidance only. Table 13. 2.4 V to 3.0 V DC GPIO Specifications Symbol Description Conditions Typ Max Units RPU Pull-up resistor 4 5.60 8 k VOH1 High output voltage Port 2 or 3 or IOH < 10 A, maximum of 10 mA 4 pins source current in all I/Os VIN – 0.20 – – V VOH2 High output voltage Port 2 or 3 or IOH = 0.2 mA, maximum of 10 mA VIN – 0.40 4 pins source current in all I/Os – – V VOH3 High output voltage Port 0 or 1 IOH < 10 A, maximum of 10 mA pins with LDO regulator Disabled source current in all I/Os for port 1 VIN – 0.20 – – V VOH4 High output voltage Port 0 or 1 IOH = 2 mA, maximum of 10 mA pins with LDO regulator Disabled source current in all I/Os for Port 1 VIN – 0.50 – – V VOH5A High output voltage Port 1 pins with LDO enabled for 1.8 V out IOH < 10 A, VIN > 2.4 V, maximum of 20 mA source current in all I/Os 1.50 1.80 2.10 V VOH6A High output voltage Port 1 pins with LDO enabled for 1.8 V out IOH = 1 mA, VIN > 2.4 V, maximum of 20 mA source current in all I/Os 1.20 – – V VOL Low output voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0 and P1) and 30 mA sink current on odd port pins (for example, P0 and P1) – – 0.75 V VIL Input low voltage – – – 0.72 V VIH Input high voltage – 1.40 – VH Input hysteresis voltage – – 80 – mV IIL Input leakage (absolute value) – – 1 1000 nA CPIN Capacitive load on pins Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT2.5 Input Low Voltage with low Bit3 of IO_CFG1 set to enable low threshold enable set, Enable for threshold voltage of Port1 input Port1 0.7 V – VIHLVT2.5 Input High Voltage with low Bit3 of IO_CFG1 set to enable low threshold enable set, Enable for threshold voltage of Port1 input Port1 1.2 Document Number: 001-77748 Rev. *F – Min V – V Page 21 of 45 CYRF89235 Table 14. 1.9 V to 2.4 V DC GPIO Specifications Symbol Description Conditions Typ Max Units 4 5.60 8 k RPU Pull-up resistor VOH1 High output voltage Port 2 or 3 or IOH = 10 A, maximum of 10 mA VIN – 0.20 4 pins source current in all I/Os – – V VOH2 High output voltage Port 2 or 3 or IOH = 0.5 mA, maximum of 10 mA VIN – 0.50 4 pins source current in all I/Os – – V VOH3 High output voltage Port 0 or 1 IOH = 100 A, maximum of 10 mA VIN – 0.20 pins with LDO regulator Disabled source current in all I/Os for Port 1 – – V VOH4 High output voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA VIN – 0.50 source current in all I/Os – – V VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0 and P1) and 30 mA sink current on odd port pins (for example, P0 and P1) – 0.40 V VIL Input low voltage – – – 0.30 × VIN V VIH Input high voltage – 0.65 × VIN – – V VH Input hysteresis voltage – – 80 – mV IIL Input leakage (absolute value) – – 1 1000 nA CPIN Capacitive load on pins Package and pin dependent temp = 25 °C 0.50 1.70 7 pF Document Number: 001-77748 Rev. *F – Min – Page 22 of 45 CYRF89235 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. DC POR and LVD Specifications Symbol Description Conditions Min Typ Max Units VIN must be greater than or equal to 1.9 V during startup, reset from the XRES pin, or reset from watchdog. – 2.36 2.41 V – 2.60 2.66 – 2.82 2.95 2.40 2.45 2.51 VPOR1 2.36 V selected in PSoC Designer VPOR2 2.60 V selected in PSoC Designer VPOR3 2.82 V selected in PSoC Designer VLVD0 2.45 V selected in PSoC Designer VLVD1 2.71 V selected in PSoC Designer 2.64 2.71 2.78 VLVD2 2.92 V selected in PSoC Designer 2.85 2.92 2.99 VLVD3 3.02 V selected in PSoC Designer 2.95 3.02 3.09 VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 – V Notes 9. Always greater than 50 mV above VPPOR1 voltage for falling supply. 10. Always greater than 50 mV above VPPOR2 voltage for falling supply. 11. Always greater than 50 mV above VPPOR3 voltage for falling supply. Document Number: 001-77748 Rev. *F Page 23 of 45 CYRF89235 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. DC Programming Specifications Symbol Description Conditions Min Typ Max Units VIN Supply voltage for flash write operations – 1.91 – 3.6 V IDDP Supply current during programming or verify – – 5 25 mA VILP Input low voltage during programming or verify See the appropriate DC Analog Mux Bus Specifications on page 20 – – VIL V VIHP Input high voltage during programming or verify See the appropriate DC Analog Mux Bus Specifications on page 20 VIH – – V IILP Input current when Applying VILP Driving internal pull-down resistor to P1 or P1 during programming or verify – – 0.2 mA IIHP Input current when applying VIHP Driving internal pull-down resistor to P1 or P1 during programming or verify – – 1.5 mA VOLP Output low voltage during programming or verify – – 0.75 V VOHP Output high voltage during programming or verify See appropriate DC Analog Mux Bus Specifications on page 20. For VIN > 3 V use VOH4 in Table 6 on page 16. VOH – VIN V FlashENPB Flash write endurance Erase/write cycles per block 50,000 – – – FlashDR Flash data retention Following maximum Flash write cycles; ambient temperature of 55 °C 20 – – Years Document Number: 001-77748 Rev. *F Page 24 of 45 CYRF89235 DC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3, 2.4 V to 3.0 V and 0 °C TA 70 °C, or 1.9 V to 2.4 V and 0 °C TA 70 °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design guidance only. Table 17. DC I2C Specifications Symbol VILI2C VIHI2C Description Input low level Input high level Conditions Min Typ Max Units 3.1 V ≤ VIN ≤ 3.6 V – – 0.25 × VIN V 2.5 V ≤ VIN ≤ 3.0 V – – 0.3 × VIN V 1.9 V ≤ VIN ≤ 2.4 V – – 0.3 × VIN V 1.9 V ≤ VIN ≤ 3.6 V 0.65 × VIN – – V DC Reference Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and 0 °C TA 70 °C, or 1.9 V to 2.4 V and 0 °C TA 70 °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design guidance only. Table 18. DC Reference Buffer Specifications Symbol Description Conditions Min Typ Max Units VRef Reference buffer output 1.9 V to 3.6 V 1 – 1.05 V VRefHi Reference buffer output 1.9 V to 3.6 V 1.2 – 1.25 V DC IDAC Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. DC IDAC Specifications Symbol Description Min Typ Max Units IDAC_DNL Differential nonlinearity –4.5 – +4.5 LSB IDAC_INL Integral nonlinearity –5 – +5 LSB IDAC_Gain (Source) Range = 0.5x 6.64 – 22.46 µA Range = 1x 14.5 – 47.8 µA Range = 2x 42.7 – 92.3 µA Notes DAC setting = 128 dec. Range = 4x 91.1 – 170 µA DAC setting = 128 dec. Range = 8x 184.5 – 426.9 µA DAC setting = 128 dec. Document Number: 001-77748 Rev. *F Page 25 of 45 CYRF89235 AC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20. AC Chip-Level Specifications Symbol Description Conditions Min Typ Max Units 24 25.2 MHz FIMO24 IMO frequency at 24 MHz Setting – 22.8 FIMO12 IMO frequency at 12 MHz setting – 11.4 12 12.6 MHz FIMO6 IMO frequency at 6 MHz setting – 5.7 6.0 6.3 MHz FCPU CPU frequency – 0.75 – 25.20 MHz F32K1 ILO frequency – 19 32 50 kHz F32K_U ILO untrimmed frequency – 13 32 82 kHz DCIMO Duty cycle of IMO – 40 50 60 % DCILO ILO duty cycle – 40 50 60 % SRPOWER_UP Power supply slew rate VIN slew rate during power-up – – 250 V/ms tXRST External reset pulse width at power-up After supply voltage is valid 1 – – ms tXRST2 External reset pulse width after power-up Applies after part has booted 10 – – s tOS Startup time of ECO – – 1 – s tJIT_IMO N=32 6 MHz IMO cycle-to-cycle jitter (RMS) – 0.7 6.7 ns 6 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) – 4.3 29.3 ns 6 MHz IMO period jitter (RMS) – 0.7 3.3 ns 12 MHz IMO cycle-to-cycle jitter (RMS) – 0.5 5.2 ns 12 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) – 2.3 5.6 ns 12 MHz IMO period jitter (RMS) – 0.4 2.6 ns 24 MHz IMO cycle-to-cycle jitter (RMS) – 1.0 8.7 ns 24 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) – 1.4 6.0 ns 24 MHz IMO period jitter (RMS) – 0.6 4.0 ns Document Number: 001-77748 Rev. *F Page 26 of 45 CYRF89235 AC USB Data Timings Specifications Table 21. AC Characteristics – USB Data Timings Min Typ Max Units tDRATE Symbol Full speed data rate Description Average bit rate Conditions 12 – 0.25% 12 12 + 0.25% MHz tJR1 Receiver jitter tolerance To next transition –18.5 – 18.5 ns tJR2 Receiver jitter tolerance To pair transition –9.0 – 9 ns tDJ1 FS Driver jitter To next transition –3.5 – 3.5 ns tDJ2 FS Driver jitter To pair transition –4.0 – 4.0 ns tFDEOP Source jitter for differential transition To SE0 transition –2.0 – 5 ns tFEOPT Source SE0 interval of EOP – 160.0 – 175 ns tFEOPR Receiver SE0 interval of EOP – 82.0 – – ns tFST Width of SE0 interval during differential transition – – – 14 ns Min Typ Max Units AC USB Driver Specifications Table 22. AC Characteristics – USB Driver Symbol Description Conditions tFR Transition rise time 50 pF 4 – 20 ns tFF Transition fall time 50 pF 4 – 20 ns tFRFM Rise/fall time matching – 90 – 111 % VCRS Output signal crossover voltage – 1.30 – 2.00 V Document Number: 001-77748 Rev. *F Page 27 of 45 CYRF89235 AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. AC GPIO Specifications Symbol FGPIO Description GPIO operating frequency Conditions Min Typ Normal strong mode Port 0, 1 0 – 0 – Max Units 6 MHz for 1.9 V <VIN < 2.40 V 12 MHz for 2.40 V < VIN< 3.6 V MHz MHz tRISE23 Rise time, strong mode, Cload = 50 pF Port 2 or 3 or 4 pins VIN = 3.0 to 3.6 V, 10% to 90% 15 – 80 ns tRISE23L Rise time, strong mode low supply, Cload = 50 pF, Port 2 or 3 or 4 pins VIN = 1.9 to 3.0 V, 10% to 90% 15 – 80 ns tRISE01 Rise time, strong mode, Cload = 50 pF, Ports 0 or 1 VIN = 3.0 to 3.6 V, 10% to 90% LDO enabled or disabled 10 – 50 ns tRISE01L Rise time, strong mode low supply, Cload = 50 pF, Ports 0 or 1 VIN = 1.9 to 3.0 V, 10% to 90% LDO enabled or disabled 10 – 80 ns tFALL Fall time, strong mode, Cload = 50 pF, all ports VIN = 3.0 to 3.6 V, 10% to 90% 10 – 50 ns tFALLL Fall time, strong mode low supply, Cload = 50 pF, all ports VIN = 1.9 to 3.0 V, 10% to 90% 10 – 70 ns Figure 10. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% tRISE23 tRISE01 tRISE23L tRISE01L Document Number: 001-77748 Rev. *F tFALL tFALLL Page 28 of 45 CYRF89235 AC Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 24. AC Low Power Comparator Specifications Symbol tLPC Description Comparator response time, 50 mV overdrive Conditions Min Typ Max Units 50 mV overdrive does not include offset voltage. – – 100 ns AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 25. AC External Clock Specifications Symbol FOSCEXT Min Typ Max Units Frequency (external oscillator frequency) Description – 0.75 – 25.20 MHz High period – 20.60 – 5300 ns Low period – 20.60 – – ns Power-up IMO to switch – 150 – – s Document Number: 001-77748 Rev. *F Conditions Page 29 of 45 CYRF89235 AC Programming Specifications The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 26. AC Programming Specifications Symbol Description Conditions Min Typ Max Units tRSCLK Rise time of SCLK – 1 – 20 ns tFSCLK Fall time of SCLK – 1 – 20 ns tSSCLK Data setup time to falling edge of SCLK – 40 – – ns tHSCLK Data hold time from falling edge of SCLK – 40 – – ns FSCLK Frequency of SCLK – 0 – 8 MHz tERASEB Flash erase time (block) – – – 18 ms tWRITE Flash block write time – – – 25 ms tDSCLK3 Data out delay from falling edge of SCLK 3.0 VDD 3.6 – – 85 ns tDSCLK2 Data out delay from falling edge of SCLK 1.9 VDD 3.0 – – 130 ns tXRST3 External reset pulse width after power-up Required to enter programming mode when coming out of sleep 300 – – s tXRES XRES pulse length – 300 – – s tVDDWAIT VDD stable to wait-and-poll hold off – 0.1 – 1 ms tVDDXRES VDD stable to XRES assertion delay – 14.27 – – ms tPOLL SDATA high pulse time – 0.01 – 200 ms tACQ “Key window” time after a VDD ramp acquire event, based on 256 ILO clocks. – 3.20 – 19.60 ms tXRESINI “Key window” time after an XRES event, based on 8 ILO clocks – 98 – 615 s Figure 11. AC Waveform SCLK (P1) TFSCLK TRSCLK SDATA (P1) TSSCLK Document Number: 001-77748 Rev. *F THSCLK TDSCLK Page 30 of 45 CYRF89235 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 27. AC Characteristics of the I2C SDA and SCL Pins Symbol Description Standard Mode Fast Mode Units Min Max Min Max 0 100 0 400 kHz fSCL SCL clock frequency tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 – 0.6 – µs tLOW LOW period of the SCL clock 4.7 – 1.3 – µs tHIGH HIGH Period of the SCL clock 4.0 – 0.6 – µs tSU;STA Setup time for a repeated START condition 4.7 – 0.6 – µs tHD;DAT Data hold time 0 3.45 0 0.90 µs – ns – µs tSU;DAT Data setup time 250 – 100 tSU;STO Setup time for STOP condition 4.0 – 0.6 tBUF Bus free time between a STOP and START condition 4.7 – 1.3 – µs tSP Pulse width of spikes are suppressed by the input filter – – 0 50 ns Figure 12. Definition for Timing for Fast/Standard Mode on the I2C Bus Note 12. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-77748 Rev. *F Page 31 of 45 CYRF89235 SPI Master AC Specifications Table 28. SPI Master AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description VIN 2.4 V VIN < 2.4 V Conditions – – – – 6 3 MHz MHz DC SCLK duty cycle – – 50 – % tSETUP MISO to SCLK setup time VIN 2.4 V VIN < 2.4 V 60 100 – – – – ns ns tHOLD SCLK to MISO hold time – 40 – – ns tOUT_VAL SCLK to MOSI valid time – – – 40 ns tOUT_HIGH MOSI high time – 40 – – ns Figure 13. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSB MSB TOUT_SU TOUT_H MOSI (output) Figure 14. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD TOUT_SU MOSI (output) Document Number: 001-77748 Rev. *F LSB MSB TOUT_H MSB LSB Page 32 of 45 CYRF89235 SPI Slave AC Specifications Table 29. SPI Slave AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description – Conditions – – 4 MHz tLOW SCLK low time – 42 – – ns tHIGH SCLK high time – 42 – – ns tSETUP MOSI to SCLK setup time – 30 – – ns tHOLD SCLK to MOSI hold time – 50 – – ns tSS_MISO SS high to MISO valid – – – 153 ns tSCLK_MISO SCLK to MISO valid – – – 125 ns tSS_HIGH SS high time – 50 – – ns tSS_CLK Time from SS low to first SCLK – 2/SCLK – – ns tCLK_SS Time from last SCLK to SS high – 2/SCLK – – ns Figure 15. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TCLK_SS TSS_CLK TSS_HIGH /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) Document Number: 001-77748 Rev. *F THOLD MSB LSB Page 33 of 45 CYRF89235 Figure 16. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSB TSETUP MOSI (input) Document Number: 001-77748 Rev. *F LSB THOLD MSB LSB Page 34 of 45 CYRF89235 Electrical Specifications - RF Section Symbol Description Min Typ Max Units Test Condition and Notes 1.9 – 3.6 VDC – 18.5 – mA Transmit power PA2. – 13.7 – mA Transmit power PA12. Supply voltage VIN DC power supply voltage range Input to VIN pins Current consumption IDD_TX2 Current consumption – Tx IDD_TX12 IDD_RX Current consumption – Rx – 18 – mA IDD_IDLE1 Current consumption – idle – 1.1 – mA IDD_SLPx Current consumption – sleep – 1 – µA Temperature = +25 °C. Using firmware sleep patch. Register 27 = 0x1200, for VIN ≥ 3.00 VDC only IDD_SLPr – 8 – µA Temperature = +25 °C; using firmware sleep patch Register 27 = 0x4200. IDD_SLPh – 38 – µA Temperature = +70 °C ‘C’ grade part; using firmware sleep patch Register 27 = 0x4200 VIH Logic input high 0.8 VIN – 1.2 VIN V VIL Logic input low 0 – 0.8 V I_LEAK_IN Input leakage current – – 10 µA VOH Logic output high 0.8 VIN – – V IOH = 100 µA source VOL Logic output low – – 0.4 V IOL = 100 µA sink I_LEAK_OUT Output leakage current – – 10 µA MISO in tristate T_RISE_OUT Rise/fall time (SPI MISO) – 8 25 ns 7 pF cap. load T_RISE_IN Rise/fall time (SPI MOSI) – – 25 ns Tr_spi CLK rise, fall time (SPI) – – 25 ns F_OP Operating frequency range 2400 – 2482 MHz VSWR_I Antenna port mismatch (Z0 = 50 ) – <2:1 – VSWR Receive mode. Measured using LC matching circuit – <2:1 – VSWR Transmit mode. Measured using LC matching circuit VSWR_O Receive section Document Number: 001-77748 Rev. *F Requirement for error-free register reading, writing. Usage on-the-air is subject to local regulatory agency restrictions regarding operating frequency. Measured using LC matching circuit for BER 0.1% Page 35 of 45 CYRF89235 Electrical Specifications - RF Section (continued) Symbol Min Typ Max Units Test Condition and Notes – –87 – dBm Room temperature only 0-ppm crystal frequency error. RxStemp – –84 – dBm Over temperature; 0-ppm crystal frequency error. RxSppm – –84 – dBm Room temperature only 80-ppm total frequency error (± 40-ppm crystal frequency error, each end of RF link) RxStemp+ppm – –80 – dBm Over temperature; 80-ppm total frequency error (± 40-ppm crystal frequency error, each end of RF link) –20 0 – dBm Room temperature only – 1 – µs RxSbase Description Receiver sensitivity (FEC off) Rxmax-sig Maximum usable signal Ts Data (Symbol) rate For BER 0.1%. Room temperature only. Minimum Carrier/Interference ratio CI_cochannel Co-channel interference – +9 – dB –60-dBm desired signal CI_1 Adjacent channel interference, 1-MHz offset – +6 – dB –60-dBm desired signal CI_2 Adjacent channel interference, 2-MHz offset – –12 – dB –60-dBm desired signal CI_3 Adjacent channel interference, 3-MHz offset – –24 – dB –67-dBm desired signal OBB Out-of-band blocking – –27 – dBm Transmit section PAVH RF output power PAVL 30 MHz to 12.75 GHz Measured with ACX BF2520 ceramic filter on ant. pin. –67-dBm desired signal, BER 0.1%. Room temperature only. Measured using a LC matching circuit – +1 – dBm PA0 (PA_GN = 0, Reg9 = 0x1820). Room temperature only – –11.2 – dBm PA12 (PA_GN = 12, Reg9 = 0x1E20). Room temperature only. TxPfx2 Second harmonic – –45 – dBm Measured using a LC matching circuit. Room temperature only. TxPfx3 Third and higher harmonics – –45 – dBm Measured using a LC matching circuit. Room temperature only. Df1avg – 263 – kHz Modulation pattern: 11110000... Df2avg – 255 – kHz Modulation pattern: 10101010... Modulation characteristics In-band spurious emission IBS_2 2-MHz offset – – –20 dBm IBS_3 3-MHz offset – – –30 dBm IBS_4 4-MHz offset – –30 – dBm Document Number: 001-77748 Rev. *F Page 36 of 45 CYRF89235 Electrical Specifications - RF Section (continued) Symbol Description Min Typ Max Units Test Condition and Notes 1 – MHz –75 – dBc/Hz 100-kHz offset –105 – dBc/Hz 1-MHz offset –40 – +40 ppm – 100 150 µs Settle to within 30 kHz of final value. AutoCAL off. – 250 350 µs Settle to within 30 kHz of final value. AutoCAL on. – 0.17 0.3 V Measured during receive state RF VCO and PLL section Fstep Channel (Step) size L100k SSB phase noise L1M dFX0 Crystal oscillator frequency error THOP RF PLL settling time THOP_AC Relative to 12-MHz crystal reference frequency LDO voltage regulator section VDO Dropout voltage Document Number: 001-77748 Rev. *F Page 37 of 45 CYRF89235 Initialization Timing Requirements Table 30. Initialization Timing Requirements Timing Parameter Min Max Unit Notes TRSU – 30 / 150 ms 30 ms Reset setup time necessary to ensure complete Reset for VIN = 6.5 mV/s, 150 ms Reset setup time necessary to ensure complete Reset for VIN = 2 mV/s TRPW 1 10 µs Reset pulse width necessary to ensure complete reset TCMIN 3 – ms Minimum recommended crystal oscillator and APLL settling time TVIN – 6.5 / 2 mV/s Maximum ramp time for VIN, measured from 0 to 100% of final voltage. For example, if VIN= 3.3 V, the max ramp time is 6.5 × 3.3 = 21.45 ms. If VIN= 1.9 V, the max ramp time = 6.5 × 1.9 = 12.35 ms. Reset setup time necessary to ensure complete Reset for VIN = 6.5mV/s Reset setup time necessary to ensure complete Reset for VIN = 6.5mV/s Reset setup time necessary to ensure complete Reset for VIN = 6.5mV/s Figure 17. Initialization Flowchart Initialize CYRF89235 at power-up MCU generates negative- going RST_n pulse Wait Crystal Enable Time Initialize Registers, beginning with Reg Initialization Done RST_n pulls up along with Vin Document Number: 001-77748 Rev. *F Page 38 of 45 CYRF89235 SPI Timing Requirements Table 31. SPI Timing Requirements Timing Parameter Min Max Unit Notes TSSS 20 – ns Setup time from assertion of SPI_SS to CLK edge TSSH 200 – ns Hold time required deassertion of SPI_SS TSCKH 40 – ns CLK minimum high time TSCKL 40 – ns CLK minimum low time TSCK 83 – ns Maximum CLK clock is 12 MHz TSSU 30 – ns MOSI setup time TSHD 10 – ns MOSI hold time TSS_SU 10 – ns Before SPI_SS enable, CLK hold low time requirement TSS_HD 200 – ns Minimum SPI inactive time TSDO – 35 ns MISO setup time, ready to read TSDO1 – 5 ns If MISO is configured as tristate, MISO assertion time TSDO2 – 250 ns If MISO is configured as tristate, MISO deassertion time T1 Min_R50 350 – ns When reading register 50 (FIFO) T1 Min 83 – ns When writing Register 50 (FIFO), or reading/writing any registers other than register 50. Figure 18. Power-on and Register Programming Sequence TVIN VIN RST_n Clock stable BRCLK Clock unstable SPI_SS SPI Activity TRPW TRSU ■ TCMIN Write Reg= 0x4200 (not drawn to scale) After register initialization, CYRF89235 is ready to transmit or receive. Document Number: 001-77748 Rev. *F Page 39 of 45 CYRF89235 Packaging Information This section illustrates the packaging specifications for the PRoC-USB device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. Packaging Dimensions Figure 19. 40-pin QFN (6 × 6 × 1.0 mm) LT40B 3.5 × 3.5 mm E-Pad (Sawn) Package Outline, 001-13190 001-13190 *H Document Number: 001-77748 Rev. *F Page 40 of 45 CYRF89235 Thermal Impedances Table 32. Thermal Impedances per Package Typical JA 27 °C/W Package 40-pin QFN  Typical JC 34 °C/W Capacitance on Crystal Pins Table 33. Typical Package Capacitance on Crystal Pins Package Package Capacitance 40-pin QFN 3.6 pF Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 34. Solder Reflow Peak Temperature Package 40-pin QFN Minimum Peak Temperature  Maximum Peak Temperature 260 265 Notes 13. TJ = TA + Power x JA. 14. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane. 15. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-77748 Rev. *F Page 41 of 45 CYRF89235 Ordering Information Table 35. Ordering Information Ordering Code Package Information CYRF89235-40LTXC 40-pin QFN (6 × 6 mm) Flash (KB) SRAM (KB) No. of GPIOs 32 2 13 Ordering Code Definitions CY RF 89 235 40 LT X C Thermal Rating C = Commercial , I = Industrial , E = Extended X = Lead-Free, X absent = Leaded Package : LT = QFN 40 pin 235 = PRoC-USB Family Code 89 = Wireless Marketing code : RF = Wireless ( radio frequency ) product family Company ID : CY = Cypress Document Number: 001-77748 Rev. *F Page 42 of 45 CYRF89235 Acronyms Acronym Document Conventions Description API application programming interface CPU central processing unit GPIO general purpose I/O ICE in-circuit emulator ILO internal lowspeed oscillator IMO internal main oscillator I/O input/output LSb least significant bit LVD low voltage detect MSb most significant bit POR power-on reset PPOR precision power-on reset PSoC programmable system-on-chip SLIMO slow IMO SRAM static random access memory Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms W mA ms mV nA ns nV W pA pF pp ppm ps sps V Unit of Measure degree Celsius decibels femtofarad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolt microvolts root-mean-square microwatts milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volt Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are decimal. Document Number: 001-77748 Rev. *F Page 43 of 45 CYRF89235 Document History Page Document Title: CYRF89235, PRoC™ USB Document Number: 001-77748 Rev. ECN No. Orig. of Change Submission Date ** 3554967 ANTG 04/03/2012 New data sheet. *A 3605878 ANTG 05/02/2012 Modified title. Updated status “Company Confidential” of the datasheet. Changed “PRoC NL Dongle” to “PRoC-USB” everywhere in the datasheet. *B 3714928 AKHL 08/16/2012 Major text update. Added Electrical Specifications - RF Section. *C 3747532 AKHL 09/18/2012 Removed “Company Confidential” tag in the header. Replaced package diagram spec with 001-13190. *D 3784571 AKHL 10/26/2012 Updated Functional Overview (Added Transmit Power Control). Updated Development Tools (Updated PSoC Designer Software Subsystems (Added Device Programmers)). Updated Electrical Specifications - RF Section (Replaced CYRF8935 with CYRF89235 in Figure 17 and also in the last bullet point below Figure 18). Updated Packaging Information (No update in package diagram, updated Thermal Impedances (Updated Table 32)). Updated in new template. *E 3872679 AKHL 01/19/2013 Updated PRoC-USB Features (Replaced “Up to 37 general-purpose I/Os (GPIOs)” with “Up to 13 general-purpose I/Os (GPIOs)”). Updated Electrical Specifications (Updated DC Chip-Level Specifications (Changed maximum value of VINUSB parameter from 3.60 V to 3.45 V in Table 7)). *F 3982770 AKHL 05/15/2013 Updated PRoC-USB Features. Description of Change Updated PRoC-USB Logical Block Diagram. Updated Functional Overview: Updated WirelessUSB-NL Subsystem (Updated Figure 6). Updated Transmit Power Control (Updated Table 1). Updated Electrical Specifications: Updated Absolute Maximum Ratings (Updated Table 5). Updated Operating Temperature (Updated Table 6). Updated DC Chip-Level Specifications (Updated Table 7). Updated DC IDAC Specifications (Updated Table 19). Updated Electrical Specifications - RF Section: Updated SPI Timing Requirements (Updated Table 31). Updated Packaging Information: No change in Package Diagram revision. Removed “Package Handling”. Updated Capacitance on Crystal Pins (Updated Table 33). Updated Solder Reflow Peak Temperature (Updated Table 34). Updated Ordering Information: No change in part numbers. Added Ordering Code Definitions. Document Number: 001-77748 Rev. *F Page 44 of 45 CYRF89235 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-77748 Rev. *F Revised May 15, 2013 Page 45 of 45 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.