AN96614 Migrating from SPI EEPROM to Cypress's SPI F-RAM™ Author: Shivendra Singh Associated Project: No Associated Part Family: SPI F-RAM Software Version: None Related Application Notes: AN304, AN87352 To get the latest version of this application note, please visit www.cypress.com/go/AN96614 AN96614 provides an overview about advantages and differences to be considered when migrating from a SPI EEPROM to Cypress’s high-reliability and energy-efficient SPI F-RAM solution. Contents 1 2 Introduction ...............................................................1 Benefits of SPI F-RAM over EEPROM .....................2 2.1 Faster Memory.................................................2 2.2 Easier Design ..................................................2 2.3 Data Security ...................................................2 2.4 Additional Features ..........................................2 3 Migrating from SPI EEPROM to SPI F-RAM ............2 3.1 Pin and Package Compatibility ........................2 3.2 Command (OPCODE) Compatibility ................4 3.3 Status Register Compatibility ...........................5 3.4 Hold Compatibility ............................................6 1 3.5 Parameter Compatibility .................................. 7 4 Firmware Compatibility ............................................. 8 4.1 Multiple Pages in EEPROMs versus Single Page in F-RAM ..................................... 8 4.2 Page Write Delay ............................................. 9 4.3 / WIP Bit in Status Register ..................... 9 5 Summary ................................................................ 10 6 Related Documents ................................................ 10 6.1 Application Notes ........................................... 10 Document History............................................................ 11 Worldwide Sales and Design Support ............................. 12 Introduction EEPROMs are frequently used for nonvolatile storage of a system’s data. However, a slow nonvolatile write performance and limited write endurance of the EEPROMs limit their usages in systems that need to execute frequent writes to the nonvolatile memory at bus speed. Many system designs have tried to resolve issues associated with EEPROMs by using a wear-leveling technique to increase the effective endurance, but at the cost of increased EEPROM density and software overheads. The other alternative method to save critical system data is to store data in the scratchpad RAM and then transfer the stored data into the nonvolatile memory, such as EEPROMs or flash, at power down by using a backup power source. Both of these methods are highly inefficient because of increased number of components, board space, hardware design complexities, and the software overheads. Cypress’s SPI F-RAM is a serial, nonvolatile memory employing an advanced ferroelectric process and offers the world’s most energy-efficient, high-performance, and high-reliability nonvolatile RAM solution. Cypress’s SPI F-RAMs are available in both industrial and automotive grade temperatures. 14 Cypress’s F-RAM has fast random access SRAM memory cells and provides virtually infinite (10 ) read/write endurance cycles, orders of magnitude higher than an EEPROM. The F-RAM performs write operations at the bus speed without incurring any write delays (No elay™) unlike serial EEP OMs and flash memories. ata is directly written into the F-RAM array; the next bus cycle can start immediately without checking the readiness of the device before subsequent access. www.cypress.com Document No. 001-96614 Rev. ** 1 Migrating from SPI EEPROM to Cypress's SPI F- AM™ The serial SPI F-RAM devices are available as drop-in replacements to the standard SPI EEPROM devices. This application note shows the differences between an industry-standard SPI EEP OM and Cypress’s SPI F-RAM solution. These differences need to be considered when migrating from an SPI EEPROM-based solution to Cypress’s SPI F-RAM solution. This application note references the M95M01 and AT256B SPI EEPROM datasheets for comparison. For more details on SPI F-RAM designs, refer to the application note AN304 - SPI Guide for F- AM™. For more details on the benefits of Cypress’s F-RAM over a serial EEPROM, refer to the application note AN87352–F- AM™ for Smart E-Meters. 2 Benefits of SPI F-RAM over EEPROM 2.1 Faster Memory 2.2 14 Virtually infinite (10 ) read/write endurance cycles do not require wear leveling Available in industry-standard packages Reliable, advanced ferroelectric process No requirement of a battery or capacitor backup to store the last moment data Additional Features 3 No software overhead for managing page boundary as with EEPROM Data Security 2.4 Full memory write at bus speed without any internal page program delay after each page write. Easier Design 2.3 Random access: No page reads/writes needed. Cypress’s F- AM is world’s most energy-efficient, fast nonvolatile RAM 151 years of data retention at 65 ºC Pb-free technology Migrating from SPI EEPROM to SPI F-RAM Cypress’s SPI F-RAMs are available in two industry-standard packages: 8-pin SOIC and 8-pin DFN. These standard and versatile package options make Cypress’s SPI F-RAMs drop-in replacements for the majority of the EEPROMs on the same footprint without compromising the system’s performance. In addition, Cypress’s F-RAM solution TM provides performance advantages such as higher data throughput, NoDelay write, and energy-efficient operation. The following sections highlight all key differences and compatibilities between an SPI EEPROM and an SPI F-RAM. 3.1 Pin and Package Compatibility Cypress’s SPI F-RAMs are pin- and package-compatible with SPI EEPROMs. Table 1 shows the pin mapping and Table 2 shows the package comparison of SPI EEPROMs and SPI F-RAMs. Table 1. SPI EEPROM and SPI F-RAM Pin Mapping Pin Description SPI EEPROM Cypress's SPI F-RAM Serial clock SS / S / CS C/SCK CS SCK Serial data input Serial data output D/SI Q/SO SI SO Chip select www.cypress.com Pin Name Document No. 001-96614 Rev. ** 2 Migrating from SPI EEPROM to Cypress's SPI F- AM™ Pin Name Pin Description SPI EEPROM Write protect Hold Power supply Ground Cypress's SPI F-RAM P P O VCC/VDD VSS/GND O VDD VSS / Table 2. SPI EEPROM and SPI F-RAM Package Comparison Feature/Function SPI EEPROM DFN EXPOSED PAD No connect Package options 8-pin DFN, 8-pin SOIC (150 mils), 8-pin SOIC (208 mils), 8-pin PDIP, 8-pin TSSOP, 8-pin dBGA, 8-pin UDFN, 8-WLCSP, 8-pin MSOP SPI F-RAM Comments No connect The EXPOSED PAD of F-RAM 8-pin DFN package is an NC (No connect) pad; therefore, it can be either floating or connected to VSS/VDD. Cypress doesn’t recommend soldering the F-RAM DFN EXPOSED PAD on the PCB. 8-pin DFN, 8-pin SOIC (150 mils), 8-pin SOIC (208 mils), The standard 8-pin DFN and 8-pin SOIC packages of EEPROMs can be replaced by the SPI F-RAMs. Other SPI EEPROM packages are incompatible with the SPI F-RAM and so will require changes to the PCB. Figure 1. SPI F-RAM 8-pin DFN (4 mm × 4.5 mm × 0.75 mm) Package Outline EXPOSED PAD The SPI F-RAM EXPOSED PAD is not connected to the die hence should be left floating. Ensure that the EXPOSED PAD of the SPI F-RAM DFN package is not soldered on the PCB when migrating to SPI F-RAM from SPI EEPROM. Doing so will cause the SPI F-RAM die to be exposed to excessive heat, which can result in bit failures and margin loss. www.cypress.com Document No. 001-96614 Rev. ** 3 Migrating from SPI EEPROM to Cypress's SPI F- AM™ 3.2 Command (OPCODE) Compatibility Table 3 shows the list of opcodes supported in SPI EEPROMs and SPI F-RAMs. Opcodes specific to EEPROM cell operations such as RDID (ABh), PE0 (42h), SE0 (D8h), which are shown in Table 3, are don’t care commands for SPI F-RAMs; these are ignored by the SPI F-RAM when executed. The SPI F-RAM cannot replace the SPI EEPROM that has these special features if the application uses these features. Table 3. OPCODE Comparison Command OPCODE (Hex) Command Description SPI EEPROM SPI F-RAM WREN (06h) Set write enable latch √ √ WRDI (04h) Reset write enable latch √ √ RDSR (05h) Read Status Register √ √ WRSR (01h) Write Status Register √ √ READ (03h) Read memory data √ √ WRITE (02h) Write memory data √ √ √ Enter sleep mode √ √ Identical functionality Read device ID X √ Read serial number Release from deep power down (Not available as standard instruction) Page erase X √ √ X √ X Sector erase Reads the page dedicated to identification Writes the page dedicated to identification Reads the lock status of the identification page Lock the identification page in read-only mode √ X √ X √ X √ X √ X SLEEP (B9h) RDID (9Fh) SNR (C3h) SE0 (D8h) RDID (83h) WRID (82h) RDLS (83h) LID (82h) www.cypress.com Advantage: F- AM doesn’t require a nonvolatile write delay of 5 ms after the Status Register write. Identical functionality. Advantage: The address counter in the SPI EEPROM burst write rolls over at the EEPROM page boundary. EEPROM requires a nonvolatile write delay of 5 ms after every byte/page write. X Fast read memory data PE0 (42h) Identical functionality. The SPI F-RAM burst write operation allows writing the entire memory at bus speed without any write delay. The address counter rolls over at the last memory location. Not supported in EEPROM FSTRD (0Bh) RDID (ABh) Comments Document No. 001-96614 Rev. ** Not supported in EEPROM. These commands are not the standard SPI EEPROM commands. These commands are supported only in specific EEPROMs. These commands are not supported in the SPI F-RAMs. 4 Migrating from SPI EEPROM to Cypress's SPI F- AM™ 3.3 Status Register Compatibility The Status Register access in the SPI EEPROM and the SPI-FRAM are identical except that EEPROMs allow reading the Status Register in a loop without resending the Read Status Register command (RDSR). The host controller can poll the EEPROM Status Register in a loop to determine the “ eady” or the “ rite In Progress” status ( / WIP). In contrast, the SPI F-RAM is always ready for the next instruction immediately after the ongoing instruction completes; therefore, in any case, the SPI F-RAM does not need reading the Status Register continuously. This will be an improvement in the firmware when using the SPI F-RAM. Reading the SPI F-RAM Status Register will always return a “ eady” status. hen migrating from the SPI EEPROM to SPI F-RAM, the firmware must ensure that either it reads only one byte per Status Register read command, or if it reads multiple bytes then firmware ignores all bytes except the first byte. Table 4 shows the Status Register bits definitions for SPI EEPROMs and SPI F-RAMs and their compatibilities. Table 4. Status Register Comparison Status Register SPI EEPROM Bit0 Bit1 / WIP WEL SPI F-RAM Comments on’t Care (0) The SPI EEP OM sets this bit to ‘1’ when it is busy during a page write operation. The SPI F- AM always returns ‘0’ indicating it is ready. Therefore, migrating to the SPI F-RAM does not require any firmware change. WEL Bit2 Bit3 Bit4 BP0 BP1 on’t Care (0) BP0 BP1 on’t Care (0) Bit5 on’t Care (0) on’t Care (0) Bit6 on’t Care (0) on’t Care (0/1) Bit7 SRWD WPEN Identical behavior. This bit is the read-only bit in the SPI F-RAM. Some SPI F- AMs return ‘0’ upon read. (Example: FM25C160B) Some SPI F- AMs return ‘1’ upon read. (Example: FM25V20A) Identical behavior. Note: Bits 4-6 are ‘don’t care’ bits. The default value of these three bits can be ignored when migrating from the SPI EEPROM to the SPI F-RAM. Figure 2. SPI EEPROM Status Register Read Continue reading returns valid data www.cypress.com Document No. 001-96614 Rev. ** 5 Migrating from SPI EEPROM to Cypress's SPI F- AM™ Figure 3. SPI F-RAM Status Register Read 3.4 First byte read returns valid data Hold Compatibility Continue reading will return invalid data The O pin can be used to interrupt a serial operation without aborting it. If the bus master pulls the O pin LOW while SCK is LOW, the current operation will pause. Taking the O pin HIGH while SCK is LOW will resume the paused operation. The transitions of O must occur while SCK is LOW. The following are the differences in the O behavior between the SPI EEPROMs and the SPI F-RAM: The SPI F-RAM allows toggling the SCK and the CS pin during a hold state, as shown in Figure 4. Some SPI EEPROMs allow entering the hold state by toggling the O pin LOW when the CS is LOW and the SCK is HIGH. Similarly, these devices allow exiting the hold state by toggling the O pin HIGH when the CS is LOW and the SCK is HIGH. See Figure 5. Some SPI EEPROMs do not allow CS toggling in the hold state. Toggling the CS during hold can reset the communication in these devices. Figure 4. SPI EEPROM O Timing Toggle the O pin to enter and exit the hold state in all SPI EEPROMs. www.cypress.com Document No. 001-96614 Rev. ** Some SPI EEPROMs also allow O pin toggle when the SCK is HIGH, to enter and exit the hold state. 6 Migrating from SPI EEPROM to Cypress's SPI F- AM™ Figure 5. SPI F-RAM O Timing SPI F-RAMs allow SCK and CS toggling in the hold state (without exiting the hold state). SPI F-RAMs allow O pin toggle when SCK is LOW to enter and exit the hold state. 3.5 Parameter Compatibility Table 5 summarizes the key parameters that need to be evaluated for system-level compatibility when migrating from the SPI EEPROM to Cypress’s SPI F-RAM. Table 5. Key Parameters Checklist Parameter Description SPI EEPROM SPI F-RAM Comments DC Parameters VDD Power supply voltage 1.5 V to 3.6 V 1.7 V to 5.5 V 2.0 V to 5.5 V VIH Input HIGH voltage Varies 0.7 × VDD to VDD + 0.3 V VIL Input LOW voltage Varies -0.3 V to 0.3 × VDD 2.4 V (min), IOH = -1 mA; VOH Output HIGH voltage Varies VDD - 0.2 V (min), IOH = -100 µA 0.4 V (max), IOL = +2 mA; VOL Output LOW voltage Varies 0.2 V (max), IOL = +150 µA www.cypress.com Document No. 001-96614 Rev. ** The SPI EEPROMs support a wider operating voltage range. When migrating to the SPI F-RAM, the system must ensure that the SPI F-RAM operating voltage is within its operating range. The SPI F-RAM follows CMOS logic standard. System must ensure that the logic levels are within operating range of both the SPI host and the SPI F-RAM for proper operation. The SPI F-RAM output driver supports standard output drive strength which makes it compatible with majority of the host controllers. Systems must ensure that the logic levels are within operating range of both the SPI host and SPI F-RAM for proper operation. 7 Migrating from SPI EEPROM to Cypress's SPI F- AM™ Parameter Description SPI EEPROM SPI F-RAM Comments AC Parameters fSCK SPI clock frequency Up to 20 MHz Up to 40 MHz Varies 30 to 50 µs/V Varies 30 to 100 µs/V Migrating from the SPI EEPROM to SPI F-RAM does not require firmware changes. However, because the SPI F-RAM supports a higher access speed, firmware upgrades can improve the data throughput when using the SPI F-RAM. Power Parameters tVR tVF VDD power-up ramp rate VDD power-down ramp rate When migrating to the SPI F-RAM, the system must ensure that the VDD power ramp rate is within the spec of the SPI F-RAM, Figure 6. Other device parameters such as device current in different operating modes, output load, start-up time, power ramp (power-up and power-down), ESD profile and packages that differ between the SPI EEPROM and SPI F-RAM can warrant some system-level analysis before replacing the SPI EEPROM with the SPI F-RAM. Figure 6. SPI F-RAM Power Cycle Timing 4 Firmware Compatibility The SPI host controller firmware for the SPI EEPROM access will work as-is for the SPI F-RAM except for the unsupported features/opcodes. This section discusses various operations in EEPROMs that can be improved in the system by firmware updates when migrating to the SPI F-RAM solution. 4.1 Multiple Pages in EEPROMs versus Single Page in F-RAM th EEPROMs are written or programmed on a page-by-page basis. A typical page size of an EEPROM device is 1/512 of the memory size. This means that to write the full EEPROM memory, the host controller needs to initiate 512 pagewrite operations. The host controller also needs to track the count of the total data bytes written in an individual page to prevent a counter roll over. The F-RAM does not support page architecture; therefore, the entire memory array can be treated as one page. The entire F-RAM array can be written in the burst mode with a single write command. Once the internal counter reaches the last F-RAM location, the counter rolls over to the start address 0h. Because the SPI F-RAM the write operation contains a single page, the host controller is required to keep track of just one counter for the SPI F-RAM, as opposed to tracking multiple counters for the page count and the byte count in a page. The SPI F-RAM simplifies firmware design by reducing the number of execution steps. Figure 7 demonstrates writing in SPI EEPROM versus writing in SPI F-RAM. www.cypress.com Document No. 001-96614 Rev. ** 8 Migrating from SPI EEPROM to Cypress's SPI F- AM™ Figure 7. Write Operation in EEPROM and F-RAM Write in EEPROM Write in F-RAM Initiate a write command Initiate a write command Send data Byte Send data byte YES YES NO Is burst write continuing? NO Address counter will roll over to the start of the page address 0h Is page boundary arrived? YES YES NO Is burst write continuing? NO Is page write continuing? Address counter will roll over to the start of the memory address 0h NO YES Is internal write initiated? Is device still active? NO NO YES Is memory boundary arrived? YES YES Is write continuing? NO Is device still active? YES NO Device ready for the next command RDY/ WIP is set to 1 Is internal write cycle complete? NO YES RDY/ WIP is cleared to 0 . Device is ready for the next command 4.2 Page Write Delay EEPROMs typically require a page write delay of 5 ms to transfer its buffer data into the nonvolatile EEPROM cells. The EEPROM page size varies between densities or between different vendors product for the same density. The system firmware must be designed to take care of the page size variation and the page write delay between different EEPROM parts. The page write delay is not required in the SPI F-RAM; therefore, the write delay can be removed in the firmware to improve the system’s nonvolatile write performance when migrating to the SPI F-RAM. 4.3 / WIP Bit in Status Register SPI EEPROMs define the Status Register bit0 as Ready ( ) or Write in Progress (WIP). When an EEPROM page write is in progress, the Status Register bit0 is set to ‘1’, indicating that EEOROM is busy. The host controller polls the Status Register /WIP bit for the EEPROM status before initiating a new write or read access. www.cypress.com Document No. 001-96614 Rev. ** 9 Migrating from SPI EEPROM to Cypress's SPI F- AM™ 5 Summary Migrating from the SPI EEP OM to Cypress’s SPI F-RAM will improve the system performance, reliability, and energy-efficiency. Cypress’s SPI F- AM’s industry-standard pin and package configuration, SPI instruction set (OPCODE), and electrical compatibility simplify the migration. Differences between two devices are highlighted throughout this application note. These differences need to be considered but will typically not be gating for migration in most applications. 6 Related Documents 6.1 Application Notes AN304 - SPI Guide for F- AM™ AN87352 - F- AM™ for Smart E-Meters About the Author Name: Shivendra Singh Title: Applications Engineer Principal www.cypress.com Document No. 001-96614 Rev. ** 10 Migrating from SPI EEPROM to Cypress's SPI F- AM™ Document History Document Title: AN96614 – Migrating from SPI EEPROM to Cypress's SPI F-RAM™ Document Number: 001-96614 Revision ** ECN 4756384 www.cypress.com Orig. of Change ZSK Submission Date 06/01/2015 Description of Change New Spec. Document No. 001-96614 Rev. ** 11 Migrating from SPI EEPROM to Cypress's SPI F- AM™ Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb Wireless/RF cypress.com/go/wireless Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support PSoC is a registered trademark and PSoC Creator is a trademark of Cypress Semiconductor Corp. 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