ATMEL ATR7040-PVPG

Features
•
•
•
•
•
•
•
Frequency Range 5 GHz to 6 GHz
Pout 25 dBm at 5.8 GHz
Gain Typically 30 dB
Pin Typically 0 dBm
VCC 2.7V to 3.8V
Power Consumption in Power-down Mode Typically < 1 µA
Package: QFN16 3 mm × 3 mm
5.8 GHz WDCT
Power Amplifier
Benefits
•
•
•
•
Biasing Control Extends Battery Time
Simple Input and Output Matching
Only One Single Supply Required
No High-side Switching Transistor Required
ATR7040
1. Description
1.1
Process
This 5-GHz power amplifier (PA) is designed using Atmel’s Silicon-Germanium (SiGe)
process and provides high efficiency.
1.2
Circuitry
The PA, ATR7040, consists of a three-stage amplifier with a typical output power of
25 dBm. The output stage was implemented using an open-collector structure. Power
up, power down, and output level are controlled at bias control pin 6 (Vctl).
4868C–DECT–05/06
Figure 1-1.
Block Diagram
VCC1
7
VCC2
6
ATR7040
RFIN
10
Matching
RFOUT/VCC3
2
RFOUT/VCC3
3
Matching
Bias control
13
VCTL
2
14
GND
PADDLE
GND
15
VCC_CTL
ATR7040
4868C–DECT–05/06
ATR7040
2. Pin Configuration
Pinning QFN16
NC
VCC_CTL
GND
VCTL
Figure 2-1.
16 15 14 13
12 NC
1
2 ATR7040 11 NC
3 GND on the 10 RFIN
4 PADDLE 9 NC
5 6 7 8
NC
VCC2
VCC1
NC
NC
RFOUT/VCC3
RFOUT/VCC3
NC
Table 2-1.
Pin Description
Pin
Symbol
1
NC
2
RFOUT
RF output and supply voltage for output amplifier stage
3
RFOUT
RF output and supply voltage for output amplifier stage
4
NC
Not connected(1)
5
NC
Not connected(1)
6
VCC2
Supply voltage for second amplifier stage
7
VCC1
Supply voltage for first amplifier stage
8
NC
Not connected(1)
9
NC
Not connected(1)
10
RFIN
11
NC
Not connected(1)
12
NC
Not connected(1)
13
VCTL
Control voltage for power ramping
14
GND
Ground
15
VCC_CTL
16
NC
PADDLE
–
Note:
Function
Not connected(1)
RF input
Supply voltage for biasing control block
Not connected(1)
Ground
1. Pin can be connected to paddle for increased GND area
3
4868C–DECT–05/06
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
Supply voltage
VCC
5
V
Supply current
Icc
400
mA
Junction temperature
Tj
150
°C
Storage temperature
TStg
–40 to +125
°C
Input RF power
Pin
10
dBm
Control voltage
Vctl
2.5
V
Symbol
Value
Unit
RthJA
40
K/W
Symbol
Value
Unit
VCC
2.7 to 3.8
V
Operating frequency range
fin
5100 to 5900
MHz
Ambient temperature range
Tamb
–25 to +75
°C
Note:
The part may not survive all maximums applied simultaneously.
Electrostatic sensitive device.
Observe precautions for handling.
4. Thermal Resistance
Parameters
Junction ambient package QFN16, 3 × 3,
slug soldered on PCB
5. Operating Range
Parameters
Supply voltage
4
ATR7040
4868C–DECT–05/06
ATR7040
6. Electrical Characteristics
Operating conditions: VCC = 3.6V, Vctl = 1.5V, input frequency = 5.8 GHz, input power 0 dBm, pulsed mode, duty cycle 10%, ton = 1 ms,
Tamb = 25°C, unless otherwise specified.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
1.0
Frequency range
Depends on external
circuitry
1.1
Supply voltage
Vcc
1.2
Input power
Pin
1.3
Saturated power output
Psat
1.4
Output power deviation
Pd
–2
+2
dB
1.5
Control voltage range
PA operating mode
Vctl
1.0
1.7
V
Power-down mode
Vctl
0.2
V
1.6
Control input current
PA on
5
1.7
Input return loss
With external matching
10
–6
dB
1.8
Isolation
Vctl ≤ 0.2V
ISOr
1.9
Power added efficiency
At power saturation,
Pin = 0 dBm
1.10
Current consumption
1.11
1.12
5100
2.7
3.6
Max.
Unit
5900
MHz
3.8
V
0
dBm
25
dBm
90
Ictl
–7
33
µA
35
dB
PAE
35
%
For 25 dBm output power
Icc
250
mA
Current consumption in
power-down mode
Vctl ≤ 0.2V
Icc
1
µA
Duty cycle of operation
At saturated output power
100
%
7. Application Circuit
Figure 7-1.
Application Circuit
VCC
C6
slug
RFIN
C1
8
7
6
5
9
4
TRL1 10
3
11
2
12
1
13
VCTL
14
15
L1
TRL2
C3
RFOUT
C2
16
VCC
5
4868C–DECT–05/06
8. Diagrams
Figure 8-1.
Output Power, Efficiency and Supply Currents Versus Input Frequency
Pin = 0 dBm, Vcc = 3.6V, Vctl = 1.4V
40
400
PAE (%)
350
Iges (mA)
300
30
250
Pout (dBm)
25
200
150
20
Iges (mA)
Pout (dBm), PAE %
35
100
15
50
10
5600
5650
5700
5750
5800
5850
5900
5950
0
6000
Frequency (MHz)
Figure 8-2.
Output Power, Gain, Efficiency and Supply Currents Versus Input Power
400
30
350
300
20
Gain (dB)
250
10
200
PAE (%)
0
Iges (mA)
Pout (dBm), Gain (dB), PAE (%)
Freq = 5800 MHz, Vcc = 3.6V, Vctl = 1.4V
40
150
-10
100
Iges (mA)
Pout (dBm)
-20
50
-30
0
-20
-15
-10
-5
0
5
Pin (dBm)
Figure 8-3.
Output Power, Efficiency and Supply Currents Versus Operating Voltage
Freq = 5800 MHz, Pin = 0 dBm, Vctl = 1.5V
40
450
400
35
350
30
300
Iges (mA)
250
25
200
Iges (mA)
Pout (dBm), PAE (%)
PAE (%)
Pout (dBm)
20
150
100
15
50
10
0
2.5
3.0
3.5
4.0
Vcc (V)
6
ATR7040
4868C–DECT–05/06
ATR7040
9. Ordering Information
Extended Type Number
Package
Remarks
ATR7040-PVPG
QFN16, 3 × 3
Taped and reeled, MOQ 2000, Pb-free
ATR7040-PVQG
QFN16, 3 × 3
Taped and reeled, MOQ 8000, Pb-free
10. Package Information
Package: QFN 16 - 3x3
Exposed pad 1.7x1.7
(acc. JEDEC OUTLINE No. MO-220)
Dimensions in mm
Not indicated tolerances ±0.05
3
0.9±0.1
1.7
+0
0.05 -0.05
68
2.
12
1
9
4
8
0.25
4
16
5
15
1
13
technical drawings
according to DIN
specifications
0.
0.4±0.1
16
0.5 nom.
Drawing-No.: 6.543-5115.01-4
Issue: 1; 07.03.05
1.5
Assembly Chip PAC
7
4868C–DECT–05/06
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4868C–DECT–05/06