ATMEL AT49F516

Features
• Single Voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 55 ns
Internal Program Control and Timer
8K Word Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Word-By-Word Programming - 10 µs/Word Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Small 10 x 14 VSOP Package
Typical 10,000 Write Cycles
512K (32K x 16)
5-volt Only
Flash Memory
Description
The AT49F516 is a 5-volt only in-system programmable and erasable Flash Memory.
It’s 512K of memory is organized as 32,768 words by 16 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55
ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA.
(continued)
Pin Configurations
VSOP Top View
Type 1
10 x 14 mm
Pin Name
Function
A0 - A14
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O15
Data Inputs/Outputs
NC
No Connect
6
5
4
3
2
1
44
43
42
41
40
I/O13
I/O14
I/O15
CE
NC
NC
VCC
WE
NC
NC
A14
PLCC Top View
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
A9
A10
A11
A12
A13
A14
NC
NC
WE
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10 x 14 mm
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/07
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
NC
CE
I/O3
I/O2
I/O1
I/O0
OE
DC
A0
A1
A2
A3
A4
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
I/O4
AT49F516
Preliminary
Rev. 1089B–10/98
1
To allow for simple in-system reprogrammability, the
AT49F516 does not require high input voltages for programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F516 is performed by erasing a
block of data (entire chip or main memory block) and then
programming on a word by word basis. The typical word
programming time is a fast 10 µs. The end of a program
cycle can be optionally detected by the DATA polling fea-
ture. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.
The optional 8K words boot block section includes a reprogramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS
I/O15 - I/O0
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
16
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y DECODER
Y-GATING
X DECODER
MAIN MEMORY
(24K WORDS)
7FFFH
2000H
1FFFH
OPTIONAL BOOT
BLOCK (8K WORDS)
0000H
Device Operation
READ: The AT49F516 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
CHIP ERASE: When the boot block programming lockout
feature is not enabled, the boot block and the main memory
block will erase together from the same chip erase command (See command definitions table). If the boot block
lockout function has been enabled, data in the boot section
will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return
to the read mode.
MAIN MEMORY ERASE: As an alternative to the chip
erase, a main memory block erase can be performed which
will erase all bytes not located in the boot block region to an
FFH. Data located in the boot region will not be changed
during a main memory block erase. The Main Memory
Erase command is a six bus cycle operation. The address
(5555H) is latched on the falling edge of the sixth cycle
while the 30H data input is latched on the rising edge of
WE. The main memory erase starts after the rising edge of
WE of the sixth cycle. Please see Main Memory Erase
2
AT49F516
cycle waveforms. The Main Memory Erase operation is
internally controlled; it will automatically time to completion.
WORD PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
AT49F516
device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular programming method and can be erased using either the chip
erase or the main memory block erase command. To activate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 0002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F516 features DATA polling to
indicate the end of a program or erase cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49F516
provides another method for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F516 in
the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Noise filter: Pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
3
Command Definition (in Hex)(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
Main Memory Erase
6
Word Program
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
30
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block Lockout(2)
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID Entry
3
5555
AA
2AAA
55
5555
90
(3)
3
5555
AA
2AAA
55
5555
F0
(3)
1
xxxx
F0
Product ID Exit
Product ID Exit
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
2. The 8K word boot sector has the address range 00000H to 1FFFH.
3. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
4
AT49F516
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT49F516
DC and AC Operating Range
Operating
Temperature (Case)
Com.
Ind.
VCC Power Supply
AT49F516-55
AT49F516-70
AT49F516-90
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
Operating Modes
Mode
Read
(2)
Program
Standby/Write Inhibit
CE
OE
WE
Ai
I/O
VIL
VIL
VIH
Ai
DOUT
VIL
VIH
VIL
Ai
DIN
X
High Z
(1)
VIH
X
X
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
VIL
VIL
VIH
High Z
Product Identification
Hardware
A1 - A14 = VIL, A9 = VH,(3), A0 = VIL
Manufacturer Code(4)
A1 - A14 = VIL, A9 = VH,(3), A0 = VIH
Device Code(4)
Software(5)
Notes:
A0 = VIL, A1 - A14 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A14 = VIL
Device Code(4)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 100001XX (binary).
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
Com.
100
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
µA
Ind.
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC (1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
Note:
Min
2.0
V
0.45
V
1. In the erase mode, ICC is 90 mA.
5
AC Read Characteristics
AT49F516-55
Symbol
Parameter
tACC
Min
AT49F516-70
Max
Min
AT49F516-90
Max
Min
Max
Units
Address to Output Delay
55
70
90
ns
(1)
CE to Output Delay
55
70
90
ns
tOE(2)
OE to Output Delay
30
35
0
40
ns
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
ns
tOH
Output Hold from OE, CE
or Address, whichever
occurred first
0
tCE
25
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2.
OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3.
tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
55/70 ns
90 ns
5.0V
5.0V
1.8K
1.8K
OUTPUT
PIN
30 pF
1.3K
tR, tF < 5 ns
OUTPUT
PIN
1.3K
100 pF
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
COUT
Note:
6
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49F516
AT49F516
AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
90
ns
AC Word Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
CE
WE
tAS
tAH
tCH
tCS
tWPH
tWP
tDH
tDS
DATA
IN
CE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
WE
tCS
CE
tWPH
tWP
tDS
DATA
tDH
IN
7
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Word Programming Time
10
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tWPH
Write Pulse Width High
90
ns
tEC
Erase Cycle Time
10
Program Cycle Waveforms
A0-A14
Main Memory or Chip Erase Cycle Waveforms
OE
CE
tWP
tWPH
WE
tAS
A0-A14
tAH
tDH
5555
5555
5555
2AAA
5555
2AAA
tEC
tDS
DATA
Notes:
8
AA
55
80
AA
55
NOTE 2
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
1.
OE must be high only when WE and CE are both low.
2.
For chip erase, the address should be 10H. For a main memory erase the data should be 30H.
AT49F516
seconds
AT49F516
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Notes:
Typ
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
A0-A14
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2.
Beginning and ending state of I/O6 will vary.
3.
Any address location may be used but the address should not vary.
9
Software Product
Identification Entry(1)
Boot Block
Lockout Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product
Identification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
EXIT PRODUCT
IDENTIFICATION
MODE(4)
1.
Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex); Address Format: A14 - A0 (Hex).
2.
A1 - A14 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3.
The device does not remain in identification mode if
powered down.
The device returns to standard operation mode.
Manufacturer Code: 1FH
Device Code: 100001XX (binary)
4.
5.
10
PAUSE 1 second(2)
Notes:
LOAD DATA F0
TO
ADDRESS 5555
Notes:
LOAD DATA 40
TO
ADDRESS 5555
AT49F516
1.
Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex); Address Format: A14 - A0 (Hex).
2.
Boot block lockout feature enabled.
AT49F516
Ordering Information(1)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
50
0.1
AT49F516-55JC
AT49F516-55VC
44J
40V
Commercial
(0° to 70°C)
50
0.3
AT49F516-55JI
AT49F516-55VI
44J
40V
Industrial
(-40° to 85°C)
50
0.1
AT49F516-70JC
AT49F516-70VC
44J
40V
Commercial
(0° to 70°C)
50
0.3
AT49F516-70JI
AT49F516-70VI
44J
40V
Industrial
(-40° to 85°C)
50
0.1
AT49F516-90JC
AT49F516-90VC
44J
40V
Commercial
(0° to 70°C)
50
0.3
AT49F516-90JI
AT49F516-90VI
44J
40V
Industrial
(-40° to 85°C)
70
90
Note:
Operation Range
1. The AT49F516 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.
Package Type
44J
44-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
40V
40-Lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm)
11
Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
40V, 40-Lead, Plastic Thin Small Outline
Package (TSOP)
Dimensions in Millimeters and (Inches)*
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
*Controlling dimension: millimeters
12
AT49F516
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Atmel Colorado Springs
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Europe
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TEL (719) 576-3300
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Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (44) 1276-686677
FAX (44) 1276-686697
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4 42 53 60 00
FAX (33) 4 42 53 60 01
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road
Tsimshatsui East
Kowloon, Hong Kong
TEL (852) 27219778
FAX (852) 27221369
Japan
Atmel Japan K.K.
Tonetsu Shinkawa Bldg., 9F
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1998.
Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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®
and/or
™
are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1089B–10/98/xM