ATMEL U9280M-H

Features
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4-bit HARVARD Architecture
4 k ´ 8-bit Application ROM
256 ´ 4-bit RAM
32 ´ 16-bit EEPROM
10 Bi-directional I/Os
4 External Interrupt Inputs (SSO20)
8 Interrupt Levels
2 ´ 8-bit Multifunction Timer/Counter
Interval Timer with Watchdog
Two-Wire Interface (TWI)
Voltage Supervisor
On-chip RC Oscillator
On-chip Crystal Oscillator
Benefits
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Contactless Power Supply and Communication Interface
Power Management for Contactless and Battery Power Supply
Shift-register-supported Modulator and Demodulator Stages
Low Power Consumption
Active Mode < 300 µA at 2 V and 1 MHz System Clock Frequency
(2 µs Instruction Cycle)
Power-down Mode < 1 µA
Supply Voltage 2.0 V to 6.5 V
High-level Language Programming in qFORTH
Operating Speed: 1 µs to 10 µs Instruction Cycle (2 µs at VDD = 2 V)
Microcontroller
with
Transponder
Interface
U9280M-H
Preliminary
Description
The U9280M-H IC is a multi-chip module for remote control and contactless ID systems. It consists of the ATAR092 microcontroller and U3280M transponder interface
circuit with EEPROM. A coil connected to the transponder interface serves as a wireless bi-directional communication interface as well as a power supply for the
microcontroller and the interface. As a transponder, the device is supplied by a magnetic RF field applied at the coil. For IR- or RF-transmitter applications, it can be
supplied by a battery. The microcontroller supports, with its built-in timers, a wide
range of IR- and RF-transmission modes such as burst-modulation modes, PWM-,
NRZ-, Manchester- and Bi-phase coding.
Rev. 4591A–RFID–03/03
1
Figure 1. Block Diagram
C
OSC2
VBATT
ATAR092 microcontroller
U9280M-H transponder interface
Power
management
Damping
stage
Reset
voltage monitor
Field/GAP
detect
ROM
COIL1
OSC1/ROSC
VDD
512-bit
EEPROM
memory
Oscillators
clock management
BP50/INT6
RAM
4-bit CPU core
BP53/INT1
Timer/
counter
BP23
Rectifier
BP20/NTE
MCL
COIL2
Clock
extractor
Serial
interface
³1
BP60/T3O
Modulator/
demodulator
Serial
interface
Biphase
modulator
BP63/T3I
I/O-Ports
VSS
BP40/
SC/INT3
MOD
FC
NGAP
BP43/
SD/INT3
BP42/
T2O
BP41/
VMI/ T2I
Pin Configuration
Figure 2. Pinning SSO20
COIL1
1
20
NGAP
COIL2
2
19
MOD
VBATT
3
18
FC
VDD
4
17
VSS
BP40/SC/INT3
5
16
BP43/SD/INT3
BP53/INT1
6
15
BP42/T2O
BP50/INT6
7
14
BP41/VMI
OSC1/ROSC
8
13
BP23
OSC2
9
12
BP20/NTE
10
11
BP63/T3I/INT5
BP60/T3O
2
U9280M-H
U9280M-H
4591A–RFID–03/03
U9280M-H
Pin Description
Pin
Symbol
Function
1
COIL1
Coil input 1, Pin to connect an LC antenna for communication and field supply
2
COIL2
Coil input 2, Pin to connect an LC antenna for communication and field supply
3
VBATT
Power-supply voltage input to connect a battery
Power-supply voltage for the microcontroller and EEPROM. At this pin a capacitor (0.5 µF to 10 µF)
must be connected to buffer the voltage during field supply and to block the VDD of the
microcontroller.
4
VDD
5
BP40/SC/INT3
6
BP53/INT3
I/O-port line/INT3 interrupt input (falling or rising edge sensitive)
7
BP50/INT6
I/O-port line/INT6 interrupt input (falling or rising edge sensitive)
8
OSC1/ROSC
9
OSC2
10
BP60/T3O
11
BP63/T3I/INT5
12
BP20/NTE
13
BP23
14
BP41/VMI
I/O-port line/Voltage monitor input/Timer 2 input
15
BP42/T2O
I/O-port line/Timer 2 output/modulator output
16
BP43/SD/INT3
17
VSS
18
FC
19
MOD
Modulation input - front end. Must be connected to the modulator output T2O.
20
NGAP
Gap detect output - front end. Must be connected to the demodulator input T3I.
I/O-port line/serial clock line/INT3 input (falling edge sensitive)
Oscillator- or external system-clock input/input for RC-oscillator resistor
Oscillator output
Bi-directional I/O-line/Timer 3 output/modulator output
I/O-port line/INT5 interrupt input/Timer 3 input/demodulator input
BP20-I/O-port line/test mode input. This input is used to control the test modes. During POR it must
not be connected with a low impedance to VDD.
I/O-port line
I/O-port line/serial data line/INT3 input (falling edge sensitive)
Circuit ground
Field clock output of the clock extractor
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Functional
Description
The U9280M-H multi-chip module contains a microcontroller and a transponder IC
mounted in a single package. Everything necessary for remote control and wireless
identifcation systems is integrated: Inputs to connect keys, outputs to control an IR- or
RF transmitter and to drive indicator LEDs, an EEPROM to store key code and identifiers, and an interface for contactless communication and a power supply.
The U3280M is a transponder interface consisting of an analog front end for contactless
data communication and power supply, and a serial 512-bit EEPROM. In addition, it
includes power management to switch the battery or magnetic-field power supply. For
modulation and demodulation of the magnetic field, the device has input and output pins
to connect the microcontroller. The MOD, NGAP and FC Pins can be connected externally to the modulator, demodulator and timer I/O pins of the microcontroller. Access to
the EEPROM is possible via a two-wire serial interface. The ATAR092 microcontrollers
are equipped with compatible two-wire serial interface to communicate with the
U3280M. In the U9280M-H the serial interfaces of the transponder interface and the
microcontroller are linked internally.
ATAR092
The ATAR092 microcontroller is a member of the Atmel’s 4-bit single-chip microcontroller family. It is especially designed for remote-control applications. It consists of an
advanced stack-based 4-bit CPU core with 4 K ROM, 256 nibble of RAM and on-chip
peripherals. The CPU is based on the HARVARD architecture and contains an interrupt
controller with 8 prioritized interrupt levels.
The peripherals include parallel I/O ports, two 8-bit programmable multifunction
timer/counters, a two-wire serial interface, an interval timer with watchdog function and
a voltage supervisor. The serial interface supports, together with the timers, a modulator
and demodulator stage for Manchester, Bi-phase and pulse-width modulation and
demodulation. The integrated clock generator contains a RC-, a 32-kHz crystal, a
4-MHz crystal oscillator and a programmable input to use an external clock.
Note:
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In the U9280M-H not all I/O pins of the ATAR092 are available (see “Pin Description”).
The microcontroller is fully described in the MARC4 ATAR092 data sheet.
U9280M-H
4591A–RFID–03/03
U9280M-H
Figure 3. Block Diagram ATAR092
V SS V DD
OSC1 OSC2
Brown-out protect
RESET
Voltage monitor
External input
RC
Crystal
External
oscillators oscillators clock input
UTCM
Clock management
Timer 1
interval- and
watchdog timer
VMI
ROM
BP10
Port 1
RAM
4 K x 8-bit
BP13
Timer 2
8/12-bit timer
with modulator
256 x 4 bit
SD
BP22
BP23
Port 2
BP21
Data direction
SSI
BP20/NTE
MARC4
Serial interface
4-bit CPU core
Timer 3
8-bit
timer / counter
with modulator
and demodulator
I/O bus
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Data dir. +
alt. function
Port 5
Port 6
BP50
BP52
BP40
BP42
INT3
T2O BP43 INT6
INT1
SC BP41
BP53
BP51
INT3
VMI
INT6
INT1
SD
T2I
The U3280M
Transponder Interface
T2I
T2O
SC
T3O
T3I
BP60 BP63
T3O
T3I
The transponder interface contains a rectifier stage to rectify the AC from the coil inputs
and to supply itself and an additional microcontroller device with power from an LC-resonant circuit at the coil inputs. It is also possible to supply the device via the VBatt -input
with DC from a battery. The built-in power management switches automatically between
battery supply (VBatt pin) and coil supply. It switches to coil supply if a field is applied at
the coil and switches back to battery if the field is removed.
The voltage from the coil or the VBatt pin is output at the VDD pin to supply the microcontroller device. At the VDD pin a capacitor must be connected to smooth and buffer the
supply voltage for the transponder interface and the microcontroller. This capacitor is
also used to buffer the supply voltage during communication (damping and gaps in the
field).
For communication, a damping-stage and a gap-detect circuitry is on the chip. By
means of the damping stage the coil voltage can be modulated to transmit data via the
field. It can be controlled with the modulator input (MOD pin) via the microcontroller. The
gap detection circuitry detects gaps in the field and outputs the gap/field signal at the
gap detect output (NGAP pin). It can be used to receive data via a modulated field and
to check if a field is applied at the coil.
For the storage of data such as key codes, identifiers and configuration bits, a 512-bit
EEPROM is available on the chip. It can be read and written to by the microcontroller via
a TWI-compatible two-wire serial interface. The serial interface, the EEPROM and the
microcontroller are supplied with the voltage at the VDD pin. That means the microcontroller can read and write to the EEPROM if the supply voltage is in the operating range.
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The U3280M contains additional operating modes to support a wide range of applications. These modes can be controlled via the serial interface. The power management
can be switched off by software to disable the automatic switching between battery and
field. This supports applications with battery supply only.
There is an on-chip Bi-phase and Manchester modulator. It can be selected and controlled via the serial interface with a special mode control byte. If this modulator is used
the external connection to the modulator input is not necessary.
Modulation
The transponder interface can modulate the magnetic field by a modulator to transmit
data to a base station. It modulates the coil voltage by varying the coil‘s load. The modulator can be controlled via the MOD pin. A high level 1 increases the current into the
coil inputs and damps the coil voltage. A low level 0 decreases the current and
increases the coil voltage. The modulator generates a voltage stroke of about 2 Vpp at
the coil. A high level at the MOD input makes the maximum of the field energy available
at VDD. During a reset a high level at the MOD input causes the optimum conditions for
starting the device and charging the capacitor at VDD after the field is applied at the coil.
Digital Input to Control the
Damping Stage (MOD)
Mod = 0: coil undamped
V COIL_peak = V DD ´ 2 + V CMS = V CU
Mod = 1: coil damped
V COIL_peak = V DD ´ 2 = V CD
VCMS = VCID: modulation voltage stroke at coil inputs
Note:
If the automatic power management is disabled the internal front end VDD is limited at
VDDC. In this case the value VDDC must be used in the formula above.
Field Clock
The field clock extractor of the interface makes the field clock available for the microcontroller. It can be used to supply timer inputs to synchronize modulation and
demodulation with the field clock.
Gap Detect
The transponder interface can also receive data. The base station modulates the data
with short gaps in the field. The gap-detection circuit detects these gaps in the magnetic
field and outputs the gap/field signal at the NGAP pin. A high level indicates that a field
is applied at the coil and a low level indicates a gap or that the field is off. The microcontroller must demodulate the incoming data stream at one of its inputs.
Digital Output of the Gap
Detection Stage (NGAP)
NGAP = 0: gap detected/no field
VCOIL_peak = VFDOFF
NGAP = 1: field detected
VCOIL_peak = VFDON
Note:
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No amplifier is used in the gap detection stage. A digital Schmitt trigger evaluates the
rectified and smoothed coil voltage.
U9280M-H
4591A–RFID–03/03
U9280M-H
Wake-up Signal
If a field is applied at the coil of the transponder interface the microcontroller can be
woken up with the wake signal at the NGAP pin. For that purpose the NGAP pin must be
connected to an interrupt input of the microcontroller. A high level at the NGAP output
indicates an applied field and can be used as a wake signal for the microcontroller via
an interrupt. If no battery voltage is available at VBatt the controller starts with a poweron-reset after the voltage of the buffer capacitor at VDD is loaded by the field above the
power-on-reset level.
The wake signal is generated if the power management switches to field supply. The
field detection stage of the power management has low-pass characteristics to avoid the
generation of wake signals and unnecessary switching between battery and field supply
in case of interferences at the coil inputs.
U3280M Signals and
Timing
Figure 4. Modulation
MOD
VCU
V CMS
VCD
Coil inputs
Figure 5. Gap Detection and Battery to Field Switching
t FGAP1
t FGAP1
t FGAP0
t FGAP0
VFDON
VFDON
V
V FDOFF
FDOFF
Coil inputs
Coil inputs
1. edge used as
1. edge used assignal
wakeup signal
wakeup
NGAP
NGAP
Field clock
FC
Field
clock
FC
Power
management
Power management
Power Supply
Battery
supply
Battery
supply
Battery
Battery
supply
t BFS
t BFS
supply
Coil supply
if automatically
power management is enabled
Coil
supply
if automatically
power management is enabled
tFBS
t FBS
The U3280M has a power management that handles two power-supply sources. Normally, the IC is supplied by a battery at the VBatt pin. If a magnetic field is applied at the
LC-resonant circuit of the device the field detection circuit switches from VBatt to field
supply. During field supply the VDD voltage is limitted to 3 V.
The VDD pin is used to connect a capacitor to smooth the voltage from the rectifier and
to buffer the power when the field is modulated by gaps and damping. The EEPROM
and the microcontroller always operate with the voltage at the VDD pin.
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Automatic Power
Management
There are different conditions to switch from the battery to field generated voltage and
vice versa.
Figure 6. Switch Conditions for Power Management
VCoil < VFDON for t > tFBS
Battery
supply
(VBatt)
Field
supply
VCoil < VFDOFF for t > tFBS
The power management switches automatically from battery to field if the rectified voltage (Vcoil) from the coil inputs becomes higher than field-on-detection voltage (VFDON)
even if no battery voltage is available (0 < VBatt < 1.8 V). It switches back to battery if the
coil voltage becomes lower than the field-off-detection voltage (VFDOFF).
The field-detection stage of the power management has low-pass characteristics to suppress noise. An applied field needs a time delay tBFS (battery-to-field switch delay) to
change the power supply. If the field is removed from the coil the power management
will generate a reset of the microcontroller.
Controlling Power
Management via the Serial
Interface
The automatic mode of the power management can be switched off and on by a command from the microcontroller. If the automatic mode is switched off the IC is always
supplied by the battery up to the next power-on reset or to a switch-on command. The
power management-on and -off command must be transferred via the serial interface.
If the power management is switched off and the device is supplied from the battery it
can communicate via the field without loading the field. This mode can be used to realize applications with a battery supply if the available field is too weak to supply the IC
with power.
Buffer Capacitor CB
The buffer capacitor connected at VDD is used to buffer the supply voltage for the microcontroller and the EEPROM during field supply. It smooths the rectified AC from the coil
and buffers the supply voltage during modulation and gaps in the field. The size of this
capacitor depends on the application. It must be of a dimension so that during modulation and gaps the ripple on the supply voltage is in the range of 100 to 300 mV. During
gaps and damping the capacitor is used to supply the device, that means the size of the
capacitor depends on the length of the gaps and damping cycles.
Example: For a supply current of 350 µA, 200 mV ripple at VDD
Table 1. Buffer Capacitor
Time with no Field Supply
8
Necessary CB
250 µs
470 nF
500 µs
1000 nF
U9280M-H
4591A–RFID–03/03
U9280M-H
Serial Interface
The transponder interface has an serial interface to the microcontroller for read and
write accesses to the EEPROM. In a special mode the serial interface can also be used
to control the Bi-phase/Manchester modulator or the power management of the
U3280M.
The serial interface of the U3280M device must be controlled by a master device (normally the ATAR09x microcontroller) which generates the serial clock and controls the
access via the SCL- and SDA-line. SCL is used to clock the data in and out of the
device. SDA is a bi-directional line used to transfer data into and out of the device. The
following protocol is used for data transfers.
Serial Protocol
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Data states on the SDA line changing only while SCL is low.
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Changes in the SDA line while SCL is high will be interpreted as a START or STOP
condition.
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A START condition is defined as a high-to-low transition on the SDA-line while the
SCL-line is high.
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A STOP condition is defined as a low-to-high transition on the SDA-line while the
SCL-line is high.
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Each data transfer must be initialized with a START condition and terminated with a
STOP condition. The START condition wakes the device from standby mode and the
STOP condition returns the device to stand-by mode.
•
A receiving device generates an acknowledge (A) after the reception of each byte.
For that the master device must generate an extra clock pulse. If the reception was
successful the receiving master or slave device pulls down the SDA-line during that
clock cycle. If in transmit mode an acknowledge is not detected (N) by the interface,
it will terminate further data transmissions and will go into receive mode. A master
device must finish its read operation by a Not-acknowledge and then issue a stop
condition to place the device into a known state.
Figure 7. Serial Protocol
SCL
SDA
Stand- Start
by condition
Data
valid
Data/
Data
change acknowledge
valid
Stop
Standcondition by
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Control Byte Format
EEPROM address
Start
A4
A3
A2
Mode control bits
A1
A0
C1
C0
Read/Write
R/W
Ackn
The control byte follows the start condition and consists of the 5-bit row address, 2 mode control bits and the read/not writebit.
Data Transfer Sequence
Start
Control byte
Ackn.
Data byte
Ackn.
Data byte
Ackn.
Stop
•
Before the START condition and after the STOP condition the device is in standby
mode and the SDA-line is switched to input with a pull-up resistor.
•
The START condition follows a control byte that determines the following operation.
Bit 0 of the control byte is used to control the following transfer direction. A 0 defines
a write access and a 1 a read access.
EEPROM
The EEPROM has a size of 512 bits and is organized as a 32 ´ 16-bit matrix. To read
and write data to and from the EEPROM the serial interface must be used. The interface
supports one and two byte write accesses and one to n-byte read accesses to the
EEPROM.
Operating Modes
The operating modes of the EEPROM are defined via the control byte. The control byte
contains the row address, the mode control bits and the read/write bit that is used to
control the direction of the following transfer. A 0 defines a write access and a 1 a read
access. The five address bits select one of the 32 rows of the EEPROM memory to be
accessed. For all accesses the complete 16-bit word of the selected row is loaded into a
buffer. The buffer must be read or overwritten via the serial interface. The two mode
control bits C1 and C2 define in which order the accesses to the buffer are performed:
High byte – low byte or low byte – high byte. The EEPROM also supports autoincrement and autodecrement read operations. After sending the start address with the
corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses.
Two special control bytes enable the complete initialization of EEPROM with a 0 or with
a 1.
Write Operations
The EEPROM allows 8-bit and 16-bit write operations. A write access starts with the
START condition followed by a write control byte and one or two data bytes from the
master. It is completed via the STOP condition from the master after the acknowledge
cycle.
If the EEPROM receives the control byte, it loads the content of the addressed memory
cell into a 16-bit read/write buffer. After the first data byte has been received the
EEPROM starts the internal programming cycle. It consists of an erase cycle (write
“zeros”) and the write cycle (write “ones”). Each cycle takes about 10 ms. The write
cycle is started after the stop condition and the complete buffer is stored back automatically to the EEPROM. That means for two-byte write operations, the second byte must
be transferred within the erase cycle otherwise only the first byte will be stored in the
EEPROM and the second byte will be ignored.
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U9280M-H
4591A–RFID–03/03
U9280M-H
Acknowledge Polling
If the EEPROM is busy with an internal write cycle, all inputs are disabled and the
EEPROM will not acknowledge until the write cycle is finished. This can be used to
detect the end of the write cycle. The master must perform acknowledge polling by
sending a start condition followed by the control byte. If the device is still busy with the
write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform further acknowledge polling sequences. If the cycle is complete, it
returns an acknowledge and the master can proceed with the next read or write cycle.
Write One Data Byte
Start
Control byte
A
Data byte 1
A
Stop
A
Data byte 1
A
Data byte 2
A
Stop
Write Two Data Bytes
Start
Control byte
A
Stop
Write Control Byte Only
Start
Note:
Control byte
A = acknowledge
Write Control Bytes
MSB
Write low byte first
A4
LSB
A3
A2
A1
A0
Row address
Byte order
LB(R)
C1
C0
R/W
0
1
0
HB(R)
MSB
Write high byte first
A4
LSB
A3
A2
Row address
Byte order
Note:
Read Operations
HB(R)
A1
A0
C1
C0
R/W
1
0
0
LB(R)
HB: high byte; LB: low byte; R: row address
The EEPROM allows byte-, word- and current address read operations. The read operations are initiated in the same way as write operations. Every read access is initiated by
sending the START condition followed by the control byte which contains the address
and the read mode. After the device receives a read command it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data
byte to the master. The master has to acknowledge the received byte if it wants to proceed with the read operation. If two bytes are read out from the buffer the device
increments respectively, decrements the word address automatically and loads the
buffer with the next word. The read mode bits determines if the low or high byte is read
first from the buffer and if the word address is incremented or decremented for the next
read access. If the memory address limit is reached, the data word address will “roll
over” and the sequential read will continue. The master can terminate the read operation
after every byte by not responding with an acknowledge (N) and by issuing a stop
condition.
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Read One Data Byte
Start
Control byte
A
Data byte 1
N
Stop
A
Data byte 1
A
Data byte 2
Read Two Data Bytes
Start
Control byte
N
Stop
Read n Data Bytes
Start
Control byte
A
Data byte 1
Note:
A
Data byte 2
A
–
Data byte n
N
Stop
A -> acknowledge, N -> no acknowledge
Read Control Bytes
MSB
Read low byte first,
address increment
A4
LSB
A3
A2
A1
A0
Row address
Byte order
LB(R)
HB(R)
LB(R+1)
HB(R+1)
C1
C0
R/W
0
1
1
–
LB(R+n)
MSB
Read high byte first,
address decrement
A4
LSB
A3
A2
A1
A0
Row address
Byte order
Note:
HB(R)
HB(R+n)
LB(R)
HB(R-1)
LB(R-1)
–
C1
C0
R/W
1
0
1
HB(R-n)
LB(R-n)
HB: high byte; LB: low byte, R: row address
Initialization after a Reset
Condition
The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrollers that have their own reset circuitry for power-on reset, watchdog reset or
brown-out reset, it may be necessary to bring the EEPROM into a known state independent of its internal reset. This is performed by reading one byte without acknowledgeing
and then generating a stop condition.
Special Modes
By means of special control bytes, the serial interface can be used to control the modulator stage or power management. The EEPROM access and the serial interface are
disabled in these modes until the next STOP condition. If no START or STOP condition
is generated, the SCL and SDA line can be used for the modulator stage. SCL is used
for the modulator clock and SDA is used for the data. In that mode, the same conditions
for clock and data changing normally are valid. The SCL and SDA line can be used for
continuous bit transfers, an acknowledge cycle after 8 bits must not be generated.
Table 2. Special Modes
12
Control Byte
Description
1100x111b
Bi-phase modulation
1101x111b
Manchester modulation
11xx0111b
Switch power management off: disables switching from battery to field supply
11xx1111b
Switch power management on: enables automatically switching between
battery and field supply
xxxxx110b
Reserved
U9280M-H
4591A–RFID–03/03
U9280M-H
Data Transfer Sequence for Bi-phase and Manchester Modulation:
Start
Control byte
Ackn
Note:
Power-on Reset
Bit 1
Bit 2
Bit 3
...
Bit n
Stop
After a reset of the microcontroller, it is not known if the transponder interface has been
reset, too. It could still be in a receive or transmit cycle. To place the serial interface of the
device into a known state, the miocrocontroller should read one byte from the device
without acknowledge and generate a stop condition.
The analog front end starts working with the applied field. The EEPROM with the serial
interface has its own reset circuitry. (The reset level of the front end is below the reset
level of the ATAR092)
The microcontroller has a power-on reset circuitry with a brown-out detection. One of
two reset voltage levels [1.8 V/2.0 V] can be selected via the software (see the
ATAR092 data sheet). If a fast instruction cycle (< 2 µs) is used the higher reset level
should be selected.
After a watchdog or brown-out detection reset, the serial interface and the EEPROM
should be reset by reading one byte from the transponder interface device without
acknowledgeing and generation of a STOP condition. That places the serial interface
and EEPROM into a known state.
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Electrical Characteristics – Common Features U9280M-H
• Operating Temperature Range: -40°C to +85°C
• Operating Voltage Range (VBatt): 2.0 V to 6.5 V
• Low Power Consumption:
– 600 µA at 6.5 V in Operating Mode ( with 2 µs Instruction Cycle)
– 200 µA at 2.0 V in Operating Mode (with 2 µs Instruction Cycle)
– 1 µA at 2.0 V in Stop Mode
• Power Supply: Contactless (Coil 125 kHz) and Battery Supply
Absolute Maximum Ratings
Voltages are given relative to VSS
Parameters
Supply voltage
Symbol
Value
Unit
VBatt,VDD
0 to +7 with reverse protection
V
Maximum current out of the VSS pin
15
mA
Maximum current out of the VBatt pin
15
mA
VIN
VSS- 0.6 < VIN < VDD + 0.6
V
IIK/IOK
±15
mA
Minimum ESD protection (100 pF through 1.5 kW)
±2
kV
Minimum ESD protection Coil 1 and Coil 2 inputs
(100 pF through 1.5 kW)
±1
kV
Input voltage (on any pin)
Input/output clamp current (VSS > Vi / Vo > VDD)
Operating temperature range
Tamb
-40 to +85
°C
Storage temperature range
Tstg
-40 to +125
°C
Soldering temperature (t £ 10 s)
Tsd
260
°C
Note:
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at any condition above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability.
All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the
build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (e.g., VDD).
Thermal Resistance
Parameters
Junction ambient SSO20
14
Symbol
Value
Unit
RthJA
140
K/W
U9280M-H
4591A–RFID–03/03
U9280M-H
Common DC Characteristics
VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified
Parameters
Test Conditions/Pins
Symbol
Min.
Operating voltage at VBatt
VBatt
Operating voltage at VDD
VDD
Typ.
Max.
Unit
2.0
6.5
V
VPOR
6.5
V
Power Supply
fSYSCL = 1 MHz
Active current
CPU active
Power down current
(CPU sleep, RC oscillator active,
4-MHz quartz oscillator active)
VDD = 2.0 V
IDD
200
VDD = 3.0 V
300
VDD = 6.5 V
600
fSYSCL = 1 MHz
1.0
VDD = 2.0 V
IPD
40
250
µA
µA
800
µA
70
µA
VDD = 3.0 V
100
VDD = 6.5 V
250
400
µA
ISleep
1.0
2.0
µA
IReset
150
Sleep current (CPU sleep, 32-kHz
quartz-oscillator inactive 4-MHz
quartz-oscillator inactive)
VDD = 6.5 V
Reset current
VDD < VPOR
µA
µA
DC Characteristics – Microcontroller ATAR092
VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
Brown-out Protection Reset Threshold Voltage
Reset threshold voltage
BOT = 1
VPOR
155
1.7
1.85
V
Reset threshold voltage
BOT = 0
VPOR
1.85
2.0
2.2
V
Reset hysteresis
VPOR
50
3.0
mV
Voltage Monitor Threshold Voltage
VM high threshold voltage
VDD > VM, VMS = 1
VMThh
VM high threshold voltage
VDD < VM, VMS = 0
VMThh
VM middle threshold voltage
VDD > VM, VMS = 1
VMThm
VM middle threshold voltage
VDD < VM, VMS = 0
VMThm
VM low threshold voltage
VDD > VM, VMS = 1
VMThl
VM low threshold voltage
VDD < VM, VMS = 0
VMThl
VMI rising edge threshold
VMS = 1, VDD = 3 V
VVMI
VMI falling edge threshold
VMS = 0, VDD = 3 V
VVMI
2.8
3.0
2.4
2.6
2.6
2.2
2.0
3.25
V
V
2.8
V
V
2.4
2.2
V
V
External Input Voltage
1.3
1.2
1.3
1.4
V
V
15
4591A–RFID–03/03
DC Characteristics – Microcontroller ATAR092 (Continued)
VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified
Parameters
Test Conditions/Pins
Symbol
Min.
VIL
VIH
Typ.
Max.
Unit
VSS
0.2 ´
VDD
V
0.8 ´
VDD
VDD
V
-12
µA
µA
µA
All Bi-directional Ports
Input voltage LOW
VDD = 1.8 V to 6.5 V
Input voltage HIGH
VDD = 1.8 V to 6.5 V
Input LOW current
(pull-up)
VDD = 2.0 V,
VDD = 3.0 V, VIL= VSS
VDD = 6.5 V
IIL
-2.0
Input HIGH current
(pull-down)
VDD = 2.0 V,
VDD = 3.0 V, VIH = VDD
VDD = 6.5 V
IIH
Input LOW current
(strong pull-up)
VDD = 2.0 V, VIL= VSS
VDD = 6.5 V
Input LOW current
(strong pull-down)
-50
-200
50
4.0
20
100
200
µA
µA
µA
IIL
-20
-300
-50
-600
-100
-1200
µA
µA
VDD = 2.0 V, VIH = VDD
VDD = 6.5 V
IIH
20
300
50
600
100
1200
µA
µA
Input leakage current
VIL= VSS
IIL
100
nA
Input leakage current
VIH= VDD
IIH
100
nA
Output LOW current
VOL = 0.2 VDD
VDD = 2.0 V
VDD = 3.0 V,
VDD = 6.5 V
1.2
5
15
2.5
mA
mA
mA
-1.2
-5
-16
-2.5
Output HIGH current
Note:
16
VOH = 0.8 VDD
VDD = 2.0 V
VDD = 3.0 V,
VDD = 6.5 V
2.0
-4.0
-20
-100
0.6
IOL
8
-0.6
IOH
-8
12
22
-24
mA
mA
mA
The BP20/NTE pin has a strong pull-up resistor during the reset-phase of the microcontroller.
U9280M-H
4591A–RFID–03/03
U9280M-H
AC Characteristics – Operation Cycle Time
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified
Parameters
System clock cycle
Test Conditions/Pins
Symbol
Min.
VDD = 1.8 V to 6.5 V
Tamb = -40°C to +85°C
tSYSCL
VDD = 2.4 V to 6.5 V
Tamb = -40°C to +85°C
tSYSCL
Typ.
Max.
Unit
500
2000
ns
250
2000
ns
5
MHz
Timer 2 Input Timing Pin T2I
Timer 2 input clock
fT2I
Timer 2 input LOW time
tT2IL
100
ns
Timer 2 input HIGH time
tT2IH
100
ns
Timer 3 Input Timing Pin T3I
Timer 3 input clock
fT3I
SYSCL/2
Timer 3 input LOW time
tT3IL
2´
tSYSCL
ns
Timer 3 input HIGH time
tT3IH
2´
tSYSCL
ns
Interrupt request LOW time
tIRL
100
ns
Interrupt request HIGH time
tIRH
100
ns
Interrupt Request Input Timing
External System Clock
EXSCL at OSC1
ECM = EN
Rise/fall time < 10 ns
fEXSCL
0.5
4
MHz
EXSCL at OSC1
ECM = DI
Rise/fall time < 10 ns
fEXSCL
0.02
4
MHz
Input HIGH time
Rise/fall time < 10 ns
tIH
0.1
µs
Reset Timing
Power-on reset time
VDD > VPOR
tPOR
1.5
fRcOut1
3.8
5
ms
RC Oscillator 1
Frequency
Stability
VDD = 2.0 V to 6.5 V
Temperature coefficient
Df/f
MHz
±50
%
Df/f/°C
0.15
%
fRcOut2
fRcOut2
4
1
MHz
RC Oscillator 2 – External Resistor
Frequency
Rext = 170 kW
Rext = 720 kW
Stability
VDD = 2.0 V to 6.5 V
Stabilization time
Df/f
±15
%
tS
10
µs
4-MHz Crystal Oscillator (Operating Range 2.2 V to 6.5 V)
Frequency
fX
4
MHz
Start-up time
tSQ
5
ms
Stability
Integrated input/output capacitances
(mask programmable)
CIN/COUT programmable in steps of
2 pF
Df/f
-10
+10
ppm
CIN
COUT
0
0
20
20
pF
pF
17
4591A–RFID–03/03
AC Characteristics – Operation Cycle Time (Continued)
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
32-kHz Crystal Oscillator (Operating Range 2.0 V to 6.5 V)
Frequency
fX
32.768
kHz
Start-up time
tSQ
0.5
s
Stability
Df/f
-10
+10
ppm
CIN
COUT
0
0
20
20
pF
pF
Integrated input/output capacitances
(mask programmable)
CIN/COUT programmable in steps of
2 pF
External 32-kHz Crystal Parameters
Crystal frequency
fX
32.768
kHz
Serial resistance
RS
30
Static capacitance
C0
1.5
pF
Dynamic capacitance
C1
3
fF
Crystal frequency
fX
4.0
MHz
50
kW
External 4 MHz Crystal Parameters
Serial resistance
RS
40
150
W
Static capacitance
C0
1.4
3
pF
Dynamic capacitance
C1
3
fF
Figure 8. Crystal and Equivalent Circuit
Equivalent
Equivalent
circuit
circuit
OSCIN
OSCIN
SCLIN
SCLIN
18
OSCOUT
OSCOUT
SCLOUT
SCLOUT
LL
C1
C1
RS
RS
C0
C0
U9280M-H
4591A–RFID–03/03
U9280M-H
DC Characteristics –Transponder Interface U3280M
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
Operating voltage at VBatt
VBatt
2.0
6.5
V
Operating voltage at VDD during
battery supply
VDDB
VDD limiter voltage during coil supply
VDDC
2.4
2.9
3.2
V
2.2
2.5
2.9
V
Power Supply
VBattVSD
V
Power Management
Field on detection voltage
VDD > 1.8 V
VFDon
Field off detection voltage
VDD > 1.8 V
VFDoff
Voltage drop at power-supply switch
IS = 1 mA, VBatt = 2 V
0.8
V
VSD
300
mV
ICI
20
mA
4.0
V
Coil Input Coil 1, Coil 2
Coil input current
Coil voltage stroke during
modulation
VCU > 5 V
Input capacitance
VCMS
1.8
CIN
30
pF
MOD Pin
Input LOW voltage
VIL
VSS
0.2 ´
VDD
V
Input HIGH voltage
VIH
0.8 ´
VDD
VDD
V
Input leakage current
IIleak
10
nA
NGAP/FC Pin
Output LOW current
VDD = 2.0 V
VOL = 0.2 ´ VDD
IOL
0.08
0.2
0.3
mA
Output HIGH current
VDD = 2.0 V
VOH = 0.8 ´ VDD
IOH
-0.06
-0.15
-0.25
mA
450
µA
EEPROM
Operating current during erase/write
cycle
VDD = 2 V
IWR
19
4591A–RFID–03/03
AC Characteristics – Transponder Interface U3280M
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
500
kHz
100
kHz
Serial Interface Timing (Internal)
SCL clock frequency (intern)
fSC
Serial Timing (if SCL and SDA Available Extern)
SCL clock frequency (extern)
fSCL
0
Clock low time
tLOW
4.7
µs
Clock high time
tHIGH
4.0
µs
SDA and SCL rise time
tR
1000
ns
SDA and SCL fall time
tF
300
ns
Start condition setup time
tSUSTA
4.7
µs
Start condition hold time
tHDSTA
4.0
µs
Data input setup time
tSUDAT
250
ns
Data input hold time
tHDDAT
0
ns
Stop condition setup time
tSUSTO
4.7
µs
tBUF
4.7
µs
Bus free time
Input filter time
tI
Data output hold time
tDH
300
100
ns
1000
ns
Coil Inputs
Coil frequency
fCOIL
125
kHz
Gap Detection
Delay field off to gap = 0
VCoilGap < 0.7 VDC
tFGAP0
10
50
µs
Delay field on to gap = 1
VCoilField > 3 VDC
tFGAP1
1
10
µs
Battery to field switch delay
tBFS
160
Field to battery switch delay
tFBS
Power Management
10
650
µs
60
ms
EEPROM
Endurance
Data erase/write cycle time
Erase/write-cycles
for 16 bits access
Data erase time
Data retention time
Tamb = 25°C
ED
500,000
tDEW
9
tDE
2
tDR
10
E/Wcycles
1,000,000
12
ms
1/2 ´
tDEW
ms
years
Power-up to read
operation
tPUR
0.2
ms
Power-up to write
operation
tPUW
0.2
ms
20
U9280M-H
4591A–RFID–03/03
U9280M-H
Ordering Information
Please select the option settings from the list below and insert in ROM CRC.
Output
Input
Port 1
Output
Input
Port 5
BP10 [X]
CMOS
[X]
Pull-up
BP50 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
BP13 [X]
CMOS
[X]
[ ] Pull-down strong
Pull-up
BP51 [X]
CMOS
[X]
Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
[ ] Pull-down strong
Port 2
BP52 [X]
BP20 [ ] CMOS
CMOS
[X]
Pull-up
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
BP53 [ ] CMOS
BP21 [X]
CMOS
[X]
Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
BP22 [X]
CMOS
[X]
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
Port 6
Pull-up
BP60 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
BP23 [ ] CMOS
[ ] Pull-down strong
[ ] Pull-up
BP63 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
[ ] Pull-down strong
Port 4
BP40 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
BP41 [ ] CMOS
OSC1
[ ] No integrated capacitance
[ ] Internal capacitance [ _____pF]
OSC2
[ ] Pull-up
[ ] No integrated capacitance
[ ] Open drain [N]
[ ] Pull-down
[ ] Internal capacitance [ _____pF]
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
BP42 [ ] CMOS
ECM (External Clock Monitor)
[ ] Pull-up
[ ] Enable
[ ] Open drain [N]
[ ] Pull-down
[ ] Disable
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
BP43 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up strong
[ ] Pull-down strong
File: _____________________ . HEX
Aproval
Date: _________________
CRC: ____________________ . HEX
Signature: _________________________
21
4591A–RFID–03/03
Ordering Information (Continued)
Extended Type Number
Package
Remarks
U9280M-H-xxxz-FSG3
SSO20
> 200 kpcs annually taped and reeled
Customer ROM mask
- To be defined by the customer
- Lead time: 18 weeks after ROM mask programming and reception of the order
Flash Version:
As flash version of the U9280M-H the MARC4 ATAR892 is used (available from stock).
Package Information
5.7
5.3
Package SSO20
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.05
0.25
0.65
5.85
20
0.15
6.6
6.3
11
technical drawings
according to DIN
specifications
1
22
10
U9280M-H
4591A–RFID–03/03
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4591A–RFID–03/03
xM