Revised August 1999 74FR543 Octal Latched Transceiver with 3-STATE Outputs General Description Features The 74FR543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Both the A and B outputs will source 15 mA and sink 64 mA. ■ Functionally equivalent to 74F543 ■ Back-to-back registers for storage ■ Bidirectional data path ■ A and B outputs have current sourcing capability of 15 mA and current sinking capability of 64 mA ■ Separate controls for data flow in each direction ■ Guaranteed pin-to-pin skew ■ Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number Package Description 74FR543SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74FR543SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 1999 Fairchild Semiconductor Corporation Connection Diagram DS010902 www.fairchildsemi.com 74FR543 Octal Latched Transceiver with 3-STATE Outputs January 1991 74FR543 Pin Descriptions Pin Names Description OEAB, OEBA Output Enable Inputs LEAB, LEBA Latch Enable Inputs CEAB, CEBA Chip Enable Inputs A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Data I/O Control Table Functional Description The 74FR543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A-to-B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on (LEAB) input makes the A-to-B latches transparent; a subsequent LOWto-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B-to-A is similar, but using the CEBA, LEBA and OEBA. Inputs CEAB LEAB OEAB www.fairchildsemi.com 2 Output Status Buffers H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram Latch Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC V Conditions VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH Voltage V Min IOH = −3 mA (An, Bn) V Min IOH = −15 mA (An, (Bn) VOL Output LOW Voltage 0.55 V Min IOL = 64 mA (A n, Bn) IIH Input HIGH Current 5 µA Max VIN = 2.7V IBVI Input HIGH Current 7 µA Max VIN = 7.0V (Control Pins) 100 µA Max VIN = 5.5V (An, Bn) −150 µA Max VIN = 0.5 (CEAB, CEBA) −100 µA Max VIN = 0.5 (LEAB, LEBA, OEAB, OEBA) V 0.0 IID = 1.9 µA, 3.75 µA 0.0 2.4 2.0 Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current Recognized HIGH Signal Recognized LOW Signal VID Input Leakage Test IOD Output Circuit Leakage Test IIH + IOZH Output Leakage Current 25 µA Max IIL + IOZL Output Leakage Current −150 µA Max VOUT = 0.5V (An, Bn) IOS Output Short-Circuit Current −225 mA Max VOUT = 0.0V (An, Bn) ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn) IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.25V (An, B n) ICCH Power Supply Current 59 72 mA Max All Outputs HIGH ICCL Power Supply Current 87 102 mA Max All Outputs LOW ICCZ Power Supply Current 69 85 mA Max Outputs 3-STATE CIN Input Capacitance 8.0 pF 5.0 Control Pins 17.0 pF 5.0 An, B n 4.75 All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded −100 3 VOUT = 2.7V (An, Bn) www.fairchildsemi.com 74FR543 Absolute Maximum Ratings(Note 1) 74FR543 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.3 3.0 4.7 1.3 4.7 tPHL An to Bn or Bn to An 1.3 2.6 4.7 1.3 4.7 tPLH Propagation Delay 2.3 5.7 8.5 2.3 8.5 tPHL LEAB to B, LEBA to A 2.3 4.0 8.5 2.3 8.5 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 2.3 4.3 7.4 2.3 7.4 2.3 4.9 7.4 2.3 7.4 1.6 3.9 7.0 1.6 7.0 1.6 3.5 7.0 1.6 7.0 Units ns ns ns ns AC Operating Requirements Symbol Parameter Min TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Typ Max Min tS(H) Setup Time, HIGH or LOW 2.5 0.5 2.5 tS(L) Dn to LE 2.5 0.1 2.5 tH(H) Hold Time, HIGH or LOW 2.0 0.0 2.0 tH(L) Dn to LE 2.0 −0.6 2.0 tW(H) LE Pulse Width HIGH 6.0 3.6 6.0 Units Max ns ns ns Extended AC Electrical Characteristics Symbol Parameter TA = 0°C to +70°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 250 pF Eight Outputs Switching (Note 4) Units (Note 3) Max Min tPLH Propagation Delay 1.3 6.3 3.2 8.7 tPHL An to Bn or Bn to An 1.3 6.3 3.2 8.7 tPLH Propagation Delay 2.3 10.2 4.2 12.8 tPHL LEAB to B, LEBA to A 2.3 10.2 4.2 12.8 tPZH Output Enable Time 2.3 11.1 2.3 11.1 Output Disable Time 1.6 7.2 1.6 7.2 tPZL tPHZ tPLZ tOSHL Pin-to-Pin Skew (Note 5) for HL Transitions tOSLH Pin-to-Pin Skew (Note 5) for LH Transitions tOST Pin-to-Pin Skew (Note 5) for HL/LH Transitions Min Max ns ns ns ns 1.2 ns 1.0 ns 3.1 ns Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW, (tOSHL), LOW-to-HIGH, (tOSLH), or HIGH-to-LOW and/or LOW-to-HIGH, (tOST). Specifications guaranteed with all outputs switching in phase. www.fairchildsemi.com 4 74FR543 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74FR543 Octal Latched Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6