Revised October 1999 74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs General Description Features The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. ■ Inputs and outputs on opposite sides of package allowing easy interface with microprocessors The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides. ■ ICC and IOZ reduced by 50% ■ Useful as input or output port for microprocessors ■ Functionally identical to 74AC373 and 74ACT373 ■ 3-STATE outputs for bus interfacing ■ Outputs source/sink 24 mA ■ 74ACT573 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC573SJ 74AC573MTC MTC20 74AC573PC 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body 74ACT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT573MTC MTC20 74ACT573PC N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 Description Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009973 www.fairchildsemi.com 74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs November 1988 74AC573 • 74ACT573 Functional Description present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was Truth Table Inputs Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) −0.5V to VCC + 0.5V AC Devices VIN from 30% to 70% of VCC ±50 mA VCC @ 3.0V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns ACT Devices ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Source or Sink Current (IO) AC VIN from 0.8V to 2.0V −65°C to +150°C VCC @ 4.5V, 5.5V Junction Temperature (TJ) (PDIP) 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 140°C DC Electrical Characteristics for AC Symbol Parameter (V) VIH VIL VOH TA = +25°C VCC Typ TA = −40°C to +85°C Units Conditions Guaranteed Limits Minimum HIGH Level 3.0 1.5 2.1 2.1 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.002 0.1 0.1 VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V VIN = VIL or VIH VOL V IOH = −12 mA IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 ±0.1 ±1.0 µA VI = VCC, GND 75 mA VOLD = 1.65V Max V IOUT = 50 µA VIN = VIL or VIH IIN (Note 3) Maximum Input Leakage Current 5.5 IOLD Minimum Dynamic 5.5 5.5 IOHD Output Current (Note 4) ICC Maximum Quiescent (Note 3) Supply Current IOZ Maximum 3-STATE Leakage Current V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) −75 mA VOHD = 3.85V Min 5.5 4.0 40.0 µA VIN = VCC or GND 5.5 ±0.25 ±2.5 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74AC573 • 74ACT573 Absolute Maximum Ratings(Note 1) 74AC573 • 74ACT573 AC Electrical Characteristics for AC Symbol Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 5) Min Typ Max Min Max tPHL Propagation Delay 3.3 0.5 8.5 10.5 2.5 11.0 tPLH Dn to On 5.0 1.5 5.5 7.0 1.5 7.5 tPLH Propagation Delay 3.3 2.5 8.5 12.0 2.5 12.5 tPHL LE to On 5.0 2.0 6.0 8.0 2.0 8.5 tPZL Output Enable Time 3.3 2.5 8.5 13.0 2.5 13.5 5.0 1.5 6.0 8.5 1.5 9.0 3.3 1.0 9.0 14.5 1.0 15.0 5.0 1.0 6.0 9.5 1.0 10.0 tPZH Output Disable Time tPHZ tPLZ Units ns ns ns ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V AC Operating Requirements for AC Symbol tS tH tW Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 6) Typ Setup Time, HIGH or LOW 3.3 0 3.0 3.0 Dn to LE 5.0 0 3.0 3.0 Hold Time, HIGH or LOW 3.3 0 1.5 1.5 Dn to LE 5.0 0 1.5 1.5 LE Pulse Width, HIGH 3.3 2.0 4.0 4.0 5.0 2.0 4.0 4.0 Note 6: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V www.fairchildsemi.com 4 Units Guaranteed Minimum ns ns ns Symbol VIH VIL Parameter TA = −40°C to +85°C (V) Typ Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 5.5 1.5 0.8 Input Voltage VOH TA = +25°C VCC Guaranteed Limits Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 7) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current ICCT Maximum IOL = 24 mA (Note 7) VI = VCC, GND VI = VIL, VIH VO = VCC, GND 1.5 mA VI = VCC − 2.1V Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 8) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA VIN = VCC or GND 5.5 ICC/Input IOLD Supply Current 0.6 5.5 4.0 Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for ACT Symbol Parameter tPLH Propagation Delay tPHL Dn to On tPLH Propagation Delay LE to On tPHL Propagation Delay LE to On VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 9) Min Typ Max Min Max 5.0 2.5 6.0 10.5 2.0 12.0 ns 5.0 3.0 6.0 10.5 2.5 12.0 ns 5.0 2.5 5.5 9.5 2.0 10.5 ns tPZH Output Enable Time 5.0 2.0 5.5 10.0 1.5 11.0 ns tPZL Output Enable Time 5.0 1.5 5.5 9.5 1.5 10.5 ns tPHZ Output Disable Time 5.0 2.5 6.5 11.0 1.5 12.5 ns tPLZ Output Disable Time 5.0 1.5 5.0 8.5 1.0 9.5 ns Note 9: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.fairchildsemi.com 74AC573 • 74ACT573 DC Electrical Characteristics for ACT 74AC573 • 74ACT573 AC Operating Requirements for ACT Symbol Parameter Setup Time, HIGH or LOW tS Dn to LE tH Hold Time, HIGH or LOW Dn to LE tW LE Pulse Width, HIGH VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum 5.0 1.5 3.0 3.5 ns 5.0 −1.5 0 0 ns 5.0 2.0 3.5 4.0 ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance for AC for ACT www.fairchildsemi.com Units (Note 10) Typ Units 5.0 pF VCC = OPEN pF VCC = 5.0V 25.0 42.0 6 Conditions 74AC573 • 74ACT573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com 74AC573 • 74ACT573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74AC573 • 74ACT573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com 74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10