CY22180 PRELIMINARY Very Low Jitter Field and Factory Programmable Clock Generator Features Benefits • Low period and cycle-to-cycle jitter — Typical pk-pk period jitter: 60 ps • Wide output frequency range — Commercial temperature: 20–200 MHz — Industrial temperature: 20–166 MHz • Input frequency range — External crystal: 10–30 MHz fundamental crystal • • • • • • — External reference: 10–133 MHz clock Integrated phase-locked loop (PLL) Field programmable and factory programmed options Programmable crystal load capacitor tuning array 3.3V operation Commercial and industrial temperature ranges Power down or output enable function • Internal PLL generates up to 200 MHz output. Can generate custom frequencies from an external crystal or a driven source. • In-house programming of samples and prototype quantities can be done using the CY3672-USB programmer and CY3619 socket adapter. Production quantities are available through Cypress’s value added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. • Eliminates the need for expensive and difficult to use higher-order crystals. • Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal. Eliminates the need for external CLoad capacitors. • Application compatibility in standard and low-power systems • Enables low-power state or output clocks to High-Z state. Logic Block Diagram Pin Configuration CY22180 8-pin SOIC PLL 1 6 OUTPUT DIVIDER XIN/CLKIN CLKOUT CXIN 1 XIN/CLKIN PROGRAMMABLE CONFIGURATION 8 2 VDD XOUT 8 NC 7 XOUT CXOUT 5 3 PD#/OE CLKOUT 6 4 VSS REFOUT 5 REFOUT 3 PD# or OE 2 4 VDD VSS Cypress Semiconductor Corporation Document #: 001-15577 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 10, 2007 CY22180 PRELIMINARY Pin Description Pin Name Description 1 XIN/CLKIN Crystal input or reference clock input. 2 VDD 3.3V power supply. 3 PD#/OE Power down pin, active LOW. If PD# = 0, the PLL and oscillator are powered down and outputs are weakly pulled low. Output enable pin, active HIGH. If OE = 1, CLKOUT and REFOUT are enabled. User has the option of choosing either PD# or OE function. 4 VSS Power supply ground. 5 REFOUT Buffered reference output. 6 CLKOUT Low jitter clock output. 7 NC No connect. Leave this pin floating. 8 XOUT Crystal output. Leave this pin floating if external clock is used. General Description The CY22180 is a low jitter clock generator for use in networking, telecommunication, datacom, consumer electronics, and other general purpose applications. The CY22180 offers a single programmable output and an optional copy of the input frequency. The on-chip reference oscillator is designed to run off a 10–30 MHz crystal, or a 10–133 MHz external clock signal. The output frequency range is 20–200 MHz. The CY22180 comes in an 8-pin SOIC, and requires a 3.3V power supply. Programming Description Field Programmable (CY22180FSXC and CY22180FSXI) The CY22180 is programmed at the package level, that is, in a programmer socket. The CY22180 is flash technology based, so the parts can be reprogrammed up to 100 times. This enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Samples and small prototype quantities can be programmed on the CY3672 programmer with the CY3619 socket adapter. CyberClocks™ Online Software CyberClocks Online Software is a web-based software application that allows the user to custom-configure the CY22180. All the parameters in Table 1 given as “Enter Data” can be programmed into the CY22180. CyberClocks Online outputs an industry-standard JEDEC file used for programming the CY22180. CyberClocks Online is available at www.cyberclocksonline.com through user registration. For more information on the registration process refer to the CY3672 data sheet. CY3672-USB Programming Kit and CY3619 Socket Adapter The Cypress CY3672 FTG programmer and CY3619 socket adapter are needed to program the CY22180. The socket adapter comes with small prototype quantities of CY22180. The CY3619 can be ordered separately, so existing users of the CY3672-USB programmer need order only the socket adapters to program the CY22180. Factory Programmed CY22180 Factory programming is available for volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number (dash number) and samples with the programmed values. This part number will be used for additional sample requests and production orders. Additional information on the CY22180 can be obtained from the Cypress website at www.cypress.com. Table 1. Pin Function Input Frequency Total Xtal Load Capacitance Output Frequency Reference Output Power-down or Output Enable Pin Name XIN and XOUT XIN and XOUT CLKOUT REFOUT PD#/OE Pin# 1 and 8 1 and 8 6 5 3 Unit MHz pF MHz On or Off Select PD# or OE Program Value ENTER DATA ENTER DATA ENTER DATA ENTER DATA ENTER DATA Document #: 001-15577 Rev. ** Page 2 of 8 CY22180 PRELIMINARY Product Functions Output Clock (CLKOUT, pin 6) Input Frequency (XIN, pin 1 and XOUT, pin 8) The output clock can be programmed to any frequency in the range of 20–200 MHz. The input to the CY22180 can be a crystal or a clock. The input frequency range for crystals is 10 to 30 MHz, and for clock signals is 10 to 133 MHz. Reference Output (REFOUT, pin 5) CXIN and CXOUT (pin 1 and pin 8) The internal load capacitors at pin 1 (CXIN) and pin 8 (CXOUT) can be programmed from 12 pF to 60 pF in 0.5-pF increments. Thus, these programmable capacitors support crystals with CL values between 6 pF and 30 pF. The crystal CL value, minus board parasitic capacitance, is the value entered into CyberClocks Online Software. If using a driven reference, CyberClocks Online Software will set CXIN and CXOUT to the minimum value 12 pF. The reference clock output has the same frequency as the input clock. This output can be programmed to be enabled (clock on) or disabled (High-Z, clock off) through CyberClocks Online software. If this output is not needed, Cypress recommends that users request the disabled (High-Z, Clock Off) option. Power Down or Output Enable (PD# or OE, pin 3) The CY22180 can be programmed to include either PD# or OE function. PD# function can be used to power down the oscillator and PLL. The OE function disables the outputs but does not turn off the PLL. PD# achieves lower power consumption, but PLL start up time means that turn-on time is slower than for OE. Absolute Maximum Ratings Supply Voltage (VDD) ........................................–0.5 to +7.0V Data Retention @ Tj = 125°C................................> 10 years DC Input Voltage...................................... –0.5V to VDD + 0.5 Package Power Dissipation...................................... 350 mW Storage Temperature (Non-condensing)..... –55°C to +125°C Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015) Junction Temperature ................................ –40°C to +125°C Recommended Crystal Specifications Parameter Description Comments Min. Typ. Max. Unit Parallel resonance, fundamental mode, AT cut 10 – 30 MHz FNOM Nominal Crystal Frequency CLNOM Nominal Load Capacitance 6 – 30 pF R1 Equivalent Series Resistance (ESR) Fundamental mode – – 25 Ω DL Crystal Drive Level – 0.5 2 mW Min. Typ. Max. Unit 3.13 3.30 3.45 V 0 – 70 °C –40 – 85 °C No external series resistor assumed Operating Conditions Parameter Description VDD Supply Voltage TA Ambient Commercial Temperature Ambient Industrial Temperature CLOAD Max. Load Capacitance @ pin 5 and pin 6 – – 10 pF FXIN External Reference Crystal 10 – 30 MHz FCLKIN External Reference Clock 10 – 133 MHz FCLKOUT CLKOUT frequency, Commercial Temperature 20 – 200 MHz CLKOUT frequency, Industrial Temperature 20 – 166 MHz FREFOUT REFOUT frequency 10 – 133 MHz TPU Power-up time for all VDDs to reach minimum specified voltage (power ramp must be monotonic) 0.05 – 500 ms Document #: 001-15577 Rev. ** Page 3 of 8 CY22180 PRELIMINARY l DC Electrical Characteristics Min Typ IOH Parameter Output High Current Description VOH = VDD – 0.5V, VDD = 3.3V (source) Condition 10 12 Max Unit mA IOL Output Low Current VOL = 0.5V, VDD = 3.3V (sink) 10 12 mA VIH Input High Voltage CMOS levels, 70% of VDD 0.7VDD – VDD + 0.3 V VIL Input Low Voltage CMOS levels, 30% of VDD –0.3 – 0.3VDD V IIH – – 10 μA IIL Input High Current, PD#/OE VIN= VDD Input Low Current, PD#/OE VIN = VSS, pull up disabled – – 10 μA – – IOZ Output Leakage Current VIN = VSS, pull up enabled CXIN or CXOUT  Three-state output, PD#/OE = 0 Programmable Capacitance Capacitance at minimum setting at pin 1 and pin 8 Capacitance at maximum setting –10 55 μA 10 μA – 12 – pF – 60 – pF – 5 7 pF CIN Input Capacitance at PD#/OE IDD Supply Current fIN = 10 MHz, fOUT = 33 MHz, REFOUT off – 11 15 mA IDDS Standby current Device powered down with PD# = 0V (driven reference pulled down) – 10 40 μA Min Typ Max Unit AC Electrical Characteristics Parameter DC Description Condition Output Duty Cycle CLKOUT < 125 MHz, Measured at VDD/2 45 50 55 % Output Duty Cycle CLKOUT > 125 MHz, Measured at VDD/2 40 50 60 % Output Duty Cycle REFOUT, Measured at VDD/2 Duty Cycle of CLKIN = 50% 45 50 55 % SR1 Rising Edge Slew Rate CLKOUT from 20 to 200 MHz; REFOUT from 10 to 133 MHz. 20%–80% of VDD 2 3 – V/ns SR2 Falling Edge Slew Rate CLKOUT from 20 to 200 MHz; REFOUT from 10 to 133 MHz. 80%–20% of VDD 2 3 – V/ns TPJ1[2, 3] CLKOUT pk-pk Period Jitter, REFOUT off CLKOUT = 20–200 MHz – – 75 (±38) ps TPJ2[2, 3] CLKIN = 10 MHz, CLKOUT = 20, 33, 66, 80, CLKOUT pk-pk Period Jitter, REFOUT off, specific 106.25, 125, 133, or 200 MHz frequencies CLKIN = 25 MHz, CLKOUT = 125 MHz – – 60 (±30) ps – – 56 (±28) ps CLKIN = 30 MHz, CLKOUT = 33, 66, 80, 106.25, 125, or 133 MHz – – 62 (±31) ps CLKIN = 66 MHz, CLKOUT = 33 or 66 MHz – – 47 (±24) ps CLKIN = 66 MHz, CLKOUT = 80, 106.25, 125, 133, 166, or 200 MHz – – 68 (±34) ps CLKIN = 133 MHz, CLKOUT = 33, 66, or 80 MHz – – 68 (±34) ps CLKIN = 133 MHz, CLKOUT = 125, 133, or 166 MHz – – 52 (±26) ps Notes 1. Guaranteed by characterization, not 100% tested. 2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, temperature, and output load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions”. 3. Cycle-to-Cycle Jitter (peak) is always less than Period Jitter (peak-to-peak). Peak-to-Peak Period Jitter is the difference between the shortest and longest measured periods. Document #: 001-15577 Rev. ** Page 4 of 8 CY22180 PRELIMINARY AC Electrical Characteristics Min Typ Max Unit TPJ3[2, 3] Parameter CLKOUT pk-pk Period Jitter, REFOUT on Description CLKOUT = 20–200 MHz Condition – 150 (±75) – ps TPJ4[2, 3] REFOUT pk-pk Period Jitter REFOUT = 10-133 MHz – – 265 (±133) ps tSTP Power Down Time (pin 3 = PD#) Time from falling edge on PD# to stopped outputs (Asynchronous) – 150 350 ns TOE1 Output Disable Time (pin 3 = OE) Time from falling edge on OE to stopped outputs (Asynchronous) – 150 350 ns TOE2 Output Enable Time (pin 3 = OE) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – 150 350 ns tPU1 Power Up Time, Crystal is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous) – 3.5 5 ms tPU2 Power Up Time, Reference clock is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous), reference clock at correct frequency – 2 3 ms Application Circuits[4, 5] Crystal Power 1 XIN/CLKIN CLKIN XOUT 8 1 XIN/CLKIN XOUT 8 no connect NC 7 no connect Power 2 VDD 0.1uF VDD or control NC 7 CY22180 3 PD#/OE CLKOUT 6 4 VSS REFOUT 5 no connect 2 VDD 0.1uF VDD or control CY22180 3 PD#/OE CLKOUT 6 4 VSS REFOUT 5 Notes 4. Since the load capacitors (CXIN and CXOUT) are provided by the CY22180, no external capacitors are needed on the XIN and XOUT pins to match the crystal load capacitor (CL). Only a single 0.1-μF bypass capacitor is required on the VDD pin. 5. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected). Document #: 001-15577 Rev. ** Page 5 of 8 CY22180 PRELIMINARY Switching Waveforms Figure 1. Duty Cycle Timing (DC = t1A/t1B) OUTPUT t1A t1B Figure 2. Output Rise/Fall Time (CLKOUT and REFOUT) VDD OUTPUT 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Figure 3. Power Down Timing and Power Up Timing POWER DOWN VDD 0V VIH VIL tPU High Impedance CLKOUT (Asynchronous) tSTP Figure 4. Output Enable/Disable Timing OUTPUT ENABLE VDD 0V VIH VIL TOE2 High Impedance CLKOUT (Asynchronous) TOE1 Document #: 001-15577 Rev. ** Page 6 of 8 CY22180 PRELIMINARY Ordering Information Part Number Description Product Flow CY22180FSXC Field Programmable, Pb-free Commercial, 0 to 70°C CY22180FSXI Field Programmable, Pb-free Industrial, –40 to 85°C CY22180SXC-xxx Factory Programmed, Pb-free Commercial, 0 to 70°C CY22180SXC-xxxT Factory Programmed, Tape and Reel - Pb-free Commercial, 0 to 70°C CY22180SXI-xxx Factory Programmed, Pb-free Industrial, –40 to 85°C CY22180SXI-xxxT Factory Programmed, Tape and Reel - Pb-free Industrial, –40 to 85°C CY3672-USB FTG programmer n/a CY3619 CY22180FSXC and CY22180FSXI Socket adapter n/a Package Diagrams Figure 5. 8-Lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Note 6. “xxx” denotes the assigned product dash number for devices that are factory-programmed. Document #: 001-15577 Rev. ** Page 7 of 8 CY22180 PRELIMINARY Document History Page Document Title: CY22180 Very Low Jitter Field and Factory Programmable Clock Generator Document Number: 001-15577 REV. ECN NO. Issue Date ** 1058460 See ECN Document #: 001-15577 Rev. ** Orig. of Change Description of Change KVM/ New Data Sheet KKVTMP Page 8 of 8 © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.