FAIRCHILD 74LCXH162373GX

Revised March 2002
74LCXH162373
Low Voltage 16-Bit Transparent Latch
with Bushold and 26Ω Series Resistor Outputs
General Description
Features
The LCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
■ 5V tolerant control inputs and outputs
The LCXH162373 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
signal environment. The 26Ω series resistor helps reduce
output overshoot and undershoot.
■ 2.3V–3.6V VCC specifications provided
■ Equivalent 26Ω series resistors on outputs
■ Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
■ 6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
■ Power down high impedance inputs and outputs
■ ±12 mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
The LCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation.
■ ESD performance:
The LCXH162373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
74LCXH162373GX
(Note 1)
Package
Number
BGA54A
(Preliminary)
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LCXH162373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74LCXH162373MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LCXH162373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74LCXH162373MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500445
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74LCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26Ω Series Resistor Outputs
February 2001
74LCXH162373
Connection Diagrams
Pin Descriptions
Pin Assignment for SSOP and TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
LEn
Latch Enable Input
I0–I15
Inputs (Bushold)
O0–O15
Outputs (Bushold)
NC
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O0
NC
OE1
LE1
NC
I0
B
O2
O1
NC
NC
I1
I2
C
O4
O3
VCC
VCC
I3
I4
D
O6
O5
GND
GND
I5
I6
E
O8
O7
GND
GND
I7
I8
F
O10
O9
GND
GND
I9
I10
I12
G
O12
O11
VCC
VCC
I11
H
O14
O13
NC
NC
I13
I14
J
O15
NC
OE2
LE2
NC
I15
Truth Tables
Inputs
Pin Assignment for FBGA
Outputs
LE1
OE1
I0–I7
O0–O7
Z
X
H
X
H
L
L
L
H
L
H
H
L
L
X
O0
Inputs
(Top Thru View)
Outputs
LE2
OE2
I8–I15
O8–O15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
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2
The LCXH162373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The
3-STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74LCXH162373
Functional Description
74LCXH162373
Absolute Maximum Ratings(Note 2)
Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
Value
I0 - I15
Units
V
−0.5 to VCC + 0.5
V
−0.5V to 7.0V
OEn, LEn
VO
Conditions
−0.5 to +7.0
−0.5 to +7.0
DC Output Voltage
Output in 3-STATE
−0.5 to VCC + 0.5
Output in HIGH or LOW State (Note 3)
IIK
DC Input Diode Current
−50
VI < GND
IOK
DC Output Diode Current
−50
VO < GND
+50
VO > VCC
V
mA
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature
−65 to +150
°C
Recommended Operating Conditions (Note 4)
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Output Current
TA
Free-Air Operating Temperature
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
0
VCC
HIGH or LOW State
0
VCC
3-STATE
0
5.5
VCC = 3.0V − 3.6V
±12
VCC = 2.7V − 3.0V
±8
VCC = 2.3V − 2.7V
±4
Units
V
V
V
mA
−40
85
°C
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
II
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
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IOH = −100 µA
VCC
TA = −40°C to +85°C
(V)
Min
2.3 − 2.7
1.7
2.7 − 3.6
2.0
V
2.3 − 2.7
0.7
2.7 − 3.6
0.8
2.3 − 3.6
VCC − 0.2
IOH = −4 mA
2.3
1.8
IOH = −4 mA
2.7
2.2
IOH = −6 mA
3.0
2.4
IOH = −8 mA
2.7
2.0
IOH = −12 mA
3.0
2.0
IOL = 100 µA
2.3 − 3.6
0.2
2.3
0.6
IOL = 4 mA
2.7
0.4
IOL = 6 mA
3.0
0.55
IOL = 8 mA
2.7
0.6
IOL = 12 mA
3.0
0.8
2.3 − 3.6
±5.0
4
V
V
IOL = 4 mA
VI = VCC or GND
Units
Max
V
µA
Symbol
(Continued)
Parameter
TA = −40°C to +85°C
VCC
Conditions
(V)
II(HOLD)
Bushold Input Minimum
VIN = 0.7V
Drive Hold Current
VIN = 1.7V
(Note 6)
Current to Change State
(Note 7)
0 ≤ VO ≤ 5.5V
IOFF
Power-Off Leakage Current
VO = VCC
ICC
Quiescent Supply Current
Increase in ICC per Input
300
−300
µA
450
−450
2.3 − 3.6
±5.0
µA
0
10
µA
VI = VCC or GND
2.3 − 3.6
20
3.6V ≤ VO ≤ 5.5V (Note 5)
2.3 − 3.6
±20
VIH = VCC −0.6V
2.3 − 3.6
500
VI = VIH or VIL
∆ICC
−75
3.6
(Note 7)
3-STATE Output Leakage
µA
75
2.7
(Note 6)
IOZ
−45
3.0
VIN = 2.0V
Bushold Input Over-Drive
Units
Max
45
2.3
VIN = 0.8V
II(OD)
Min
µA
µA
Note 5: Outputs disabled or 3-STATE only.
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Min
Max
Min
Max
Min
tPHL
Propagation Delay
1.5
6.2
1.5
6.7
1.5
7.4
tPLH
In to On
1.5
6.2
1.5
6.7
1.5
7.4
tPHL
Propagation Delay
1.5
6.3
1.5
7.2
1.5
7.6
tPLH
LE to On
1.5
6.3
1.5
7.2
1.5
7.6
tPZL
Output Enable Time
1.5
6.9
1.5
7.3
1.5
9.0
1.5
6.9
1.5
7.3
1.5
9.0
1.5
6.0
1.5
6.3
1.5
7.2
1.5
6.0
1.5
6.3
1.5
7.2
tPZH
tPLZ
Output Disable Time
tPHZ
Units
Max
ns
ns
ns
ns
tS
Setup Time, In to LE
2.5
2.5
3.0
ns
tH
Hold Time, In to LE
1.5
1.5
2.0
ns
tW
LE Pulse Width
3.0
3.0
3.5
ns
tOSHL
Output to Output Skew (Note 8)
1.0
tOSLH
1.0
ns
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
5
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74LCXH162373
DC Electrical Characteristics
74LCXH162373
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
Conditions
VCC
(V)
TA = 25°C
Typical
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.25
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
−0.35
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
−0.25
0.35
Units
V
V
Capacitance
Typical
Units
CIN
Symbol
Input Capacitance
Parameter
VCC = Open, VI = 0V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
20
pF
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Conditions
6
74LCXH162373
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V, and 2.7V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH, tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f = 1 MHz, tr = tf = 3 ns)
Symbol
VCC
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH − 0.3V
VOH − 0.3V
VOH − 0.15V
7
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74LCXH162373
Schematic Diagram Generic for LCX Family
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8
74LCXH162373
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
Preliminary
9
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74LCXH162373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
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10
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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11
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74LCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26Ω Series Resistor Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)