FAIRCHILD 74F64SJ

Revised March 1999
74F64
4-2-3-2-Input AND-OR-Invert Gate
General Description
This device contains gates configured to perform a 4-2-3-2
input AND-OR-INVERT function.
Ordering Code:
Order Number
Package Number
Package Description
74F64SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F64SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F64PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Pin Names
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
Description
An, Bn, Cn, Dn
Inputs
1.0/1.0
20 µA/−0.6 mA
O
Output
50/33.3
−1 mA/20 mA
© 1999 Fairchild Semiconductor Corporation
DS009467.prf
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74F64 4-2-3-2-Input AND-OR-Invert Gate
April 1988
74F64
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
twice the rated IOL (mA)
in LOW State (Max)
DC Electrical Characteristics
Symbol
Parameter
VCC
Units
Conditions
VIH
Input HIGH Voltage
V
VIL
Input LOW Voltage
V
VCD
Input Clamp Diode Voltage
V
Min
IIN = −18 mA
VOH
Output HIGH
V
Min
IOH = −1 mA
V
Min
IOL = 20 mA
µA
Max
VIN = 2.7V
µA
Max
VIN = 7.0V
10% VCC
Voltage
5% VCC
VOL
Output LOW Voltage
10% VCC
IIH
Input HIGH
Recognized as a HIGH Signal
Recognized as a LOW Signal
IOH = −1 mA
Current
IBVI
Input HIGH Current
Breakdown Test
ICEX
Output High Leakage Current
µA
Max
VOUT = VCC
VID
Input Leakage
V
0.0
IID = 1.9 µA
µA
0.0
VIOD = 150 mV
Test
IOD
All Other Pins Grounded
Output Leakage
Circuit Current
All Other Pins Grounded
VIN = 0.5V
IIL
Input LOW Current
mA
Max
IOS
Output Short-Circuit Current
mA
Max
VOUT = 0V
ICCH
Power Supply Current
mA
Max
VO = HIGH
ICCL
Power Supply Current
mA
Max
VO = LOW
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
TA = 0° to +70°C
VCC = +5.0V
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
2.5
4.6
6.5
2.5
7.5
tPHL
An, Bn, Cn, Dn to O
1.5
3.2
4.5
1.5
5.5
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2
Units
ns
74F64
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
3
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74F64 4-2-3-2-Input AND-OR-Invert Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
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SEMICONDUCTOR CORPORATION. As used herein:
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1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
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device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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