TC90A53N/F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC90A53N,TC90A53F 3-LINE DIGITAL Y / C SEPARATOR IC TC90A53N / F is a 3-line digital Y / C separator IC which separates luminance signal Y and chroma signal C from composite video signals. Toshiba’s logical comb filter realizes good Y / C separation at low cost. FEATURES · TV format : NTSC (3.58) · Dynamic comb filter · Vertical edge enhancement circuit · PLL 4 × multiplier circuit · Internal 8-bit 4 fsc AD converter · Internal 8-bit 4 fsc DA converter (2 ch) · 1-line color dot interference reducer circuit · Sync tip clamp circuit · Internal 2H-line memory · Color killer mode (Y / C separation off) · Chroma signal C output wide band mode · Package : SDIP 28-pin and SOP 28-pin · 5 V single power supply Weight: SDIP28-P-400-1.78: 1.7 g (Typ.) SOP28-P-450-1.27: 0.8 g (Typ.) 000707EBA1 · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 2001-02-08 1/17 TC90A53N/F BLOCK DIAGRAM 2001-02-08 2/17 TC90A53N/F PIN CONNECTION PIN FUNCTION PIN No. PIN NAME FUNCTION PIN No. PIN NAME FUNCTION L : C-BPF = Wide Band H : Narrow Band 1 VREFL ADC Bias 15 CBPF 2 VSS1 ADC GND 16 VENH0 3 VDD1 ADC Power Supply 17 VENH1 4 VREFH ADC Bias 18 1LINE L : 1-line Color ON H : 1-line Color OFF 5 ADIN Video Signal Input 19 CORING L : Coring ON (2LSB) H : Coring OFF (0LSB) 6 BIAS1 ADC Bias 20 VDD3 Digital Power Supply 7 CLAMPC Clamp Circuit Filter 21 VSS3 Digital GND 8 TEST1 Test Pin 22 BIAS3 DAC Bias 9 1 / 2 VDD Line Memory Bias 23 COUT C Output 10 VFIL VCO Filter 24 BIAS2 DAC Bias 11 CKIN Clock Input 25 YOUT Y Output 12 VDD2 PLL Power Supply 26 VREF1 DAC Bias 13 VSS2 PLL GND 27 VDD4 DAC Power Supply 14 KILLER L : Color Mode H : Black And White Mode 28 VSS4 DAC GND Sets Vertical Enhance Amount. (VENH0, VENH1) = (L, L) = Small (H, L) = Small (L, H) = Medium, (H, H) = Large (Note) : Pins 9 and 26 need external bias. 2001-02-08 3/17 TC90A53N/F PIN FUNCTION PIN No. PIN NAME FUNCTION I/O INTERFACE 1 VREFL ADC bias pin. Sets lower limit of range D for ADC. Fixed internally to 1.5 V (typ.). Connect 0.01 mF capacitor between this pin and GND. 2 VSS1 ADC GND ¾ ¾ 3 VDD1 ADC power supply (+5 V) ¾ ¾ 4 VREFH ADC bias pin. Sets upper limit of range D for ADC. Fixed internally to 3.5 V (typ.). Connect 0.01 mF capacitor between this pin and GND. ¾ 5 ADIN Composite video signal input pin. 6 BIAS1 ADC bias pin. Fixed internally to 1.3 V (typ.). Connect 0.01 mF capacitor between this pin and GND. ¾ 7 CLAMPC External filter used for Sync tip clamping the input composite video signal. Connect 510 kW and 4700 pF between this pin and GND. ¾ 8 TEST Test pin. Connect GND. ¾ 9 1 / 2 VDD Line-memory bias. Supply 1 / 2 VDD by dividing digital power supply using a resistor. Connect 0.01 mF capacitor between this pin and GND. ¾ I ¾ I 2001-02-08 4/17 TC90A53N/F PIN No. PIN NAME 10 VFIL Connect a VCO filter. 11 CKIN Inputs clock. First DC-cut fsc clock in sync with color burst using a capacitor, then input the result. 12 VDD2 PLL power supply (+5 V) ¾ ¾ 13 VSS2 PLL GND ¾ ¾ 14 KILLER 15 CBPF FUNCTION I/O INTERFACE ¾ I Selects color killer mode. L : Color mode H : Black and white mode (Y / C sep off) I Selects color signal horizontal band. L : Wide band (does not pass BPF) H : Narrow band (passes BPF) I Select vertical enhance amount. VENH0 VENH1 16 17 18 VENH0 VENH1 1 LINE L L : Small (+0.25) H L : Small (+0.25) L H : Medium (+0.75) H H : Large (+1.25) 1-line color dot interference reducer ON / OFF L : 1-line color dot interference reducer ON H : 1-line color dot interference reducer OFF I I 2001-02-08 5/17 TC90A53N/F PIN No. PIN NAME FUNCTION I/O INTERFACE Selects coring. 19 CORING L : Coring ON (2LSB) I H : Coring OFF (0LSB) 20 VDD3 Digital power supply (+5 V) ¾ ¾ 21 VSS3 Digital GND ¾ ¾ 22 BIAS3 DAC bias pin. Fixed internally to 3.5 V (typ.). Connect a 0.01 mF capacitor between this pin and GND. ¾ 23 COUT Outputs C signal. O 24 BIAS2 DAC bias pin. Fixed internally to 1.6 V (typ.). Connect a 0.01 mF capacitor between this pin and GND. ¾ 25 YOUT Outputs Y signal. O 26 VREF1 DAC bias pin. Sets lower limit of range D for DAC. Supply power by dividing power for DAC using a resistor. Recommended value : 3.0 V I 27 VDD4 DAC power supply (+5 V) ¾ ¾ 28 VSS4 DAC GND ¾ ¾ 2001-02-08 6/17 TC90A53N/F DESCRIPTION OF FUNCTIONS (1) CLAMP (Input clamp) Circuit used to Sync tip clamp composite signal. Apply feedback clamp so that at Y / C separation, the minimum data value after A / D conversion is the internally-fixed level. (2) ADC (A / D converter) High-speed series-parallel 8-bit A / D converter (Dynamic Range: 2.0V). Input composite video signal with amplitude of 1.5 Vp-p (sync to white 100%). (3) 1 H memory Line memory consisting of DRAM for 1 H delay. Two line memories configure a 3-line comb filter. Because the system clock is 4 fsc (14.3 MHz), 910 clocks / 1 H is set. (4) VENH (Vertical enhancer circuit) After coring (2LSB) the non-correlation component among the three lines of the luminance signal, this block enhances the vertical outline. The enhance amount can be selected from three settings : large (+1.25), medium (+0.75), and small (+0.25). The vertical enhance amount is added to the luminous signal obtained by subtracting the color signal from the composite signal, then the luminous signal is output via the D / A converter. Note that if the luminous signal is lower than the pedestal level (internally-fixed value), the vertical enhance amount is not added to. (5) BPF (Horizontal bandpass filter) Uses fsc as the center frequency. Filters the composite signal delayed by 0 H, 1 H, or 2 H and extracts the color signal. The bandpass filter for outputting the color signal at a later stage can be switched on or off to select output of a narrow- or wide-band color signal. (6) DCF (Vertical dynamic comb filter) Vertical bandpass filter which extracts the color signal by detecting vertical non-correlation. Using Toshiba logic, determines the correlation among three lines. If no correlation, determines as the luminous signal and suppresses output of the color signal. (7) 1-line color dot interference reducer circuit Improves color dot interference on a screen where only 1 line has color so that the C signal is processed as the Y signal. Extracts 1-line color dot component and the result is added to the output from the dynamic comb filter. (8) RTIM (Clock / memory timing generator) This block supplies × 4 fsc (14.3 MHz) obtained using the VCO via a buffer to the blocks and generates the timing signal necessary for memory. (9) PLL (× 4 clock generator) Multiplies fsc (3.58 MHz) by 4 and generates system clock 4 fsc (14.3 MHz). (10) DAC (D / A converter) High-speed 8-bit D / A converter. The output amplitudes are : Y output of 1.5 V p-p (typ.) and C output at burst level of 572 mV p-p (typ.). (11) Color killer circuit When the input video signal is a monochrome image, this circuit enables effective use of the luminance signal information regardless of whether there is a burst signal. It does this by preventing the chroma signal output from the comb filter from being subtracted from the luminance signal. While the VBI signal is active it is better not to use the comb function. Setting the KILLER pin to High at this time enables the use of character multiplex and other signals from the Y output unchanged. But since Vertical edge enhancement does not become OFF, be careful when using with Vertical edge enhancement. 2001-02-08 7/17 TC90A53N/F MODE LIST PIN14 KILLE R PIN15 CBPF PIN16 VENH0 PIN17 VENH1 PIN18 1 LINE PIN19 CORING L ¾ ¾ ¾ ¾ ¾ Y / C separation ON Color mode H ¾ ¾ ¾ ¾ ¾ Y / C separation OFF Black and white mode (killer) ¾ L ¾ ¾ ¾ ¾ Color signal horizontal band, wide Does not pass BPF for color signal output. ¾ H ¾ ¾ ¾ ¾ Color signal horizontal band, narrow Passes BPF for color signal output. ¾ ¾ L L ¾ ¾ Vertical enhance small Enhance amount : (+0.25) ¾ ¾ H L ¾ ¾ Vertical enhance small Enhance amount : (+0.25) ¾ ¾ L H ¾ ¾ Vertical enhance medium Enhance amount : (+0.75) ¾ ¾ H H ¾ ¾ Vertical enhance large Enhance amount : (+1.25) ¾ ¾ ¾ ¾ L ¾ 1-line color ON 1-line color dot interference reducer circuit ON ¾ ¾ ¾ ¾ H ¾ 1-line color OFF 1-line color dot interference reducer circuit OFF ¾ ¾ ¾ ¾ ¾ L Coring ON Coring circuit ON (2LSB) ¾ ¾ ¾ ¾ ¾ H Coring OFF Coring circuit OFF (0LSB) MODE OPERATION MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Power Supply Voltage VDD VSS~VSS + 6.0 V Input Voltage VIN -0.3~VDD + 0.3 V TC90A53N PD 900 TC90A53F (Note) 600 Tstg -55~125 Power Dissipation Storage Temperature mW °C (Note) : Ta = 75°C RECOMMENDED OPERATING CONDITIONS SYMBOL TEST CONDITION MIN TYP. MAX UNIT Power Supply Voltage VDD ¾ 4.75 5.0 5.25 V Input Voltage VIN ¾ 0 ¾ VDD V Operating Temperature Topr ¾ -10 ¾ 75 °C CHARACTERISTIC 2001-02-08 8/17 TC90A53N/F ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Ta = 25°C, VDD = 5 V) SYMBOL TEST CIRCUIT Operating Voltage VDD Operating Current IDD CHARACTERISTIC YOUT Output Voltage Level COUT TEST CONDITION MIN TYP. MAX UNIT 1 4.75 5.0 5.25 V 1 40 60 80 mA 3.0 3.15 3.3 3.9 4.0 4.1 1.4 1.5 1.6 1 VREFL VREFH Pin Voltage Level 3.4 3.5 3.6 ADIN CLOCK = 3.579545 MHz 500 mVp-p 1.5 1.6 1.8 BIAS1 VREF1 = 3.0 V 0.8 1.4 2.4 BIAS2 1 / 2 VDD = 2.5 V 0.8 1.6 2.6 VIN = No input (Note 1) 1 2.4 3.4 4.4 CLAMPC BIAS3 2.0 3.0 4.0 VFIL 0.9 1.9 2.9 CKIN 1.5 2.2 3.0 V V High Level VIH 1 4 ¾ ¾ V Low Level VIL 1 ¾ ¾ 1 V ADIN Pin Input Capacitance CIN 1 ¾ 50 ¾ pF Pull-Down Resistance RPD 1 25 50 100 kΩ Input Voltage (Note 1) : Pins 9 and 26 need external bias. 2001-02-08 9/17 TC90A53N/F AC CHARACTERISTICS Y output (Ta = 25°C, VDD = 5 V, clock frequency = 3.579545 MHz, 0.5 Vp-p, S1 = 2, VREF1 = 3.0 V) SYMBOL TEST CIRCUIT Input Level VIN 1 0~140 IRE ( Figure 2 ) Low-Frequency Gain GV 1 S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 15.734 kHz, 1.5 Vp-p Vdc = 2.5 V MTF1 1 MTF2 1 CHARACTERISTIC Frequency Characteristics Comb Characteristics Comb 1 Ls 1 Linearity (Figure 1) Ly Output Impedance Zo 1 1 TEST CONDITION S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 1.5 Vp-p Vdc = 2.5 V S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 1.5 Vp-p Vdc = 2.5 V S2 = 1, S3 = 1, S4 = 1, S5 = 2 VIN = 5-stage staircase waveform, 1.5Vp-p (Figure 2) S2 = 1, S3 = 1, S5 = 2 VIN = 15.734 kHz, 1.5 Vp-p Vdc = 2.5 V V1－V2 Zo = ´ 400 V2 MIN TYP. MAX UNIT ¾ 1.5 1.6 Vp-p -0.5 0.0 0.5 dB f2 / f1 -2.0 -1.2 -0.5 f4 / f1 -3.0 -2.0 -1.5 f2 / f3 40 45 ¾ Y1 / Y2 35 40 43 dB dB % S / Y2 57 60 63 250 400 700 W V1 : S4 = 1, V2 : S4 = 2 Clock Leakage (4 fsc component) Clock Dominant Wave Leakag (fsc component) Lck 1 S2 = 2, S3 = 2, S4 = 1, S5 = 1 VIN = No input ¾ 5.0 20 mVrms Lsc 1 S2 = 2, S3 = 2, S4 = 1, S5 = 1 VIN = No input ¾ 1.0 2.0 mVrms 2001-02-08 10/17 TC90A53N/F C output (Ta = 25°C, VDD = 5 V, clock frequency = 3.579545 MHz, 0.5 Vp-p, S1 = 1, VREF1 = 3.0 V) SYMBOL TEST CIRCUIT TEST CONDITION MIN TYP. MAX BWCW 1 Amplitude difference between fsc where S2 = 2, S3 = 2, S4 = 1, S5 = 2 and fsc - 503496 Hz VIN = 1.5 Vp-p, Vdc = 2.5 V -0.5 -0.2 ¾ BWCN 1 Amplitude difference between fsc where S2 = 2, S3 = 2, S4 = 1, S5 = 2 and fsc - 503496 Hz VIN = 1.5 Vp-p, Vdc = 2.5 V -1.0 -0.5 ¾ CV 1 S2 = 2, S3 = 2, S4 = 1, S5 = 1, VIN = fsc, 430 mVp-p -2 -0.9 -0.6 dB Comb 1 S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 430 mVp-p, Vdc = 2.5 V 30 35 ¾ dB Differential Gain DG 1 0 2 5 % Differential Phase DP 1 0 2 5 ° 250 400 700 Ω CHARACTERISTIC Wide Band BPF Characteristics Narrow Band Gain Comb Characteristics Output Impedance Zo f3 / f2 S2 = 2, S3 = 3, S4 = 1, S5 = 1, VIN = 5-stage staircase waveform, Y = 140 IRE = 1.5 Vp-p C = 40 IRE (Figure 2) DG = (Comax-Comin) / Comax (Figure 3) S2 = 2, S3 = 2, S5 = 2 VIN = 15.734 kHz, 1.5 Vp-p Vdc = 2.5 V V1－V2 Zo = ´ 400 V2 1 UNIT dB V1:S4 = 1, V2:S4 = 2 Clock Leakage (4 fsc Component) Clock Dominant Wave Leakag (fsc Component) Lck 1 S2 = 2, S3 = 2, S4 = 1, S5 = 1, VIN = No input ¾ 5.0 20 mVrms Lsc 1 S2 = 2, S3 = 2, S4 = 1, S5 = 1, VIN = No input ¾ 0.3 1.0 mVrms f1 = 15.734 kHz f2 = 3.587412 MHz f3 = 3.595279 MHz f4 = 4.783216 MHz CLOCK PLL CIRCUIT CHARACTERISTICS CHARACTERISTIC Pull-in Frequency Range (4 fsc Component) Input Amplitude (fsc Component) SYMBOL TEST CIRCUIT TEST CONDITION MIN TYP. MAX UNIT fck 1 ¾ 3.57 3.58 3.59 MHz Vck 1 ¾ 0.4 ¾ ¾ Vp-p 2001-02-08 11/17 TC90A53N/F TEST CIRCUIT 1 2001-02-08 12/17 TC90A53N/F LINEARITY TEST (Figure 1) 5-STAGE STAIRCASE SIGNAL (Figure 2) CHROMA DIFFERENTIAL GAIN (Figure 3) REFERENCE DATA (Figure 4-a) DEFINITION OF VERTICAL ENHANCE a : Vertical edge level b : enhancement level Note that output does not drop below the pedestal level (64 / 256) due to vertical outline enhance. 2001-02-08 13/17 TC90A53N/F (Flgure 4-b) VERTICAL ENHANCE CHARACTERISTICS (Figure 4-c) VERTICAL ENHANCE CHARACTERISTICS(ENLARGED) (Figure 5) FREQUENCY CHARACTERISTICS OF COLOR SIGNAL OUTPUT 2001-02-08 14/17 TC90A53N/F APPLICATION CIRCUIT 2001-02-08 15/17 TC90A53N/F PACKAGE DIMENSIONS SDIP28-P-400-1.78 Unit : mm Weight : 1.7 g (Typ.) 2001-02-08 16/17 TC90A53N/F PACKAGE DIMENSIONS SOP28-P-450-1.27 Unit : mm Weight : 0.8 g (Typ.) 2001-02-08 17/17