TC9WMA2FK TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic TC9WMA2FK 2,048-Bit (256 × 8 Bit) Serial E2PROM The TC9WMA2FK is electrically erasable/programmable nonvolatile memory (E2PROM). Features • Serial data input/output • Programmable in units of one word and collectively erasable in one operation • Automatically set programming time (built-in timer) • Programming time: 10 ms (max) (VCC = 3.0 to 5.5 V) Weight: 0.01 g (typ.) 12 ms (max) (VCC = 2.3 to 2.7 V) • Overwrite enabled or disabled by software • Single power supply and low power consumption • Operating voltage range for reading: VCC = 1.8 to 5.5 V • Operating voltage range for writing: VCC = 2.3 to 5.5 V • Wide operating temperature range (−40 to 85°C) Product Marking Pin Assignment (top view) US8 Type name CS CLK DI 8 7 6 DO 5 9WM A2 No.1 pin indicator 1 2 3 4 VCC NC RST GND 1 2007-10-19 TC9WMA2FK Block Diagram Chip select CS Clock input Timing generator Control circuit Power supply (booster circuit) VCC Power supply Reset input RST CLK Command register Data Input DI Memory cell Input/Output circuit GND Ground Address Address register decoder Data Output DO Data register Pin Function Pin Name Input/Output CS Input Chip select A low on CS selects the chip. Always return CS high temporarily before executing instructions. CLK Input Clock input The data on DI is latched by a rising edge of CLK . Data is output to DO by a falling edge of CLK . CLK is effective when CS is low. DI Input Serial data input This pin is used to enter addresses, commands, and data into the chip. DO Output Serial data output This pin outputs data from the chip. RST Input Reset input A low on this input resets the chip. NC ⎯ VCC GND Power supply Function No connection (not connected internally) 1.8 V~5.5 V (for reading) 2.3~5.5 V (for writing) 0 V (GND) 2 2007-10-19 TC9WMA2FK Functional Description 1. Types of Instructions Operation Read Address Command C0 C1 C2 C3 A0~A7 1 Program A0~A7 0 1 1 0 0 0 0 0 All erase ******** 0 0 1 1 0 0 0 0 Busy monitor ******** 1 0 1 1 0 0 0 0 Overwrite enable ******** 1 0 0 1 0 0 0 0 Overwrite disable ******** 1 1 0 1 0 0 0 0 A0~A7 1 0 0 0 1 0 0 0 Read Auto-incremented 0 0 0 0 Data 0 0 0 D0~D7 *: Don’t care 2. Operation Method Be sure to drive CS and CLK high temporarily before entering an instruction. After CS is asserted low, CLK becomes effective, acting as a serial transfer synchronizing signal. The data on DI is latched on a rising edge of CLK , while data is output to DO on a falling edge of CLK . Instructions can only be executed when the chip is not being programmed or collectively erased (i.e., when the ready/busy status signal is high). However, the Monitor Busy instruction can be entered at any time. Only the commands listed in the above table can be used. Do not use any other command. • Read Entering the Read instruction causes memory data at the specified address to be read out and serially output from the DO pin. • Program Entering the Program instruction causes overwrite operation to automatically start within the chip, overwriting memory data at the specified address with the input data. After the instruction is entered, CS can be driven high even while overwrite operation is still in progress internally. • All Erase Entering the Erase All instruction causes erase operation to automatically start within the chip, erasing memory data at all addresses. After the instruction is entered, CS can be driven high even while erase operation is still in progress internally. This command clears the memory data to 0. • Busy Monitor Entering the Monitor Busy instruction causes a ready/busy status signal to be output from the DO pin. This output signal is low while the chip is being programmed or collectively erased, and is high after programming or collective erase operation is completed. The ready/busy status signal is output continuously until CS is driven high. • Overwrite Enable/Disable Entering the Enable Overwrite instruction places the chip in overwrite enabled mode, where the Program and Erase All instructions can be entered. Entering the Disable Overwrite instruction places the chip in overwrite disabled mode, where the Program and Erase All instructions cannot be entered. Once the chip is placed in overwrite disabled mode, it remains disabled against overwriting until the Enable Overwrite instruction is entered. • Read Auto-incremented After the data at the specified address is output, the subsequent CLK pulse causes the address to be incremented so that the data at the next address is output automatically. After the data at the last address is output, that at the first address will be read and output. 3 2007-10-19 TC9WMA2FK 3. Precautions on Powering Up or Down the Chip (1) (2) (3) A wait time of 1 ms is required before the chip can start operation after it is powered up. Ensure that RST is low when powering up or down the chip. Resetting the chip places it in overwrite disabled mode. 4. Timing Chart (1) Read CS 1 2 7 8 9 10 11 12 13 14 15 16 17 23 24 CLK DI A0 A1 A6 A7 1 0 Address DO 0 0 0 0 0 0 Command D0 Hi-Z D6 D7 Hi-Z Data (2) Program CS 1 2 7 8 9 10 11 12 13 14 15 16 17 23 24 CLK DI A0 A1 Address DO A6 A7 0 1 1 0 0 0 0 0 D0 D6 D7 Command Hi-Z 4 2007-10-19 TC9WMA2FK (3) All Erase CS 1 2 7 8 9 10 11 12 13 14 15 16 CLK DI 0 0 1 1 0 0 0 0 Command DO (4) Hi-Z Busy Monitor CS 1 2 7 8 9 10 11 12 13 14 15 16 CLK DI 1 0 1 1 0 0 0 0 Command DO (5) Hi-Z Hi-Z Overwrite Enable/Disable CS 1 2 7 8 9 10 11 12 13 14 15 16 CLK Enable 1 0 0 1 0 0 0 0 1 0 0 0 0 Command DI Disable 1 1 0 Command DO Hi-Z 5 2007-10-19 TC9WMA2FK (6) Read Auto-incremented CS 1 2 7 8 9 10 11 12 13 14 15 16 17 23 24 25 31 32 33 39 40 D6 D7 D0 D6 D7 D0 D6 D7 CLK DI A0 A1 Address DO A6 A7 1 0 0 0 1 0 0 0 Command D0 Hi-Z Data A0･･･A7 Address 6 Data A0･･A7 + 1 Address Hi-Z Data A0･･A7 + 2 Address 2007-10-19 TC9WMA2FK Absolute Maximum Ratings (Note) (GND = 0 V) Characteristics Symbol Rating Unit Power supply voltage VCC −0.3~7.0 V Input voltage VIN −0.3~VCC + 0.3 V VOUT −0.3~VCC + 0.3 V Power dissipation PD 200 (25°C) mW Soldering temperature (in time) Tsld 260 (10 s) °C Storage temperature Tstg −55~125 °C Operating temperature Topr −40~85 °C Output voltage Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Operating Ranges (Note 1) (GND = 0 V, Topr = −40 to 85°C) Characteristics Symbol Test Condition Min Max Unit Supply voltage (for reading) VCC 1.8 5.5 V Supply voltage (for writing) VCC 2.3 5.5 V Operating Ranges (Note 1) (VCC = 1.8 to 2.7 V, GND = 0 V, Topr = −40 to 85°C) Characteristics Low level input voltage High level input voltage Operating frequency Symbol 1.8 V < = VCC < 2.3 V 2.3 V < = VCC < 2.7 V Min Max Min Max 0 0.15 × VCC 0 0.35 VIH1 0.7 × VCC (Note 1) VCC 1.6 VCC VIH2 0.8 × VCC (Note 2) VCC 1.8 VCC fCLK 0.25 0 0.5 VIL 0 Unit V V MHz Operating Ranges (Note 1) (VCC = 2.7 to 5.5 V, GND = 0 V, Topr = −40 to 85°C) Characteristics Low level input voltage High level input voltage Operating frequency Symbol 2.7 V < = VCC < = 3.6 V 4.5 V < = VCC < = 5.5 V Min Max Min Max 0 0.45 0 0.7 VIH1 (Note 2) 1.6 VCC 2.0 VCC VIH2 (Note 3) 2.2 VCC 3.0 VCC 0 1 0 1 VIL fCLK Unit V V MHz Note 1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note 2: CS , DI, RST Note 3: CLK 7 2007-10-19 TC9WMA2FK Electrical Characteristics D.C. Characteristics (VCC = 1.8 to 2.7 V, GND = 0 V, Topr = −40 to 85°C) Characteristics Symbol Test Condition 1.8 V < = VCC < 2.3 V 2.3 V < = VCC < 2.7 V Min Max Min Max Unit Input current ILI ⎯ ±1 ⎯ ±1 μA Output leakage current ILO ⎯ ±1 ⎯ ±1 μA IOH = −1 mA ⎯ ⎯ ⎯ ⎯ High level output voltage VOH IOH = −500 μA ⎯ ⎯ VCC − 0.4 ⎯ IOH = −100 μA VCC − 0.2 ⎯ ⎯ ⎯ IOL = 2 mA ⎯ ⎯ ⎯ ⎯ IOL = 500 μA ⎯ ⎯ 0.4 ⎯ IOL = 100 μA 0.2 ⎯ ⎯ ⎯ Low level output voltage VOL V V Quiescent supply current ICC1 (Note 1) ⎯ 5 ⎯ 5 μA Supply current during read ICC2 (Note 2) ⎯ 0.5 ⎯ 1.0 mA Supply current during all erase/program ICC3 (Note 3) ⎯ ⎯ ⎯ 1.0 mA D.C. Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Topr = −40 to 85°C) Characteristics Symbol Test Condition 2.7 V < = VCC < 3.6 V 4.5 V < = VCC < = 5.5 V Min Max Min Max Unit Input current ILI ⎯ ±1 ⎯ ±1 μA Output leakage current ILO ⎯ ±1 ⎯ ±1 μA VCC − 0.4 ⎯ VCC − 0.4 ⎯ IOH = −500 μA ⎯ ⎯ ⎯ ⎯ IOH = −100 μA ⎯ ⎯ ⎯ ⎯ IOL = 2 mA 0.4 ⎯ 0.4 ⎯ IOL = 500 μA ⎯ ⎯ ⎯ ⎯ IOL = 100 μA ⎯ ⎯ ⎯ ⎯ IOH = −1 mA High level output voltage Low level output voltage VOH VOL V V Quiescent supply current ICC1 (Note 1) ⎯ 5 ⎯ 5 μA Supply current during read ICC2 (Note 2) ⎯ 1.5 ⎯ 2.5 mA Supply current during all erase/program ICC3 (Note 3) ⎯ 1.0 ⎯ 2.0 mA Note 1: CS = 1 (except when busy, however) Note 2: Current that flows for a period between a fall of the 14th CLK pulse and a rise of the 16th CLK pulse when executing the Read instruction. Note 3: Current that flows while executing the Erase All or Program instruction. 8 2007-10-19 TC9WMA2FK A.C. Characteristics (VCC = 1.8 to 2.7 V, GND = 0 V, Topr = −40 to 85°C) Characteristics Symbol Maximum clock frequency Minimum clock pulse width Test Condition fMAX twCLK (L) twCLK (H) 1.8 V < = VCC < 2.3 V 2.3 V < = VCC < 2.7 V Unit Min Max Min Max 0 0.25 0 0.5 MHz 1.0 ⎯ 1.0 ⎯ μs Minimum reset pulse width tWRST 1 ⎯ 1 ⎯ μs Minimum chip select pulse width tWCS 1 ⎯ 1 ⎯ μs Reset setup time tRSS RST setup time when CS is switched over 1 ⎯ 1 ⎯ μs Clock setup time tCKS CLK setup time when CS is switched over 500 ⎯ 500 ⎯ ns CS setup time tCSS CS setup time when CLK is switched over 500 ⎯ 500 ⎯ ns Time from CLK switchover until valid data is output ⎯ 2.0 ⎯ 1.0 Propagation delay time tpLH tpHL tpZH tpZL tpLZ tpHZ Time from CS switchover until output data goes Hi-Z ⎯ 2.0 ⎯ 1.0 Input data setup time ts Input data setup time when CLK is switched over 500 ⎯ 500 ⎯ ns Input data hold time th Input data hold time when CLK is switched over 500 ⎯ 500 ⎯ ns (Note) μs Note: CL = 100 pF, RL = 1 kΩ 9 2007-10-19 TC9WMA2FK A.C. Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Topr = −40 to 85°C) Characteristics Symbol Maximum clock frequency Minimum clock pulse width Test Condition fMAX twCLK (L) twCLK (H) 2.7 V < = VCC < = 3.6 V 4.5 V < = VCC < = 5.5 V Unit Min Max Min Max 0 1 0 1 MHz 0.4 ⎯ 0.4 ⎯ μs Minimum reset pulse width tWRST 1 ⎯ 1 ⎯ μs Minimum chip select pulse width tWCS 1 ⎯ 1 ⎯ μs Reset setup time tRSS RST setup time when CS is switched over 1 ⎯ 1 ⎯ μs Clock setup time tCKS CLK setup time when CS is switched over 250 ⎯ 250 ⎯ ns CS setup time tCSS CS setup time when CLK is switched over 250 ⎯ 250 ⎯ ns tpLH tpHL tpZH tpZL Time from CLK switchover until valid data is output ⎯ 0.25 ⎯ 0.25 tpLZ tpHZ Time from CS switchover until output data goes Hi-Z ⎯ 0.5 ⎯ 0.5 Input data setup time ts Input data setup time when CLK is switched over 250 ⎯ 250 ⎯ ns Input data hold time th Input data hold time when CLK is switched over 250 ⎯ 250 ⎯ ns Propagation delay time (Note) μs Note: CL = 100 pF, RL = 1 kΩ 10 2007-10-19 TC9WMA2FK 2 E PROM Characteristics (GND = 0 V, 2.3 V =< VCC =< 2.7 V, Topr = −40 to 85°C) Characteristics Symbol Test Condition Min All erase time tE ⎯ Program time tP ⎯ Typ. 5 Max Unit 12 ms 12 ms Endurance NEW 1 × 10 ⎯ ⎯ Times Data retention time tRET 10 ⎯ ⎯ Year Max Unit 10 ms 10 ms 2 E PROM Characteristics (GND = 0 V, 3.0 V =< VCC =< 5.5 V, Topr = −40 to 85°C) Characteristics Symbol Test Condition Min All erase time tE ⎯ Program time tP ⎯ Typ. 5 Endurance NEW 1 × 10 ⎯ ⎯ Times Data retention time tRET 10 ⎯ ⎯ Year VCC (V) Typ. Unit 3.3 4 pF 3.3 3 pF 3.3 8.5 pF Capacitance Characteristics (Ta = 25°C) Characteristics Input capacitance Symbol Test Condition CIN Output capacitance CO Equivalent Internal capacitance CPD fIN = 1 MHz (Note) Note: CPD denotes the IC’s internal equivalent capacitance calculated from the amount of current it consumes while operating. The average current consumption during non-loaded operation is obtained from the equations below. ICC (Read) = fCLK･CPD･VCC + ICC1 + ICC2･3/24 ICC (Prog) = fCLK･CPD･VCC + ICC1 + ICC3 11 2007-10-19 TC9WMA2FK A.C. Characteristics Timing Chart tCSS tCKS tCKS tCSS VCC CS CLK VCC/2 GND VCC VCC/2 GND ts th VCC VCC/2 CLK GND VCC/2 DI tPLH tPHL tPLH tPHL VCC VCC/2 CLK GND DO VCC/2 tPLZ tPHZ CS VCC VCC/2 GND VCC CLK GND VCC/2 DO HiZ tPZH tPZL VCC VCC/2 CLK GND HiZ DO VCC/2 tWCLK (L) tWCLK (H) CLK VCC/2 VCC VCC/2 GND tWRST RST VCC/2 VCC VCC/2 GND tRSS RST VCC VCC/2 GND VCC/2 CS tWCS CS VCC/2 VCC VCC/2 tPZH tPZL CLK tPLH tPHL GND VCC VCC/2 GND DO VCC/2 12 2007-10-19 TC9WMA2FK Input/Output Circuits of Pins Pin Name Type Input/Output Circuit Remarks CS DI Input RST CLK Input Hysteresis input Output control signal DO VCC Output Initial “HiZ” 13 2007-10-19 TC9WMA2FK Package Dimensions Weight: 0.01 g (typ.) 14 2007-10-19 TC9WMA2FK RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 15 2007-10-19