TM FQG4902 250V Dual N & P-Channel MOSFET General Description Features These dual N and P-channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on half bridge. • N-Channel 0.54A, 250V, RDS(on) = 2.0 Ω @ VGS = 10 V P-Channel -0.54A, -250V, RDS(on) = 2.0 Ω @ VGS = -10 V • Low gate charge ( typical N-Channel 6.0 nC) ( typical P-Channel 12.0 nC) • Fast switching • Improved dv/dt capability D2 D2 D1 D1 8-DIP G2 S2 G1 S1 Pin #1 Absolute Maximum Ratings Symbol VDSS ID 5 4 6 3 7 2 8 1 TA = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TA = 25°C) Drain Current N-Channel 250 P-Channel -250 Units V 0.54 -0.54 A 0.34 -0.34 A (Note 1) 4.32 -4.32 A (Note 2) 5.5 - Continuous (TA = 100°C) IDM Drain Curent VGSS dv/dt PD Gate-Source Voltage Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) TJ, TSTG - Derate above 25°C Operating and Storage Temperature Range - Pulsed ± 30 -5.5 1.4 0.011 -55 to +150 V V/ns W W/°C °C Thermal Characteristics Symbol RθJA Parameter Thermal Resistance, Junction-to-Ambient ©2002 Fairchild Semiconductor Corporation (Note 5a) Typ -- Max 90 Units °C/W Rev. A1, April 2002 FQG4902 QFET Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Type Min Typ Max Units Off Characteristics BVDSS ∆BVDSS / ∆TJ IDSS Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA N-Ch 250 -- -- V VGS = 0 V, ID = -250 µA P-Ch -250 -- -- V N-Ch -- 0.24 -- V/°C P-Ch -- -0.2 -- V/°C ID = 250 µA, Referenced to 25°C ID = -250 µA, Referenced to 25°C VDS = 250 V, VGS = 0 V VDS = 200 V, TA = 125°C VDS = -250 V, VGS = 0 V VDS = -200 V, TA = 125°C N-Ch P-Ch -- -- 10 µA -- -- 100 µA -- -- -10 µA -- -- -100 µA IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V All -- -- 100 nA IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V All -- -- -100 nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 µA N-Ch 2.0 -- 4.0 V VDS = VGS, ID = -250 µA P-Ch -2.0 -- -4.0 V VGS = 10 V, ID = 0.27 A N-Ch -- 1.1 2.0 Ω VGS = -10 V, ID = -0.27 A P-Ch -- 1.5 2.0 Ω VDS = 40 V, ID = 0.27 A N-Ch -- 1.3 -- S VDS = -40 V, ID = -0.27 A P-Ch -- 1.1 -- S N-Channel VDS = 25 V, VGS = 0 V, f = 1.0 MHz P-Channel VDS = -25 V, VGS = 0 V, f = 1.0 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch ------- 195 345 40 65 7 11 250 445 55 85 9.5 14.5 pF pF pF pF pF pF N-Channel VDD = 125 V, ID = 0.54 A, RG = 25 Ω N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch --------------- 5.5 8.0 17 19 29 44 23 33 6.0 12.0 1.1 2.2 2.7 5.3 20 25 45 50 70 100 55 75 7.8 15.6 ----- ns ns ns ns ns ns ns ns nC nC nC nC nC nC Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge P-Channel VDD = -125 V, ID = -0.54 A, RG = 25 Ω (Note 3,4) ©2002 Fairchild Semiconductor Corporation N-Channel VDS = 200 V, ID = 0.54 A, VGS = 10 V P-Channel VDS = -200 V, ID = -0.54 A, (Note 3,4) VGS = -10 V Rev. A1, April 2002 FQG4902 Electrical Characteristics Symbol Parameter Test Conditions Type Min Typ Max Units ------ ------ 0.54 -0.54 4.32 -4.32 1.5 A A A A V -- -- -5.0 V -- 90 -- ns -- 189 -- nC -- 77 -- ns -- 210 -- nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current ISM Maximum Pulsed Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.54 A N-Ch P-Ch N-Ch P-Ch N-Ch VGS = 0 V, IS = -0.54 A P-Ch trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 0.54 A, (Note 3) dIF / dt = 100 A/µs trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = -0.54 A, (Note 3) dIF / dt = 100 A/µs N-Ch P-Ch Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. ISD ≤ 0.54A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 3. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 4. Essentially independent of operating temperature 5. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RθCA is determined by the user’s board design Maximum RθJA using the different board layouts on 3”x4.5” FR-4 PCB in a still air environment : a. 90°C/W when mounted without any pad copper b. 62.5°C/W when mounted on a 4.5 in2 pad of 2oz copper. In such an environment, the power dissipation can be enhanced up to 2W ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4902 Electrical Characteristics (Continued) FQG4902 Typical Characteristics : N-Channel VGS 15.0 V 10.0 V 8.0 V 6.0 V 5.5 V 5.0 V 4.5 V Bottom : 4.0 V ID, Drain Current [A] 0 10 ID , Drain Current [A] Top : 0 10 150℃ 25℃ -55℃ ※ Notes : 1. 250μ s Pulse Test 2. TA = 25℃ -1 10 ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test -1 -1 0 10 10 1 10 10 0 2 4 VDS, Drain-Source Voltage [V] 6 8 10 VGS , Gate-Source Voltage [V] Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics 10 IDR, Reverse Drain Current [A] RDS(ON) [Ω ], Drain-Source On-Resistance 8 VGS = 10V 6 VGS = 20V 4 2 0 10 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test ※ Note : TJ = 25℃ -1 0 0 2 4 6 8 10 10 0.2 0.4 0.6 ID, Drain Current [A] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 1.0 1.2 1.4 Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 12 400 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd VDS = 50V 300 Ciss Coss 200 Crss 100 ※ Notes : 1. VGS = 0 V 2. f = 1 MHz VGS, Gate-Source Voltage [V] 10 Capacitance [pF] 0.8 VSD, Source-Drain voltage [V] VDS = 125V VDS = 200V 8 6 4 2 ※ Note : ID = 0.54 A 0 -1 10 0 0 10 1 10 VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics ©2002 Fairchild Semiconductor Corporation 0 2 4 6 8 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A1, April 2002 FQG4902 Typical Characteristics : N-Channel (Continued) 2.5 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.0 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 150 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 0.27 A 0.5 0.0 -100 200 -50 0 50 100 o 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.6 Operation in This Area is Limited by R DS(on) 1 100 μ s 1 ms 10 ms 100 ms 1s 0 10 -1 10 ID, Drain Current [A] ID, Drain Current [A] 10 0.4 DC 0.2 ※ Notes : -2 10 o 1. TA = 25 C o 2. TJ = 150 C 3. Single Pulse -3 10 0 1 10 0.0 25 2 10 10 50 θJ A Z (t), T h e rm a l R e s p o n s e 100 125 150 Figure 10. Maximum Drain Current vs. Ambient Temperature Figure 9. Maximum Safe Operating Area 10 75 TA, Ambient Temperature [℃] VDS, Drain-Source Voltage [V] 2 D = 0 .5 0 .2 10 1 0 .1 PDM 0 .0 5 t1 0 .0 2 10 t2 0 .0 1 0 ※ N o te s : 1 . Z θ J A ( t) = 9 0 ℃ /W M a x . 2 . D u t y F a c to r , D = t 1 /t 2 3 . T J M - T A = P D M * Z θ J A ( t) s i n g le p u ls e 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4902 Typical Characteristics : P-Channel VGS -15.0 V -10.0 V -8.0 V -6.0 V -5.5 V -5.0 V Bottom : -4.5 V -ID, Drain Current [A] 0 10 -ID , Drain Current [A] Top : 150℃ 0 10 25℃ -55℃ ※ Notes : 1. 250μ s Pulse Test 2. TA = 25℃ -1 10 ※ Notes : 1. VDS = -40V 2. 250μ s Pulse Test -1 -1 0 10 10 1 10 10 0 2 4 6 8 10 -VGS , Gate-Source Voltage [V] -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 10 -I DR, Reverse Drain Current [A] RDS(ON) [Ω ], Drain-Source On-Resistance 8 VGS = -10V 0 10 6 VGS = -20V 4 2 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test ※ Note : TJ = 25℃ -1 10 0 0 2 4 6 8 10 12 0.0 0.5 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 800 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 2.0 2.5 3.0 12 VDS = -50V Ciss Coss 400 ※ Notes : 1. VGS = 0 V 2. f = 1 MHz Crss 200 -VGS, Gate-Source Voltage [V] Capacitance [pF] 1.5 Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature VDS = -125V 10 600 1.0 -VSD, Source-Drain voltage [V] -ID, Drain Current [A] VDS = -200V 8 6 4 2 ※ Note : ID = -0.54 A 0 -1 10 0 10 1 10 -VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics ©2002 Fairchild Semiconductor Corporation 0 0 3 6 9 12 15 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A1, April 2002 FQG4902 Typical Characteristics : P-Channel (Continued) 2.5 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance -BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.0 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = -250 μ A 0.9 0.8 -100 -50 0 50 100 150 1.5 1.0 ※ Notes : 1. VGS = -10 V 2. ID = -0.27 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.6 Operation in This Area is Limited by R DS(on) 1 100 μ s 1 ms 10 ms 100 ms 1s 0 10 -1 10 -ID, Drain Current [A] -ID, Drain Current [A] 10 0.4 DC 0.2 ※ Notes : -2 10 o 1. TA = 25 C o 2. TJ = 150 C 3. Single Pulse -3 10 0 1 10 0.0 25 2 10 10 50 -VDS, Drain-Source Voltage [V] θJ A Z (t), T h e rm a l R e s p o n s e Figure 9. Maximum Safe Operating Area 10 75 100 125 150 TA, Ambient Temperature [℃] Figure 10. Maximum Drain Current vs. Ambient Temperature 2 D = 0 .5 0 .2 10 1 0 .1 PDM 0 .0 5 t1 0 .0 2 10 t2 0 .0 1 0 ※ N o te s : 1 . Z θ J A ( t) = 9 0 ℃ /W M a x . 2 . D u t y F a c to r , D = t 1 /t 2 3 . T J M - T A = P D M * Z θ J A ( t) s i n g le p u ls e 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4902 Gate Charge Test Circuit & Waveform (N-Channel) 50KΩ 12V VGS Same Type as DUT Qg 200nF 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms (N-Channel) VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Gate Charge Test Circuit & Waveform (P-Channel) 50KΩ 12V VGS Same Type as DUT Qg 200nF -10V 300nF VDS VGS Qgs Qgd DUT -3mA Charge Resistive Switching Test Circuit & Waveforms (P-Channel) VDS RL VDD VGS RG -10V t on td(on) VGS td(off) tf 10% DUT VDS ©2002 Fairchild Semiconductor Corporation t off tr 90% Rev. A1, April 2002 FQG4902 Peak Diode Recovery dv/dt Test Circuit & Waveforms (N-Channel) DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4902 Peak Diode Recovery dv/dt Test Circuit & Waveforms (P-Channel) + VDS DUT _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Compliment of DUT (N-Channel) VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4902 Package Dimensions #4 #5 1.524 ±0.10 0.060 ±0.004 0.46 ±0.10 #8 2.54 0.100 9.60 MAX 0.378 #1 9.20 ±0.20 0.362 ±0.008 ( 6.40 ±0.20 0.252 ±0.008 0.018 ±0.004 0.79 ) 0.031 8-DIP 5.08 MAX 0.200 7.62 0.300 3.40 ±0.20 0.134 ±0.008 3.30 ±0.30 0.130 ±0.012 0.33 MIN 0.013 +0.10 0.25 –0.05 +0.004 0~15° 0.010 –0.002 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS™ EnSigna™ FACT™ FACT Quiet Series™ FAST® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ I2C™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER® SMART START™ SPM™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET® VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2002 Fairchild Semiconductor Corporation Rev. H5