SiHP12N50C, SiHB12N50C, SiHF12N50C Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Low Figure-of-Merit Ron x Qg 560 V RDS(on) (Ω) VGS = 10 V 0.555 Qg (Max.) (nC) 48 Qgs (nC) 12 Qgd (nC) • 100 % Avalanche Tested • Gate Charge Improved • Trr/Qrr Improved 15 Configuration Single TO-220AB TO-220 FULLPAK G D • Compliant to RoHS Directive 2002/95/EC D S D2PAK GD S (TO-263) G S G D N-Channel MOSFET S ORDERING INFORMATION Package TO-220AB D2PAK (TO-263) TO-220 FULLPAK Lead (Pb)-free SiHP12N50C-E3 SiHB12N50C-E3 SiHF12N50C-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) LIMIT TO220-AB SYMBOL D2PAK (TO-263) PARAMETER Drain-Source Voltage VDS 500 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C)a VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currentc Single Pulse Avalanche EAS PD Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)d TJ, Tstg for 10 s A 28 1.67 Maximum Power Dissipation V 7.5 IDM Energyb UNIT 12 ID Linear Derating Factor TO-220 FULLPAK 0.28 180 208 mJ 36 - 55 to + 150 300 W/°C W °C Notes a. Limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 Ω, IAS = 12 A. c. Repetitive rating; pulse width limited by maximum junction temperature. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91388 S10-0969-Rev. B, 26-Apr-10 www.vishay.com 1 SiHP12N50C, SiHB12N50C, SiHF12N50C Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TO220-AB D2PAK (TO-263) TO-220 FULLPAK Maximum Junction-to-Ambient RthJA 62 65 Maximum Junction-to-Case (Drain) RthJC 0.6 3.5 mount)a RthJA 40 - Junction-to-Ambient (PCB UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.6 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance IGSS IDSS RDS(on) gfs VGS = ± 30 V - - ± 100 VDS = 500 V, VGS = 0 V - - 50 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 VGS = 10 V - 0.46 0.555 Ω - 3 - S - 1375 - - 165 - - 17 - - 32 48 - 12 - ID = 4 A VDS = 50 V, ID = 3 A μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz VGS = 10 V ID = 10 A, VDS = 400 V pF nC Gate-Drain Charge Qgd - 15 - Turn-On Delay Time td(on) - 18 - - 35 - - 23 - - 6 - - 1.1 - - - 12 - - 28 - - 1.8 - 580 - ns - 4.3 - μC - 13 - A Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VDD = 250 V, ID = 10 A Rg = 4.3 Ω, VGS = 10 V f = 1 MHz, open drain ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Body Diode Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 10 A, VGS = 0 V TJ = 25 °C, IF = IS, dI/dt = 100 A/μs, VR = 20 V V Note • The information shown here is a preliminary product proposal, not a commercial product data sheet. Vishay Siliconix is not committed to produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products. www.vishay.com 2 Document Number: 91388 S10-0969-Rev. B, 26-Apr-10 SiHP12N50C, SiHB12N50C, SiHF12N50C Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) VGS TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V 25 20 15 35 TJ = 25 °C ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 30 10 5 7.0 V 0 25 20 TJ = 150 °C 15 10 5 0 0 5 10 15 20 25 0 30 5 10 15 20 25 VGS, Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics (TO-220) Fig. 3 - Typical Transfer Characteristics VGS TJ = 150 °C TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V 15 12 9 RDS(on), Drain-to-Source On-Resistance (Normalized) VDS, Drain-to-Source Voltage (V) 18 ID, Drain-to-Source Current (A) TJ = 25 °C 30 7.0 V 6 3 0 0 5 10 15 20 25 30 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics (TO-220) Document Number: 91388 S10-0969-Rev. B, 26-Apr-10 3 ID = 12 A 2.5 2 1.5 1 0.5 VGS = 10 V 0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 SiHP12N50C, SiHB12N50C, SiHF12N50C Vishay Siliconix 100 2400 C, Capacitance (pF) 2000 ISD, Reverse Drain Current (A) VGS = 0 V, f = 1MHz Ciss = Cgs +Cgd Cds SHORTED Crss = Cgd Coss = Cds + Cgd 1600 Ciss 1200 800 Coss 400 Crss TJ = 150 °C TJ = 25 °C 10 1 VGS = 0 V 0.1 0 1 10 100 0.2 1000 0.4 VDS, Drain-to-Source Voltage (V) ID, Drain-to-Source Current (A) VGS, Gate-to-Source Voltage (V) 1.2 1.4 1.6 OPERATION IN THIS AREA LIMITED BY RDS(on) 100 ID = 12 A 1 Fig. 7 - Typical Source-Drain Diode Forward Voltage VDS = 400 V VDS = 250 V VDS = 100 V 20 0.8 VSD, Source-to-Drain Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 24 0.6 16 12 8 4 10 100 µs 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse 10 ms 0.1 0 0 10 20 30 40 50 10 60 100 VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area (TO-220AB, D2PAK) OPERATION IN THIS AREA LIMITED BY RDS(on) 100 ID, Drain-to-Source Current (A) 1000 10 100 µs 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse 10 ms 0.1 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig. 9 - Maximum Safe Operating Area (TO-220 FULLPAK) www.vishay.com 4 Document Number: 91388 S10-0969-Rev. B, 26-Apr-10 SiHP12N50C, SiHB12N50C, SiHF12N50C Vishay Siliconix VDS RD VDS 90 % VGS D.U.T. RG + - VDD 10 % VGS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % t d(on) tr t d(off) t f Fig. 10b - Switching Time Waveforms Fig. 10a - Switching Time Test Circuit 1 Thermal Response (ZthJC) 0.5 0.1 0.05 0.1 0.02 PDM Single Pulse (Thermal Response) t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 0.001 10-4 10-3 10-2 0.1 1 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case (TO-220AB, D2PAK) 1 Thermal Response (ZthJC) 0.5 0.2 0.1 PDM 0.1 0.05 t1 t2 0.02 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 0.001 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case (TO-220 FULLPAK) Document Number: 91388 S10-0969-Rev. B, 26-Apr-10 www.vishay.com 5 SiHP12N50C, SiHB12N50C, SiHF12N50C Vishay Siliconix 15 V QG VGS L VDS Driver QGS D.U.T. RG + A - VDD IAS 20 V tp 0.01 Ω Fig. 13a - Unclamped Inductive Test Circuit QGD VG A Charge Fig. 14a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. V DS 50 kΩ tp 12 V 0.2 µF 0.3 µF D.U.T. + V - DS VGS 3 mA I AS IG ID Current sampling resistors Fig. 13b - Unclamped Inductive Waveforms www.vishay.com 6 Fig. 14b - Gate Charge Test Circuit Document Number: 91388 S10-0969-Rev. B, 26-Apr-10 SiHP12N50C, SiHB12N50C, SiHF12N50C Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - • • • • RG dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Body diode VDD forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 15 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91388. Document Number: 91388 S10-0969-Rev. B, 26-Apr-10 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1