Revised August 2000 100351 Low Power Hex D-Type Flip-Flop General Description Features The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. ■ 40% power reduction of the 100151 ■ 2000V ESD protection ■ Pin/function compatible with 100151 ■ Voltage compensated operating range: −4.2V to −5.7V ■ Available to industrial grade temperature range Ordering Code: Order Number Package Number Package Description 100351SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100351PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100351QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100351QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Pin Descriptions Pin Names Description D0–D5 Data Inputs CPa, CPb Common Clock Inputs MR Asynchronous Master Reset Input Q0–Q5 Data Outputs Q0–Q5 Complementary Data Outputs © 2000 Fairchild Semiconductor Corporation DS009885 www.fairchildsemi.com 100351 Low Power Hex D-Type Flip-Flop July 1988 100351 Truth Tables (Each Flip-flop) Asynchronous Operation Synchronous Operation Inputs Dn L H L CPa L H L X X X H L Outputs Inputs MR Qn(t+1) Dn CPa CPb MR Qn(t+1) L L L X X X H L L H L L L L H L Qn(t) H L Qn(t) L L Qn(t) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care t = Time before CP positive transition t+1 = Time after CP positive transition = LOW-to-HIGH transition Logic Diagram www.fairchildsemi.com Outputs CPb 2 Recommended Operating Conditions −65°C to +150°C Storage Temperature (TSTG) +150°C Maximum Junction Temperature (TJ) Case Temperature (TC) −7.0V to +0.5V VEE Pin Potential to Ground Pin Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V 0°C to +85°C Commercial VEE to +0.5V Input Voltage (DC) 100351 Absolute Maximum Ratings(Note 1) −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max VOH Symbol Output HIGH Voltage −1025 −955 −870 VOL Output LOW Voltage −1830 −1705 −1620 VOHC Output HIGH Voltage −1035 VOLC Output LOW Voltage VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µA VIN = VIL (Min) IIH Input HIGH Current µA VIN = VIH (Max) mA Inputs OPEN IEE Parameter −1610 MR 350 D0–D5 240 CPa, CPb 350 Power Supply Current −129 −62 Units mV mV Conditions VIN =VIH (Max) Loading with or VIL (Min) 50Ω to −2.0V VIN = VIH (Min) Loading with or VIL (Max) 50Ω to −2.0V Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = 0°C Min fMAX Toggle Frequency tPLH Propagation Delay tPHL CPa, CPb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time TC = +25°C Max Min 375 Max 375 TC = +85°C Min Units Conditions Max 375 MHz Figures 2, 3 0.80 2.00 0.80 2.0 0.90 2.10 ns Figures 1, 3 1.10 2.30 1.10 2.30 1.20 2.40 ns Figures 1, 4 0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 3 ns Figure 5 D0–D5 0.40 0.40 0.40 MR (Release Time) 1.60 1.60 1.60 0.80 0.80 0.80 ns Figure 5 2.00 2.00 2.00 ns Figures 3, 4 tH Hold Time tPW(H) Pulse Width HIGH D0–D5 CPa, CPb, MR 3 Figure 4 www.fairchildsemi.com 100351 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = 0°C Min fMAX Toggle Frequency tPLH Propagation Delay tPHL CPa, CPb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH 375 Max 375 TC = +85°C Min Units Conditions Max 375 MHz Figures 2, 3 0.80 1.80 0.80 1.80 0.90 1.90 ns Figures 1, 3 1.10 2.10 1.10 2.10 1.20 2.20 ns Figures 1, 4 0.45 1.70 0.45 1.60 0.45 1.70 ns Figures 1, 3 ns Figure 5 D0–D5 0.30 0.30 0.30 1.50 1.50 1.50 0.80 0.80 0.80 ns Figure 5 2.00 2.00 2.00 ns Figures 3, 4 Hold Time Pulse Width HIGH CPa, CPb, MR tOSHL Min MR (Release Time) D0–D5 tPW(H) TC = +25°C Max Figure 4 Maximum Skew Common Edge Output-to-Output Variation PLCC only 220 220 220 ps 210 210 210 ps 240 240 240 ps 230 230 230 ps (Note 4) Clock to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC only (Note 4) Clock to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC only (Note 4) Clock to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC only (Note 4) Clock to Output Path Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 4 100351 Industrial Version PLCC DC Electrical Characteristics VEE=−4.2V to −5.7V, VCC=VCCA= GND, TC= 0°C to +85°C (Note 5) Symbol TC = −40°C Parameter Min TC = 0° to +85°C Max Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 VOL Output LOW Voltage −1830 −1575 −1830 −1620 −1095 −1035 Units mV Conditions VIN =VIH (Max) Loading with or VIL (Min) 50Ω to −2.0V VIN = VIH (Min) Loading with or VIL (Max) 50Ω to −2.0V VOHC Output HIGH Voltage VOLC Output LOW Voltage VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current −1565 −1610 mV for All Inputs for All Inputs IEE 0.50 MR 350 350 D0–D5 240 240 CPa, CPb 350 350 Power Supply Current −129 −62 −129 −62 µA VIN = VIL (Min) µA VIN = VIH (Max) mA Inputs OPEN Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter fMAX Toggle Frequency tPLH Propagation Delay tPHL CPa, CPb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH TC = +25°C Max Min 375 Max 375 TC = +85°C Min Max 375 Units Conditions MHz Figures 2, 3 0.80 1.80 0.80 1.80 0.90 1.90 ns Figures 1, 3 1.10 2.10 1.10 2.10 1.20 2.20 ns Figures 1, 4 0.45 1.70 0.45 1.60 0.45 1.70 ns Figures 1, 3 ns Figure 5 D0–D5 0.60 0.30 0.30 MR (Release Time) 2.20 1.50 1.50 0.60 0.90 0.90 ns Figure 5 2.00 2.00 2.00 ns Figures 3, 4 Hold Time D0–D5 tPW(H) TC = −40°C Min Pulse Width HIGH CPa, CPb, MR 5 Figure 4 www.fairchildsemi.com 100351 Test Circuitry Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Jig and stray capacitance ≤ 3 pF FIGURE 2. Toggle Frequency Test Circuit www.fairchildsemi.com 6 100351 Switching Waveforms FIGURE 3. Propagation Delay (Clock) and Transition Times FIGURE 4. Propagation Delay (Reset) Notes: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 5. Setup and Hold Time 7 www.fairchildsemi.com 100351 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 8 100351 Low Power Hex D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com