MC100EP40 3.3V / 5VECL Differential Phase−Frequency Detector The MC100EP40 is a three−state phase−frequency detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply. When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. When Reference (R) and Feedback (FB) inputs are 80 ps or less in phase difference, the Phase Lock Detect pin will indicate lock by a high state (VOH). The VTX (VTR, VTR, VTFB, VTFB) pins offer an internal termination network for 50 line impedance environment shown in Figure 2. An external sinking supply of VCC−2 V is required on VTX pin(s). If you short the two differential VTR and VTR (or VTFB and VTFB) together, you provide a 100 termination resistance that is compatible with LVDS signal receiver termination. For more information on termination of logic devices, see AND8020. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. For more information on Phase Lock Loop operation, refer to AND8040. Special considerations are required for differential inputs under No Signal conditions to prevent instability. • • • • • • • • • January, 2004 − Rev. 8 MARKING DIAGRAM 20 20 100 EP40 ALYW 1 TSSOP−20 DT SUFFIX CASE 948E A L Y W 1 = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device MC100EP40DT Package Shipping† TSSOP−20 75 Units/Rail MC100EP40DTR2 TSSOP−20 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Maximum Frequency > 2 GHz Typical Fully Differential Advanced High Band Output Swing of 400 mV Theoretical Gain = 1.11 Trise 97 ps Typical, Ffall 70 ps Typical The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V 50 Internal Termination Resistor Semiconductor Components Industries, LLC, 2004 http://onsemi.com 1 Publication Order Number: MC100EP40/D MC100EP40 VCC PLD 20 1 19 2 VCC D D U U VCC NC VEE 18 17 16 15 14 13 12 11 3 4 VEE VTFB VTFB FB 5 6 7 FB R R 9 8 PIN DESCRIPTION 10 VTR VTR VBB Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 20−Lead Pinout (Top View) PIN FUNCTION U, U ECL Up Differential Outputs D, D ECL Down Differential Outputs FB, FB ECL Feedback Differential Inputs R, R ECL Reference Differential Inputs PLD ECL Phase Lock Detect Function VTR ECL Internal Termination for R VTR ECL Internal Termination for R VTFB ECL Internal Termination for FB VTFB ECL Internal Termination for FB VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect VTR 50 U C A A R R U U A C S 50 U FF Reset A R VTR C Reset D B D VTFB Reset 50 (V) FB FB R B D FF S B 50 Reset B D D VTFB VBB Figure 2. Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 4 kV > 400 V > 2 kV Level 1 UL 94 V−0 @ 0.125 in 699 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 D D MC100EP40 MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 20 TSSOP 20 TSSOP 140 100 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 20 TSSOP 23 to 41 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C VI VCC VI VEE 2. Maximum Ratings are those values beyond which device damage may occur. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) −40°C Symbol Power Supply Current VOH Output HIGH Voltage (Note 4) VOL Output LOW Voltage (Note 4) 85°C Min Typ Max Min Typ Max Min Typ Max Unit 100 128 160 100 130 160 110 140 170 mA U, U, B, B 2225 2350 2475 2275 2400 2525 2300 2425 2550 mV 1775 1355 1900 1480 2025 1605 1800 1355 1925 1480 2050 1605 1825 1355 1950 1480 2075 1605 mV PLD Characteristic IEE 25°C VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1875 2.0 150 −150 1875 150 −150 −150 1875 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 4. All loading with 50 to VCC−2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC100EP40 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current (Note 7) 100 128 160 100 130 160 110 140 170 mA VOH Output HIGH Voltage (Note 8) 3925 4050 4175 3975 4100 4225 4000 4125 4250 mV VOL Output LOW Voltage (Note 8) 3475 3055 3600 3180 3725 3305 3500 3055 3625 3180 3750 3305 3525 3055 3650 3180 3775 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV VBB Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 9) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current U, U, B, B PLD 3575 2.0 3575 150 −150 3575 150 −150 A −150 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 7. For (VCC − VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC−VEE operation at 3.3 V. 8. All loading with 50 to VCC−2.0 volts. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 10) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current (Note 11) 100 128 160 100 130 160 110 140 170 mA VOH Output HIGH Voltage (Note 12) −1075 −950 −825 −1025 −900 −775 −1000 −875 −750 mV VOL Output LOW Voltage (Note 12) U, U, B, B PLD −1525 −1945 −1400 −1820 −1275 −1695 −1500 −1945 −1375 −1820 −1250 −1945 −1475 −1945 −1350 −1820 −1225 −1945 VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VBB Output Voltage Reference −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 13) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current Symbol Characteristic mV −1425 VEE+2.0 0.0 VEE+2.0 150 −150 −1425 0.0 VEE+2.0 150 −150 −1425 −150 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. Input and output parameters vary 1:1 with VCC. 11. For (VCC − VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC−VEE operation at 3.3 V. 12. All loading with 50 to VCC−2.0 volts. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC100EP40 AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 14) −40°C Symbol Min Characteristic fmax Maximum Frequency (See Figure 3. Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential tJITTER Random Clock Jitter (See Figure 3. Fmax/JITTER) VPP Input Voltage Swing (Differential) tr tf Output Rise/Fall Times (20% − 80%) 25°C Typ Max Min >2 FB to D/U R to D/U Q, Q 400 85°C Typ Max Min >2 525 700 0.2 <1 150 800 1200 60 85 130 410 550 750 0.2 <1 150 800 1200 60 110 150 450 ps 0.2 <1 ps 150 800 1200 mV 80 120 160 ps 5V 7 450 6 3.3 V 5 ÏÏ ÏÏ ÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 4 300 JITTEROUT ps (RMS) VOUTamplitude (mVpp) 8 3 2 1 (JITTER) 0 250 1.0 1.5 2.0 FREQUENCY (GHz) 2.5 Figure 3. Fmax/Jitter @ 25C Q D Receiver Device Driver Device Q D 50 50 V TT V TT = V CC − 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) http://onsemi.com 5 GHz 775 9 500 Unit 575 10 550 350 Max >2 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC−2.0 V. 400 Typ MC100EP40 Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels AN1405 − ECL Clock Distribution Techniques AN1406 − Designing with PECL (ECL at +5.0 V) AN1504 − Metastability and the ECLinPS Family AN1568 − Interfacing Between LVDS and ECL AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8009 − ECLinPS Plus Spice I/O Model Kit AND8020 − Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 6 MC100EP40 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E−02 ISSUE A 20X 0.15 (0.006) T U 2X S L/2 K REF 0.10 (0.004) 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 B L J J1 −U− PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC100EP40 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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