MB86961A UNIVERSAL INTERFACE FOR 10BASE -T DECEMBER 1999 DATASHEET FEATURES polarity reversal on the twisted-pair input. • Full-duplex capability • Combines Manchester encoder/decoder and twisted pair transceiver functions • Direct interface to all popular Ethernet controllers • Direct interface to AUI and 10BASE-T outputs • Manual or automatic AUI /10BASE-T selection • Integrated pulse shaper and Tx/Rx filters • Selectable 100 Ω/150 Ω termination permits operation with shielded or unshielded twisted pair cable • Reverse-polarity detection for receiver with automatic correction Pulse shaping and filtering functions are performed by the MB86961A to eliminate the need for external filtering components and thus reduce overall system cost. The device also provides outputs for receive, transmit, collision and link test LEDs and provides compatibility with both shielded and unshielded twisted pair cables. The receive threshold can be reduced to allow an extended range between nodes in low noise environments. Its wide range of features and its ability to interface to virtually all popular controllers make the MB86961A the ideal device for twisted pair Ethernet applications. • On-chip jabber logic, SQE test and link test with enable/disable option • Remote signaling of link down and jabber conditions • Programmable receive threshold for extended range • Output drivers for receive, transmit, collision and link test pass LED indicators • TP loopback enable/disable for external loopback testing • Power down mode for minimum power dissipation • Automatic shut-down of unused port to reduce power consumption • Low power CMOS technology, single 5 volt power supply MD1 MD0 NTH CIN CIP VCC1 DON DOP DIN DIP PAUI PIN CONFIGURATION 6 5 RLD LI JAB TEST TCLK TXD TEN CLKO CLKI COL AUTOSEL 44-pin PLCC and 48-pin PQFP packages 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 11 36 35 12 13 TOP VIEW 34 33 14 15 32 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 LEDR LEDT/PDN LEDL LEDC/XLBK LBK GND1 RBIAS RCMPT RXD CD RCLK • The MB86961A is part of a complete family of Ethernet devices available from Fujitsu. It is fabricated in a lowpower CMOS technology and is supplied in a 44-pin PLCC and 48-pin PQFP packages. GENERAL DESCRIPTION The MB86961A Universal Interface for 10BASE-T (Twisted-Pair) Ethernet is fully compliant with the IEEE 802.3 specifications for AUI (Attachment Unit Interface) and 10BASE-T (Twisted-Pair) interfaces and provides the electrical interface between an Ethernet controller and the DB15 (AUI) and RJ45 (10BASE-T) connections to an Ethernet local area network. Functions provided by the MB86961A include Manchester encoding and decoding of the serial data stream, level conversion, collision detection, signal quality error (SQE) and link integrity testing, jabber control, loopback, and automatic correction of (PLCC Package Shown) 1 TPIN TPIP UTP TPONB TPONA VCC2 GND2 TPOPA TPOPB PLR RJAB MB86961A PIN ASSIGNMENT - 44-PIN PLCC PIN 1 2 3 4 5 6 7 8 9 10 11 PIN VCC1 CIP CIN NTH MD0 MD1 RLD LI JAB TEST TCLK — I I I I I O I O I O 12 13 14 15 16 17 18 19 20 21 22 PIN TXD TEN CLKO CLKI COL AUTOSEL LEDR LEDT/PDN LEDL LEDC/XLBK LBK 23 24 25 26 27 28 29 30 31 32 33 I I O I O I O O/I O/I O/I I PIN GND1 RBIAS RCMPT RXD CD RCLK RJAB PLR TPOPB TPOPA GND2 — I O O O O O O O O — 34 35 36 37 38 39 40 41 42 43 44 VCC2 TPONA TPONB UTP TPIP TPIN PAUI DIP DIN DOP DON — O O I I I I I I O O RJAB PLR TPOPB TPOPA GND VCC VCC TPONA TPONB UTP TPIP TPIN O O O O — — — O O I I I PIN ASSIGNMENT - 48-PIN PQFP PIN 1 2 3 4 5 6 7 8 9 10 11 12 PIN PAUI DIP DIN DOP DON NC VCC CIP CIN NTH MD0 MD1 I I I O O — — I I I I I 13 14 15 16 17 18 19 20 21 22 23 24 PIN RLD LI JAB TEST TCLK TXD VCC TEN CLKO CLKI COL AUTOSEL 25 26 27 28 29 30 31 32 33 34 35 36 O I O I O I — I O I O I PIN LEDR LEDT/PDN LEDL LEDC/XLBK LBK GND NC RBIAS RCMPT RXD CD RCLK O O/I O/I O/I I — — I O O O O 37 38 39 40 41 42 43 44 45 46 47 48 ORDERING CODE PACKAGE STYLE PACKAGE CODE VCC = +V + 5% 44-Pin Plastic Leaded Chip Carrier 48-Pin Plastic Quad Flat Package LCC-44P-M02 FPT-48P-M02 MB86961APD-G MB86961APF-G 2 MB86961A BLOCK DIAGRAM PAUI LI MD0 Mode Select Logic Controller Compatibility/ Port Select/ Polarity Reverse/ Loopback/Link Test LBK MD1 UTP PLS Only PLS/MAU Select Twisted Pair Interface TCLK CLK1 CLK0 XTAL OSC Manchester Encoder TEN TXD TPOPB CMOS TX AMP Pulse Shaper & Filter WatchDog Timer DO TPONA TPONB Collision/ Polarity/ Detect/ Correct RLD RJAB TPOPA RX Slicer TPIP TPIN Remote Signaling RCMPT CD Drop Cable Interface Squelch/ Link Detect LEDL RXD RCLK EXL TX AMP DI Manchester Decoder RX Slicer COL NTH JAB PLR 3 DIP DIN CI Collision Receiver LEDC/XLBK DON LPBK Collision Logic LEDT/PDN LEDR DOP CIP CIN MB86961A SIGNAL DESCRIPTIONS Symbol Type Description AUTOSEL I AUTOMATIC PORT SELECT: When AUTOSEL=1, automatic port selection is enabled (The MB86981A defaults to the AUI port only if TP link integrity=Fail). When AUTOSEL=0, manual port selection is enabled (the PAUI pin determines the active port). CD O CARRIER DETECT: An output to notify the controller of activity on the network. CIP CIN I I AUI COLLISION PAIR: Differential input pair connected to the AUI transceiver CI circuit. The input is collision signaling or SQE. CLKO CLKI O I CRYSTAL OSCILLATOR: A 20MHz crystal must be connected across these pins, or a 20 MHz clock applied at CLKI. COL O COLLISION DETECT: Output which drives the collision detect input of the controller. DIP DIN I I AUI RECEIVE PAIR: Differential input pair from the AUI transceiver DI circuit. The input is Manchester encoded. DOP DON O O AUI TRANSMIT PAIR: A differential output driver pair for the AUI transceiver cable. The output is Manchester encoded. JAB O JABBER INDICATION: Output goes high to indicate Jabber state. LBK I LOOPBACK: When LBK=1, forced loopback is enabled. When LBK=0, normal loopback is enabled. LEDC/XLBK O/I COLLISION LED: Open drain driver for the collision indicator. Output is pulled low during collision ( half-duplex mode). If externally tied low, the MB86961A disables the internal TP loopback and collision detection circuits in anticipation of external TP loopback or full-duplex operation. MB86961A is ready for loopback testing 16 ms after this pin goes low. No delay is needed when the pin goes high. LEDL O/I LINK LED: Open drain driver for link integrity indicator. Output pulled low during link test pass. If externally tied low, internal circuitry is forced to “Link Pass’ state and the MB86961A will continue to transmit link test pulses. LEDR O RECEIVE LED: Open drain driver for the receive indicator LED. Output is pulled low during receive. LEDT/ PDN O/I TRANSMIT LED/POWER DOWN: Open drain driver for the transmit indicator. Output is pulled low during transmit. If externally tied low, the MB86961A goes to power down state. LI I LINK TEST ENABLE: When LI=0, the Link Integrity Test function is disabled. When LI=1, the Link Integrity Test function is enabled. MD0 MD1 I I MODE SELECT: Mode select pins which determine controller compatibility mode. See Table 1. NTH I NORMAL THRESHOLD: When NTH=1, the normal TP squelch threshold is in effect. When NTH=0, the normal TP squelch threshold is reduced by 4.5 dB. PAUI I PORT/AUI SELECT: In Manual Port Select mode (AUTOSEL=0), PAUI selects the active port. When PAUI=1, the AUI port is selected, When PAUI=0, the TP port is selected. In Auto Port Select mode, PAUI is ignored. PLR O POLARITY REVERSE: Output goes high to indicate reversed polarity. RBIAS I BIAS CONTROL: A bias resistor at this pin controls the bias of the operating circuit. RCLK O RECEIVE CLOCK: A recovered 10 MHz clock which is synchronous with the received data and connected to the controller receive clock input. 4 MB86961A SIGNAL DESCRIPTIONS (Continued) Symbol Type Description RCMPT O REMOTE COMPATIBILITY: Output goes high to signal the controller that the remote port is compatible with the MB86961A remote signaling features. RJAB O REMOTE JABBER: Output goes high to signal the controller that the remote port is in Jabber condition. RLD O REMOTE LINK DOWN: Output goes high to signal to the controller that the remote port is in link down condition. RXD O RECEIVE DATA: Output signal connected directly to the receive data input of the controller. TCLK O TRANSMIT CLOCK: A 10 MHz clock output. This clock signal is directly connected to the transmit clock input of the controller. TEN I TRANSMIT ENABLE: Enables data transmission and starts the watchdog timer. Synchronous with TCLK (see Figures 14, 20, 26, and 32 for details). TEST I TEST: Input for factory test of the device. Leave open for normal operation. TPIP TPIN O O RECEIVE TWISTED-PAIR: A differential input pair from the twisted-pair cable. Receive filter is integrated in-chip. No external filters are required. TPOPA/B TPONA/B O O TRANSMIT TWISTED PAIR: Two differential driver pair outputs (A and B) to the twisted-pair cable. The output is pre-equalized, no external filter is required. Two pairs are used to provide compatibility with both 100 Ω load cable and 150 Ω load cable. TXD I TRANSMIT DATA: Input signal containing NRZ data to be transmitted on the network. TXD is connected directly to the transmit data output of the controller. UTP I UTP/STP: When UTP=0, 150 Ω termination for shielded TP is selected. When UTP=1,100 Ω termination for unshielded TP is selected. VCC1, VCC2 — POWER INPUTS: +5V power supply inputs. GND1 GND2 — — GROUND RETURNS 1 & 2: Grounds 5 MB86961A APPLICATIONS external port selection through the PAUI pin. The remote status output are inverted and used to drive LED indicators. (See Figure 3.) Figure 1 shows the MB86961A in a typical application, interfacing between a controller and the RJ45 connector of the twisted-pair network. Figures 2 through 5 show detailed diagrams of various MB86961A applications. TWISTED-PAIR ONLY Figure 4 shows the MB86961A is a typical twisted-pair only application. The DTE is connected to a 10BASE-T network through the twisted-pair RJ45 connector. (The AUI port is not used.) With MD0 tied high and MD1 grounded, the MB86961A logic and framing are set to Mode 2 (compatible with Intel 82586 controllers). The LI pin externally controls the link test function. The UTP and NTH pins are both tied low, selecting the reduced receiver threshold and 150 Ω termination for shielded TP cable. The switch at LEDT/PDN manually controls the power down mode. (See Figure 4.) AUTO PORT SELECT LOOPBACK CONTROL PIN With MD0 and MD1 both tied high, the MB86961A logic and framing are set to Mode 4 (compatible with National NS8390 controllers). The AUTOSEL pin is tied high, allowing the MB86961A to automatically select the active port. The high at LI enables Link Testing. The UTP and NTH pins are both tied high selecting the standard receiver threshold and 100 Ω termination for unshielded TP cable. (See Figure 2.) AUI ENCODER/DECODER ONLY In this application, the DTE is connected to the coaxial network through the AUI. AUTOSEL and PAUI are both tied to ground, manually selecting the AUI port. The twisted-pair port is not used. With MD1 and MD0 both grounded, the MB86961A logic and framing are set to Mode 1 (compatible with AMD AM7990 controllers). The LI pin is tied low, disabling the link test function. The LBK input controls loopback. A 20 MHz crystal connected across CLKI and CLK0 provides the required clock signal. (See Figure 5.) MANUAL PORT SELECT LINK TEST FUNCTION With MD0 low and MD1 tied high, the MB86961A logic and framing are set to Mode 3 (compatible with Fujitsu’s MB86960 controller). As in Figure 3, the LI pin is tied high, enabling Link Testing, and the UTP and NTH pins are both tied high, selecting the standard receiver threshold and 100 Ω termination for unshielded TP cable. However, in this application AUTOSEL is tied low, allowing 10BASE-T MB86961A MB86960 10BASE-T Inter- Ethernet AUI H O S B U Figure 1. Typical System Diagram 6 MB86961A 20 MHz 20 pF 20 pF 1 CLK1 TXD TXE TXC RXC RXD CPS COL NS8390 Back-End Controller Interface Loopback Enable CLK0 TPOPB TPOPA TXD TEN TCLK RCLK RXD CD COL LBK TPONA TPONB +5 V TPIP 18pF 2 37.5Ω ±1% 3 75Ω ±1% 50Ω ±1% 4 1:1 5 50Ω ±1% 2 1 78Ω 330Ω 330Ω 330Ω 330Ω Line Status + 1 µF TANT 1 2 3 0.1 µF +12 V 9 CIN 2 10 Fuse 3 CIP 11 78Ω 4 DON 12 DOP 13 5 RCMPT JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2 To 10Base-T Twisted-Pair Network 6 RIAB RLD 1 37.5Ω ±1% TPIN MB86961A Remote Status RJ45 1: 2 0.1µF PAUI AUTOSEL MD0 MD1 NTH UTP LI Programming Options 75Ω ±1% DIN 6 14 78Ω 7 15 D-Connector to AUI Drop Cable 8 DIP 3 12.4 KΩ ±1% RBIAS GND1 GND2 Suitable crystals includes: MTRON Industries, Inc. MP-1 and MP-2, and Ecliptek ECSM20.000M Suitable TP transformers include: Fil-Mag 23Z128 and SM23Z128, Valor PT4069, and Pulse Engineering PE-65745, PE-65454 and PE-68048 Suitable AUI transformers include: Fil-Mag 23Z90 and SM23Z90, and Valor LT6030 Figure 2. LAN Adapter Board Application - Auto Port Select with External Loopback Control 7 MB86961A 20 MHz 20 pF 20 pF 1 CLK1 TXD TEN TCKN RCKN RXD XCD -XCOL MB6950 or MB86960 Back-End Controller Interface LBC CLK0 TPOPB TPOPA TXD TEN TCLK RCLK RXD CD COL LBK TPONA TPONB 75Ω ±1% RJ45 1: 2 1 37.5Ω ±1% 18pF 2 37.5Ω ±1% 3 75Ω ±1% 50Ω ±1% To 10Base-T Twisted-Pair Network 4 1:1 TPIP Loopback Enable +5 V 330Ω 330Ω 330Ω Programming Options 0.1µF PAUI AUTOSEL MD0 MD1 NTH UTP LI 5 6 TPIN 50Ω ±1% 2 1 78Ω 2 MB86961A 10 11 RIAB 330Ω 330Ω 330Ω 330Ω 78Ω 4 DON 12 DOP 13 5 RCMPT Remote Status JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2 Line Status + 1 µF TANT 1 2 3 0.1 µF Fuse 3 CIP RLD +12 V 9 CIN DIN 6 14 78Ω 7 15 D-Connector to AUI Drop Cable 8 DIP 3 12.4 KΩ ±1% RBIAS GND1 GND2 Suitable crystals include: MTRON Industries, Inc. MP-1 and MP-2, and Ecliptek Corp. ECSM20.000M Suitable TP transformers include: Fil-Mag 23Z128 and SM23Z128, Valor PT4069, and Pulse Engineering PE-65745, PE-65454 and PE-68048 Suitable AUI transformers include: Fil-Mag 23Z90 and SM23Z90, and Valor LT6030 Figure 3. LAN Adapter Board Application - Manual Port Select with Link Test Function 8 MB86961A 20 MHz 20 pF 20 pF 1 CLK1 82586 Back-End Controller Interface LBK CLK0 TPOPB TPOPA TXD TEN TCLK RCLK RXD CD COL LBK TXD -RTD TXC RXC RXD -CRD -CDT TPONA TPONB TPIP Programming Options Loopback Enable RJ45 1: 2 1 37.5Ω ±1% 18pF 2 37.5Ω ±1% 3 75Ω ±1% 75Ω ±1% 1:1 0.1µF PAUI AUTOSEL MD0 MD1 NTH UTP LI +5 V 75Ω ±1% To 10Base-T Twisted-Pair Network 4 5 6 TPIN 75 Ω ±1% 2 CIN MB86961A CIP RIAB Remote Status RLD DON RCMPT JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2 Power Down 10kΩ 10kΩ 10kΩ Line Status Ext. _BK + 1 µF TANT 1 2 0.1 µF DOP DIN DIP 12.4 KΩ ±1% RBIAS GND1 GND2 Suitable crystals include: MTRON Industries Inc. MP-1 and MP-2, and Ecliptek Corp. ECSM20.000M Suitable TP transformers include: Fil-Mag 23Z128 and SM23Z128, Valor PT4069, and Pulse Engineering PE-65745, PE-65454 and PE-68048 Figure 4. Twisted-Pair Only Application 9 MB86961A 20 MHz 20 pF 20 pF 1 CLK1 NS8390 Back-End Controller Interface Loopback Enable CLK0 TPOPB TPOPA TXD TEN TCLK RCLK RXD CD COL LBK TX TENA TCLK RCLK RX RENA CLSN TPONA TPONB TPIP PAUI AUTOSEL MD0 MD1 NTH UTP LI +5 V Programming Options TPIN 1 78Ω CIN 2 MB86961A 10 11 RJAB RLD 78Ω 4 DON 12 DOP 13 5 330Ω 330Ω 330Ω 330Ω RCMPT JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2 Line Status + 1 µF TANT 0.1 µF Fuse 3 CIP Remote Status +12 V 9 DIN 6 14 78Ω 7 15 D-Connector to AUI Drop Cable 8 DIP 2 12.4 KΩ ±1% RBIAS GND1 GND2 1 Suitable crystals include: MTRON Industries Inc. MP-1 and MP-2, and Ecliptek Corp. ECSM20.000M 2 Suitable AUI transformers include: Fil-Mag 23Z90 and SM23Z90, and Valor LT6030 Figure 5. AUI Encoder/Decoder Only Application 10 MB86961A FUNCTIONAL DESCRIPTION CONTROLLER COMPATIBILITY MODES The MB86961A Universal Ethernet Interface Transceiver performs the physical layer signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It functions as a PLS-only device (for use with 10BASE2 or 10BASE5 coaxial cable networks) or as an Integrated PLS/MAU (for use with 10BASE-T twisted-pair networks). The MB86961A is compatible with most industry standard controllers including devices produced by Advanced Micro Devices (AMD), Intel, Fujitsu and National Semiconductor. Four different control signal timing and polarity schemes (Modes 1 through 4) are required to achieve this compatibility. Mode select pins MD0 and MD1 determine controller compatibility modes as listed in Table 1. The MB86961A interfaces a back-end controller to either an AUI drop cable or twisted-pair (TP) cable. The controller interface includes transmit and receive clock and NRZ data channels, as well as mode control logic and signaling. The AUI interface comprises three circuits: Data output (DO), Data Input (DI) and Collision (CI). The twisted-pair interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces, the MB86961A contains an internal crystal oscillator and four LED drivers for visual status reporting. Table 1. Functions are defined from the back end controller side of the interface. The MB86961A Transmit function refers to data transmitted by the back end to the AUI cable (PLSOnly mode) or to the twisted-pair network (Integrated PLS/MAU mode). The MB86961A Receive function refers to data received by the back end from the AUI cable (PLS-Only) or from the twisted-pair network (Integrated PLS/MAU mode). In the integrated PLS/MAU mode, the MB86961A performs all required MAU functions defined by the IEEE 802.3 10BASE-T specification such as collision detection, link integrity testing, signal quality error messaging, jabber control and loopback. In the PLS-Only mode, the MB86961A receives incoming signals from the AUI DI circuit with up to 18ns of jitter and drives the AUI DO circuit. MB86961A Compatibility Modes MD1 MD0 0 0 Mode 1: Compatible with Advanced Micro Devices AM7990 controllers Mode 0 1 Mode 2: Compatible with Intel 82586 controllers 1 0 Mode 3: Compatible with Fujitsu’s MB86960 controller 1 1 Mode 4: Compatible with National Semiconductor 8390 controllers • Mode 1: Figures 12-17 • Mode 2: Figures 18-23 • Mode 3: Figures 24-29 • Mode 4: Figures 30-35 The related timing specifications are provided in the electrical characteristics section of this data sheet. 11 MB86961A TRANSMIT FUNCTION decoder and output as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively. No external filters are required. The MB86961A receives NRZ data from the controller at the TXD input (see MB86961A block diagram), and passes it through a Manchester encoder. The encoded data is then transferred to either the AUI cable (the DO circuit) or the twisted-pair network (the TPO circuit). The advanced integrated pulse shaping and filtering network produces the output signal on TPON and TPOP, shown in Figure 6. The TPO output is pre-distorted and prefiltered to meet the 10BASE-T jitter template. No external filters are required. During idle periods, the MB86961A transmits link integrity test pulses on the TPO circuit if LI is enabled and integrated PLS/MAU mode is selected. The MB86961A can be programmed for either shielded TP (150 Ω) or unshielded TP (100 Ω) through the UTP pin. An internal intelligent squelch function discriminates noise from link test pulses and valid data streams. The receive function is activated only by valid data streams above the squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the MB86961A receive function enters the idle state. If the polarity of the TPI circuit is reversed, the MB86961A detects the polarity reversal and reports it via the PLR output. The MB86961A automatically corrects reversed polarity. POLARITY REVERSE FUNCTION JABBER CONTROL FUNCTION The MB86961A polarity reverse function uses both link pulses and end-of-frame data to determine the polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle. Whenever polarity is reversed, these two counters are reset to zero. If the MB86961A enters the link fail state and no valid Figure 7 is a state diagram of the MB86961A Jabber control function. The MB86961A on-chip watchdog timer prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and activates the JAB pin. Once the MB86961A is in the jabber state, the TXD circuit must remain idle for a period of 0.25 to 0.75 seconds before it will exit the jabber state. Power On SQE FUNCTION NO OUTPUT In the integrated PLS/MAU mode, the MB86961A supports the signal quality error (SQE) function as shown in Figure 8. After every successful transmission on the 10BASE-T network, the MB86961A transmits the SQE signal to the DTE for 10 ±5 bit times over the internal CI Circuit. (DO = Active) NONJABBER OUTPUT Start_XMIT_Max_Timer (DO = Active)• (XMIT_Max_Timer_Done) (DO = Idle) RECEIVE FUNCTION The MB86961A receive function acquires timing and data from the twisted-pair network (the TPI circuit) or from the AUI (the DI Circuit). Valid received signals are passed through the on-chip filters and Manchester JAB XMIT = Disable LPBK = Disable CI = SQE (DO = Idle) UNJAB WAIT Start_Unjab_Timer XMIT = Disable LPBK = Disable CI = SQE (Unjab_Timer_Done) Figure 6. MB86961A TPO Output Waveform (DO = Active) (Unjab_Timer_Not_Done) Figure 7. Jabber Control Function 12 MB86961A simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The MB86961A reports collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 9 is a state diagram of the MB86961A collision detection function. Refer to Electrical Characteristics for collision detection and COL/CI output timing. data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled, polarity detection is based only on received data. Polarity correction is always enabled. COLLISION DETECTION FUNCTION The collision detection function operates on the twistedpair side of the interface. A collision is defined as the LOOPBACK FUNCTION Power On The MB86961A provides the normal loopback function specified by the 10BASE-T standard for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the MB86961A from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. The “normal” loopback function is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Normal loopback is also disabled during link fail and jabber states. OUTPUT IDLE (DO = Active) OUTPUT DETECTED (DO = Idle) The MB86961A also provides additional loopback functions. An external loopback mode, useful for system-level testing, is controlled by pin 21 (LEDC). When LEDC is tied low, the MB86961A disables the collision detection and internal loopback circuits to allow external loopback or full-duplex operation. The MB86961A provides loopback functions controlled by pin 22 (LBK). When the TP port is selected and LBK=1, TP loopback is “forced,” overriding collisions on the TP circuit. When LBK=0, normal loopback is in effect. SQE WAIT TEST Start_SQE_Test_Wait_Timer (SQE_Test_Wait_Timer_Done)• (XMIT = Enable) (XMIT = Disable) SQE TEST Start_XMIT_Max_Timer CI = SQE (SQE_Test_Timer_Done) Figure 8. SQE Function A (DO= Active)• (TPI = Idle)• (XMIT = Enabled) Power On IDLE (TPI = Active) OUTPUT INPUT TPO = DO DI = DO DI = TPI (DO= Active)• (TPI = Active)• (XMIT = Enabled) A (DO= Idle) + (XMIT = Disabled) (DO= Active)• (TPI = Active)• (XMIT = Enabled) COLLISION A TPO = DO DI = TPI CI = SQE (TPI = Idle) (DO= Active)• (TPI = Idle) (DO= Idle) Figure 9. Collision Detection Function 13 MB86961A high. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50-150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. The MB86961A ignores any link integrity pulse with an interval less than 2-7 ms. The MB86961A will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses. When the AUI port is selected and LBK=1, data transmitted by the back-end controller is internally looped back from the TXD pin through the Manchester encoder/decoder to the RXD pin. When LBK=0, no AUI loopback occurs. LINK INTEGRITY TEST Figure 10 is a state diagram of the MB86961A Link Integrity test function. The link integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when pin 8 (LI) is tied Power On IDLE TEST Start_Link_Loss_Timer Start_Link_Test_Min_Timer (TPI = Active) ((Link_Test_Rcvd = True) • (Link_Test_Min_Timer_Done)) (Link_Loss_Timer_Done) • (TPI = Idle) (Link_Test_Rcvd = False) LINK TEST FAIL RESET LINK TEST FAIL WAIT Link_Count = 0 XMIT = Disable RCVR = Disable LPBK= Disable XMIT = Disable RCVR = Disable LPBK= Disable Link_Count = LInk Count + 1 (TPI = Active) (Link_Test_Rcvd = False) • (TPI = Idle) (Link_Test_Rcvd = Idle) • (TPI = Idle) LINK TEST FAIL Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT = Disable RCVR = Disable LPBK = Disable (TPi = Active) + (Link_Count = LC_Max) (Link_Test_Min_Timer_Done)• (Link_Test_Rcvd = True) LINK TEST FAIL EXTENDED (TPI = Idle • Link_Test_Max_Timer_Done) + ((Link_Test_Min_Timer_Done) • (Link_Test_Rcvd = True)) Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT = Disable (TPI = Idle) • (DO = Idle) Figure 10. Link Integrity Test Function 14 MB86961A REMOTE SIGNALING tions: link down, jabber, and remote signaling capability. Figure 11 shows the interval variations used to signal local status to the other end of the line. The MB86961A also recognizes these alternate pulse intervals when received from a remote unit. Remote status conditions are reported to the controller over the RLD, RJAB and RCMPT output pins. The MB86961A transmits standard link pulses which meet the 10BASE-T specification. However, the MB86961A encodes additional status information into the link pulse by varying the link pulse timing. This is referred to as remote signaling. Using alternate pulse intervals, the MB86961A can signal three local condi- 10ms 15ms 20ms 10ms 15ms 20ms 10ms 15ms 20ms LI-RLD1 20ms 15ms 10ms 20ms 15ms 10ms 20ms 15ms 10ms LI-RJAB2 10ms 20ms 10ms 20ms 10ms 20ms 10ms 20ms LI-RCMPT3 Notes: 1. For Remote Link Down (RLD) signaling, the interval between LI pulses increments from 10 ms to 15 ms to 20 ms, and then the cycle starts over. 2. For Remote Jabber (RJAB) signaling, the interval between LI pulses decrements from 20 ms to 15 ms to 10 ms, and then the cycle starts over. 3. For Remote Compatibility (RCMPT) signaling, the interval between LI pulses continually switches between 10 ms and 20 ms. Figure 11. Remote Signaling Link Integrity Pulse Timing 15 MB86961A ELECTRICAL CHARACTERISTICS Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Rating VCC Supply voltage TOP Operating temperature TST Storage temperature Note: Conditions Min. Max. Units -0.3 6 V 0 70 °C -65 150 °C Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 3. INPUT/OUTPUT CHARACTERISTICS (TA = 0°C to +70°C, VCC = 5 V ±5%) Symbol VIL Parameter Input low Condition Min. Typ.1 Max. Units — — 0.8 V 2.0 — — V — — 0.4 V IOL < 10 mA — — 10 %VCC IOH = 40 mA 2.4 — — V IOH < 10 mA 90 — — %VCC Normal mode — 90 — mA voltage1 VIH Input high voltage VOL Output low voltage VOH Output high voltage ICC Supply current tR Output rise time tF Output fall time 2 IOL =3.2 mA Power-down mode — 5 — mA CMOS TCLK and RCLK — 3 — ns TTL TCLK and RCLK — 2 — ns CMOS TCLK and RCLK — 3 — ns TTL TCLK and RCLK — 2 — ns Notes: 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional test patterns are performed at these input levels. The majority of functional tests are performed at levels 0V and 3 V. Table 4. AUI ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C, VCC = 5 V ±5%) Symbol Parameter Condition Min. Typ.1 Max. Units IIL Input low current — — -700 µA IIH Input high current — — 500 µA VOD Differential output voltage ±550 — ±1200 mV VDS Differential squelch threshold — 220 — mV Note: Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 16 MB86961A Table 5. TP ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C, VCC = 5 V ±5%) Symbol Parameter Condition Min. Typ.1 Max. Units ZOUT Transmit output impedance — 5 — Ω VOD Peak differential output voltage Load=100 Ω at TPOP and TPON — 3.5 — V tJIT Transmit timing jitter addition 0 line length 1 — — ±8 ns tJIT Transmit timing jitter addition After line model specified by IEEE 802.3 for 10BASE-T — — ±3.5 ns ZIN Receive input impedance Between TPIP/TPIN, CIP/CIN and DIP/DIN — 20 — kΩ VDS Differential squelch threshold — 420 — mV VDSL Lower squelch threshold — 250 — mV Notes: 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design, not subject to production testing. Table 6. SWITCHING CHARACTERISTICS (TA = 0°C to +70°C, VCC = 5 V ±5%) Symbol Parameter Condition Min. Typ. Max. Units Jabber Timing tJAB Maximum transmit time 20 — 150 ms tUJAB Unjab time 250 — 750 ms Link Integrity Timing tLL Time link loss 55 — 66 ms tLP1 Time between Link Integrity Pulses 8 — 24 ms tLP2 Interval for valid receive Link integrity Pulses 4.1 — 65 ms General tRST Receive start-up delay1 0 — 500 ns tTST Transmit start-up delay1 0 — 200 ns tLST Loopback start-up delay1 0 — 500 ns Note: Parameter is guaranteed by design; not subject to production testing. 17 MB86961A Table 7. RCLK/Start-of-Packet Timing Symbol Parameter tDATA Decoder acquisition time tCD CD turn-on delay tRDS Receive data setup from RCLK tRDH Receive data hold from RCLK Min. Typ.1 Max. Units AUI — 900 — ns TP — 1300 — ns AUI — 50 — ns TP — 400 — ns Mode 1 40 — — ns Modes 2, 3 and 4 30 — — ns Mode 1 10 — — ns Modes 2, 3 and 4 30 — — ns Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Note: Table 8. RCLK/End-of-Packet Timing Symbol Parameter Type Mode 1 Mode 2 Mode 3 Mode 4 Units tRCH RCLK hold after CD low Min. 0 1 27 5 bt tRD RCV data throughput delay Typ. 300 275 275 275 ns tCDOFF CD turn off delay Typ. 400 375 375 375 ns tIFG Receive block out Typ. 2 50 27 5 bt Notes: 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. CD Turn off delay measured from middle of last bit, so timing specification is unaffected by the value of the last bit. Table 9. Transmit Timing Symbol Parameter Min. Typ.1 Max. Units tEHCH TEN setup from TCLK — 30 — ns tDSCH TXD setup from TCLK — 30 — ns tCHEL TEN hold after TCLK — 5 — ns tCHDU TXD hold after TCLK — 5 — ns Note: Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Table 10. Collision Detection, COL/CI Output and Loopback Timing Symbol Parameter Min. Typ.1 Max. Units tCOLD COL turn on delay — 50 — ns tCOLOFF COL turn off delay — 160 — ns tSQED SQE Delay 0.65 — 1.6 ms tSQEP SQE Pulse Duration 500 — 1500 ns tKHEH LBK setup from TEN — 25 — ns tKHEL LBK hold after TEN — 0 — ns Note: Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 18 MB86961A MODE 1 (MD1=0, MD0=0) TIMING DIAGRAMS — FIGURES 12 - 17 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN tCD CD RCLK tRDH tRDS tDATA RXD 1 0 1 0 1 0 1 Figure 12. Mode 1 RCLK/SOP Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN tCDOFF CD tIFG tRD RCLK RXD 1 0 1 0 1 0 1 0 0 Note: RXD is triggered by the rising edge of RCLK, with RCLK advanced by 25 ns. The controller is sampled at the rising edge. Figure 13. Mode 1 RCLK/EOP Timing 19 MB86961A TEN tEHCH tCHEL TCLK tDSCH tCHDU TXD Figure 14. Mode 1 Transmit Timing CI tCOLOFF tCOLD COL Figure 15. Mode 1 Collision Detect Timing TEN tSQED COL tSQEP Figure 16. Mode 1 COL/CI Output Timing LBK tKHEH tKHEL TEN tCAEA CD Figure 17. Mode 1 Loopback Timing 20 MB86961A MODE 2 (MD1=0, MD0=1) TIMING DIAGRAMS — FIGURES 18 - 23 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN tCD CD RCLK tRDH tRDS tDATA RXD 1 0 1 0 1 Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge. Figure 18. Mode 2 RCLK/SOP Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN tCDOFF tIFG CD tRD RCLK RXD 1 0 1 0 1 0 1 0 0 Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge. Figure 19. Mode 2 RCLK/EOP Timing 21 0 1 MB86961A TEN tEHCH tCHEL TCLK tDSCH tCHDU TXD Figure 20. Mode 2 Transmit Timing CI tCOLOFF tCOLD COL Figure 21. Mode 2 Collision Detect Timing TEN t Carrier Detect Blocked tSQED tSQEP COL Figure 22. Mode 2 COL/CI Output Timing LBK tKHEH tKHEL TEN tCAEA CD Figure 23. Mode 2 Loopback Timing 22 MB86961A MODE 3 (MD1=1, MD0=0) TIMING DIAGRAMS — FIGURES 24 - 29 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN tCD CD RCLK tRDH tRDS tDATA RXD 1 0 1 0 1 Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge. Figure 24. Mode 3 RCLK/SOP Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN tCDOFF tIFG CD tRD 27 Bits RCLK RXD 1 0 1 0 1 0 1 0 0 Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge. Figure 25. Mode 3 RCLK/EOP Timing 23 0 1 MB86961A TEN tEHCH tCHEL TCLK tDSCH tCHDU TXD Figure 26. Mode 3 Transmit Timing CI tCOLOFF tCOLD COL Figure 27. Mode 3 Collision Detect Timing TEN tSQED tSQEP COL Figure 28. Mode 3 COL/CI Output Timing LBK tKHEH tKHEL TEN tCAEA CD Figure 29. Mode 3 Loopback Timing 24 MB86961A MODE 4 (MD1=1, MD0=1) TIMING DIAGRAMS — FIGURES 30 - 35 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN tCD CD RCLK tRDH tRDS tDATA RXD 1 0 1 0 1 Note: RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge. Figure 30. Mode 4 RCLK/SOP Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN tCDOFF tIFG CD tRD RCLK RXD 1 0 1 0 1 0 1 0 0 Note: RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge. Figure 31. Mode 4 RCLK/EOP Timing 25 0 1 MB86961A TEN tEHCH tCHEL TCLK tDSCH tCHDU TXD Figure 32. Mode 4 Transmit Timing CI tCOLOFF tCOLD COL Figure 33. Mode 4 Collision Detect Timing TEN tSQED COL tSQEP Figure 34. Mode 4 COL/CI Output Timing LBK tKHEH tKHEL TEN tCAEA CD Figure 35. Mode 4 Loopback Timing 26 MB86961A 44-pin plastic QFJ (PLCC) (LCC-44P-MO2) ORDERING INFORMATION: MB86961APD-G 44-pin plastic QFJ (PLCC) (Case No.: LCC-44P-MO2) +0.22 4.30 -0.11 (.169 +.009 -.004 ) +0.60 2.70 -0.41 +.024 (.106 -.046 ) 0.51(.020)MIN 17.53±0.13 SQ (.690±.005) 16.59±0.08 SQ (.653±.003) 1 6 44 40 1.27±0.13 (050±.005) 0.10(.004) 39 7 12.70(.500)REF INDEX 0.43(.017) TYP 16.03±0.51 (.631±.020) 0.66(.026) TYP 29 17 18 28 “A” Details of “A” part +0.05 0.20 -0.02 (.008 +.002 -.001 ) R0.75(.030) TYP R0.95(.037)TYP 16.03±0.51 (.631±.020) 1997 FUJITSU LIMITED C44052S-2C-4 No.: LEAD No. Dimension in mm (inches) 27 MB86961A ORDERING INFORMATION: MB86961APF-G 48-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-48P-M02) .106(2.70)MAX .677±.016 SQ .002(0.05)MIN 36 25 37 24 .472 +.012 SQ (12.0 +0.30 ) INDEX .535±.016 .346(8.80) 13 48 LEAD No. 1 12 .0315(0.80) .012±.002 .006(0.16) .006 +.002 (0.15 +0.05 ) M Details of “A” part “A” “B” Details of “B” part .024(0.60) .006(0.15) .006(0.15) 0° to 10° .071±.012 .020(0.50) 1992 FUJITSU LIMITED F48002S-9C 28 Dimensions in inches (millimeters) MB86961A Worldwide Headquarters Japan Fujitsu Limited Asia Tel: Fax: 1015 Kamiodanaka Nakaharaku Kawasaki 211 Japan Tel: Fax: +81 44 754 3753 +81 44 754 3332 http://www.fujitsu.co.jp/ +65 281 0770 +65 281 0220 Fujitsu Microelectronics Asia PTE Limited #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 http://www.fsl.com.sg/ USA Europe Tel: Fax: +1 408 922 9000 +1 408 922 9179 Fujitsu Microelectronics Inc 3545 North First Street San Jose CA 95134-1804 USA Tel: +49 6103 6900 Fax: +49 6103 69012 Tel: Fax: +1 800 866 8608 +1 408 922 9179 Customer Response Center Mon-Fri: 7am-5pm (PST) http://www.fujitsu.ede.com/ Fujitsu Mikroelektronik GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany http://www.fujitsumicro.com/ All Right Reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies. The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc. Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice. No part of the publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu Microelectronics, Inc. LAN-DS-20638-12/97 29