ETC MTD907

MYSON
TECHNOLOGY
MTD907
Ethernet Encoder/decoder and 10BaseT
Transceiver with Built-in Waveform Shaper
FEATURES
•
•
•
•
•
•
•
•
•
Pin-out and functionally compatible with Level One LXT907.
Built-in UTP waveform shaping function - no external filters required.
Integrated Manchester encoder/decoder.
10Base-T compliant transceiver and AUI transceiver.
Full duplex capability.
Automatic and manual interface selection (AUI/TP).
Automatic TP polarity detection and correction.
Heartbeat enable/disable function and jabber disable function.
Drives 4 LED status indicators.
GENERAL DESCRIPTION
MTD907 is an integrated Ethernet Endec and 10Base-T transceiver with built-in UTP transmission waveform
shaping function. The integrated encoder/decoder conforms to IEEE802.3 standards and provides all needed
active circuitry with which to interface the majority of IEEE802.3-conforming controllers to either the 10Base-T
media or attachment unit interface (AUI). The functions provided by MTD907 include Manchester
encoding/decoding, jabber detection, automatic media selection, reception squelch and transmission
waveform shaping, automatic UTP polarity detection and correction for the UTP media.
BLOCK DIAGRAM
AUT
LBK
PAULTE
TPA, TPB
MD0, MD1
TXC
TXC, TXE
CRS, RXC,
RXD
COL, JAB
DSQ
LEDR, LEDL,
LEDC, LEDT
JAB, PLR
MODE
CONTROL
WAVEFORM
SHAPING
AMP
TNA, TNB
MANCHESTER
CODER/
DECODER
COLLISION
LOGIC
MEDIA
SELECTION
AND
CONTROL
REMOTE
SIGNALING
TST
TRST
TEST LOGIC
AC/DC
SQUELCH
RDP
RDN
NTH
DOP
AMP
LED/STATUS
LOGIC
RLD,
RJAB,
RCMPT
LINKTEST
POLARITY
DETECT
DON
AC/DC
SQUELCH
XCAL
OSC
X2
DIP, CIP
DIN, CIN
REFERENCE Circuit
X1
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
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MTD907
1.0 PIN CONNECTION
MD1
MD0
NTH
CIN
CIP
VDD1
DON
DOP
DIN
DIP
PAU
44-pin PLCC
7
6
5
4
3
2
1 44 43 42 41 40
39
8
38
9
37
10
11
12
13
36
MTD907
44-pin PLCC
35
34
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
RDN
RDP
DSQ
TNB
TNA
VDD2
VSS2
TP A
TP B
PLR
RJAB
LEDR
LEDT
LEDL
LEDC
LBK
VSS1
TRST
RCMPT
RXD
CRS
RXC
RLD
LTE
JAB
TST
TXC
TXD
TXE
X1
X2
COL
AUT
1.0 PIN DESCRIPTIONS
No
1
34
2
3
4
Symbol
VDD1
VDD2
CIP
CIN
NTH
I/O
I
I
I
Name
Positive Power
Supply
Collision Input
Pair
Normal
Threshold
Mode
Selection
5
6
MD0
MD1
I
I
7
RLD
O
8
LTE
I
9
JAB
O
10
TST
I
Remote Link
Down
Link Test
Enabler
Jabber
Indicator
Test
11
TXC
O
Transmit Clock
12
13
TXD
TXE
I
I
Transmit Data
Transmission
Enabler
14
15
X1
X2
O
I
Crystal
Oscillator
16
COL
O
Collision
Detection
Description
+5 Volt power supplies.
AUI transceiver CI circuit differential input pair.
Active high input, selects normal TP input threshold;
when NTH=0, the TP input threshold is reduced 4.5dB.
Mode selection pins. Determines controller compatibility
mode: mode 00 is for AMD, 01 for Intel, 10 for Fujitsu, 11
for NSC.
Active high output. Signifies when the remote port is in
link down condition.
Active high input. Enables the link test when high; when
low, disables the TP link test.
Active high output. High output indicates jabber
condition.
Active high input internally pulled low. This pin is used in
test mode only.
10 MHz clock output. Should be directly connected to
the controller to synchronize transmission operation.
Input signal, NRZ data from the controller.
Active high input. Enables data transmission and begins
jabber timer; should be synchronized with TXC by the
controller.
Built-in crystal oscillator. A 20 MHz crystal must be
connected across these 2 pins or an external clock must
be applied to X2 with X1 left open.
Output signal; drives controller collision detection input.
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17
AUT
I
Automatic Port
Selection
18
LEDR/
JABDIS
O
I
Receive LED,
Disable Jabber
19
LEDT/
PWDN
O
I
Transmit LED,
Power Down
20
LEDL/
LPSS
O
I
Link LED,
Link Pass
21
LEDC/
FDX
O
I
Collision LED,
Full Duplex
22
23
33
24
LBK
VSS1
VSS2
TRST
I
-
25
RCMPT
O
26
RXD
O
Loopback
Negative
Power Supply
Test Mode
Reset
Remote
Compatible
Received Data
27
CRS
O
Carrier Sense
28
RXC
O
29
RJAB
O
30
PLR
O
31
32
35
36
TPB
TPA
TNA
TNB
O
O
O
O
Received
Clock
Remote
Jabber
Polarity
Reversal
Twisted-pair
Transmission
Pairs A & B
37
DSQ
I
Disable SQE
38
39
40
RDP
RDN
PAU
I
I
I
Receive Data
Input Pair (TP)
Select
Port/AUI
41
42
43
44
DIP
DIN
DOP
DON
I
I
O
O
AUI Reception
Pair
AUI
Transmission
Pair
I
MTD907
Active high input. When active, MTD907 defaults to the
AUI port if the TP link test fails. If driven low, the port
selection is determined by the PAU pin.
Active low output driver for receiving the LED indicator.
The LED 'on’time is extended by at least 80 ms.
When externally tied or driven low, disables the internal
jabber timer.
Active low output driver for LED transmission indicator.
The LED 'on’time is extended by at least 80ms.
When externally tied or driven low, forces MTD907 into
power-down state.
Active low output driver for link integrity LED indicator.
When externally tied or driven low, forces MTD907 into
'link pass' state.
Active low output driver for collision indicator LED. The
LED on time is extended by at least 80 ms.
When externally tied low, enables MTD907 for full duplex
operation by disabling internal TP loopback and TP
collision detection functions.
Active high input; enables internal loopback mode.
Power supply ground.
Active high test mode reset signal. Only recognized in
test mode (TST pin high) and internally pulled low.
Active high output; indicating TP transceiver at the
remote end is compatible with remote signaling.
Output signal; recovers received data. Should be
connected directly to controller.
Output signal; detects incoming network traffic. Should
be connected directly to controller.
Output signal; recovers received clock. Should be
connected directly to controller.
Active high output signal; indicates when the remote end
is in jabber state.
Active high output signal; indicates when the TP polarity
is reversed.
Two differential driver pairs (A and B) for the TP cable.
The outputs are pre-equalized, thus no external filters
are required. The TPX pins and TNX pins must be
shorted together with a 24.9W 1% to match the 100W TP
impedance.
Active high input. When driven high, selects MTD907 for
hub/switch/repeater operation by disabling signal quality
test (heartbeat).
Differential input pair for TP cable. The reception filter is
integrated on-chip. No external filter is required.
Recognized only if the AUT pin is low. PAU=1 selects
AUI port, PAU=0 selects TP port. It is recommended
that you tie this pin to ground if driving AUT pin high.
Differential input pair from the AUI transceiver DI circuit.
Differential output pair to the AUI transceiver DO circuit.
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2.0 CONTROLLER COMPATIBILITY MODE DESCRIPTIONS
Mode
1
2
3
4
Controllers:
Advanced Micro Devices AM7990 or compatible controllers.
Intel 82586 or 82596, or compatible controllers.
Fujitsu MB86950 or MB86960, Seeq 8005 or compatible continuous
clock-type controllers.
National Semiconductor 8390, TI TMS380C26 or compatible controllers.
MD0
0
0
1
MD1
0
1
0
1
1
3.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage (Vcc)
DC Input Voltage (Vin)
Storage Temperature
Operating Temperature
-0.5V to +7V
-0.5V to Vcc+0.5V
o
o
-65 C to 150 C
o
o
0 C to 70 C
4.0 OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Supply Current
Symbol
Vcc
Top
Min
4.75
0
Typ
5
-
Max
5.25
70
Icc
Icc
Icc
Icc
-
35
60
50
3
55
80
70
6
Unit
V
Test Conditions
o
C
mA
mA
mA
mA
Idle
Transmitting on TP
Transmitting on AUI
Power-down mode
5.0 ELECTRICAL CHARACTERISTICS (under operating conditions)
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage (LED)
Output Rise Time (TXC, RXC)
Output Fall Time (TXC, RXC)
X2 Rise Time (external clock)
X2 Duty Cycle (external clock)
Symbol
VIL
VIH
VOL
VOH
VOL
TR
TR
TF
TF
-
Min
2.0
2.4
-
Typ
3
2
3
2
50/50
Max
0.8
0.4
0.7
12
8
12
8
10
40/60
Unit
V
V
V
V
V
ns
ns
ns
ns
ns
%
Test Conditions
Iol=1.6mA
Iol=40uA
Iol=10mA
Cload=20pF
TTL load
Cload=20pF
TTL load
6.0 AUI ELECTRICAL CHARACTERISTICS (under operating conditions)
Parameter
Input Low Current
Input High Current
Differential Output Voltage
Differential Squelch Threshold
Symbol
IL
IH
VOD
VDS
Min
550
150
Typ
220
Max
-700
500
1200
350
Unit
uA
uA
mV
mV
Test Conditions
5 MHz square wave
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7.0 TP ELECTRICAL CHARACTERISTICS (under operating conditions )
Parameter
Transmit Output Impedance
Peak Differential Output
Voltage
Transmit Timing Jitter
Addition
Transmit Timing Jitter
Added by MAU and PLS
Sections
Receive Input Impedance
Differential Squelch
Threshold
Symbol
Zout
Vod
Min
3.3
Typ
5
3.5
Max
3.7
Unit
W
V
Test Conditions
-
-
6.4
10
Internal MAU
-
-
3.5
5.5
+/ns
+/ns
Zin
Vds
300
20
420
585
kW
mV
Vds
180
250
345
mV
Load=100 W
After IEEE 802.3specified TP line model
Between input pairs
5MHz square wave
input, NTH=1
5MHz square wave
input, NTH=0
8.0 SWITCHING CHARACTERISTICS (under operating conditions)
Jabber Timing:
Parameter
Maximum Transmission Time before Jabber
Unjab Time
Symbol
-
Min
20
250
Typ
-
Max
150
750
Unit
ms
ms
Link Integrity Pulse Timing:
Parameter
Link Loss Time
Transmit Link Integrity Timing
Receive Link Integrity Pulse Timing
Symbol
-
Min
63
8
3.1
Typ
-
Max
64
24
63
Unit
ms
ms
ms
Start-of-Frame Timing, AUI
Parameter
Decoder Acquisition Time
CD Turn-on Delay
Symbol
tDATA
tCD
Min
-
Typ
700
50
Max
1100
200
Unit
ns
ns
Start-of-Frame Timing, TP
Parameter
Decoder Acquisition Time
CD Turn-on Delay
Symbol
tDATA
tCD
Min
-
Typ
1000
400
Max
1700
550
Unit
ns
ns
RXC Timing
Parameter
Receive Data Setup from RXC
Receive Data Hold from RXC
RXC Shut-off Delay from CRS
Assertion
RXC Hold after CRS Turn-off
RXD Data through Delay
CRS Turn-off Delay
RXC Switching Delay after CD Off
Symbol
Typ
Mode
1
Mode
2
Mode3
Mode
4
tRDS
tRDH
tSWS
Min.
Min.
Typ.
43
10
-
30
30
-
30
30
+/-100
30
30
-
ns
ns
ns
tRCH
tRD
Max.
Max.
Typ.
8
400
500
-
1
375
475
-
375
475
120
8
375
475
-
bt
ns
ns
ns
tCRSOFF
tSWE
Unit
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Transmission Timing
Parameter
TXE Setup from TXC
TXD Setup from TXC
TXE Hold from TXC
TXD Hold from TXC
Transmission Start-up Delay, AUI
Transmission Start-up Delay, TP
Transmission through Delay, AUI
Transmission through Delay, TP
Symbol
tEHCH
tDACH
tCHEL
tCHDU
tSTUD
tSTUD
tTPD
tTPD
Min
22
22
5
5
-
Typ
200
350
-
Max
450
450
300
350
Unit
ns
ns
ns
ns
ns
ns
ns
ns
COL and Loopback Timing
Parameter
COL Turn-on Delay
COL Turn-off Delay
COL (SQE) Delay after TXE Off
COL (SQE) Pulse Duration
LBK Setup from TXE
LBK Hold after TXE
Symbol
tCOLD
tCOLOFF
tSQED
tSQEP
tKHEH
tKHEL
Min
0.65
500
10
10
Typ
25
0
Max
500
500
1.6
1500
-
Unit
ns
ns
us
ns
ns
ns
0
1
1
9.0 TIMING DIAGRAM
Mode 1, RXC - Start of Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
0
TPIP/TPIN
or DIP/DIN
CRS
tCRS
RXC
tRDS
tDATA
tRDH
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Mode 1, RXC - End of Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CRS
tRD
RXC
tRCH
RXD
1
0
1
0
1
0
1
0
0
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Mode 1, Transmission Timing
TXE
tEHCH
tCHEL
TXC
tDSCH
TXD
tCHDU
tTPD
tSTUD
TPO
Mode 1, Collision Detection Timing
CI
tCOLOFF
tCOLD
COL
Mode 1, HBT/CI Output Timing
TXE
tSQED
COL
tSQEP
Mode 1, Loopback Timing
LBK
tKHEH
tKHEL
TXE
tCAEA
CRS
Mode 2, RXC - Start of Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
TPIP/TPIN
or DIP/DIN
CRS
tCRS
RXC
tRDS
tDATA
tRDH
RXD
1
0
1
0
0
1
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Mode 2, RXC - End of Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CRS
tRD
RXC
tRCH
RXD
1
0
1
0
1
0
1
0
0
Mode 2, Transmission Timing
TXE
tCHEL
tEHCH
TXC
tDSCH
tCHDU
TXD
tTPD
tSTUD
TPO
Mode 2, Collision Detection Timing
CI
COL
tCOLD
tCOLOFF
Mode 2, HBT/CI Output Timing
TXE
tSQED
COL
tSQEP
Mode 2, Loopback Timing
LBK
TXE
CRS
tKHEH
tKHEL
tCAEA
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Mode 3, RXC - Start of Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
0
1
1
1
TPIP/TPIN
or DIP/DIN
CRS
tCRS
Recovered form Input Data Stream
tSWS
RXC
Generated form TCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
Mode 3, RXC - End of Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CRS
tRD
Recovered Clock
Generated from TXC
tSWE
RXC
RXD
1
0
1
0
1
0
1
0
0
Mode 3, Transmission Timing
TXE
tEHCH
tCHEL
TXC
tDSCH
TXD
tCHDU
tSTUD
tTPD
TPO
Mode 3, Collision Detection Timing
CI
COL
tCOLD
tCOLOFF
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MTD907
Mode 3, HBT/CI Output Timing
TXC
tSQED
COL
tSQEP
Mode 3, Loopback Timing
LBK
tKHEH
TXE
tKHEL
tCAEA
CRS
Mode 4, RXC - Start of Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
TPIP/TPIN
or DIP/DIN
CRS
tCRS
RXC
tRDS
tRDH
tDATA
RXD
1
0
1
0
0
1
Mode 4, RXC - End of Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CRS
tRD
RXC
tRCH
RXD
1
0
1
0
1
0
1
0
0
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MTD907
Mode 4, Transmission Timing
TXE
tEHCH
tCHEL
TXC
tDSCH
TXD
tCHDU
tTPD
tSTUD
TPO
Mode 4, Collision Detection Timing
CI
COL
tCOLOFF
tCOLD
Mode 4, HBT/CI Output Timing
TXE
tSQED
COL
tSQEP
Mode 4, Loopback Timing
LBK
tKHEH
tKHEL
TXE
CRS
tCAEA
10.0 FUNCTIONAL DESCRIPTION
MTD907 is an Ethernet Endec and 10BaseT transceiver with a built-in waveform shaper that performs the
Media Attachment Unit (MAU) and Physical Layer Signaling (PLS) functions as defined in the IEEE802.3
specification.
MTD907 can function as either a PLS-only device interfacing a supported controller to an AUI cable or as an
integrated PLS/MAU interfacing a supported controller to the TP cable. In the following functional descriptions,
aII functions are defined as seen from the controller side of the interface.
Controller Compatibility
MTD907 is configurable for interfacing with common industrial standard Ethernet controllers. The mode
selection pins, MD0 and MD1, provide the mode configuration capability as tabulated in Section 2.0. The timing
specification of different controller modes is specified in Section 8.0’s RXC timing. Applicable timing diagrams
for each of the supported controller modes are included in Section 9.0.
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Transmission Function
MTD907 samples TXD data from the controller at the rising edge of the TXC signal and then performs the
Manchester encoding on the input data stream. The encoded data is then transmitted through either the AUI
port or the TP cable network . The built-in waveform-shaping circuits produce pre-distorted TP output
waveform comforming to the jitter template specified in IEEE802.3. No external filter is required in MTD907
applications. If LTE is enabled and the TP port is selected as the network media, MTD907 transmits link
integrity test pulses at regular intervals during idle periods. Due to its voltage drive and TP output drivers' low
output impedence, the driving end source resistance is decided by external resistors.
Jabber Control Function
The jabber control function of MTD907 closely follows the IEEE 802.3 specification. The MTD907 built-in
watchdog timer prevents the DTE from continuous transmission. When the TXE input is asserted for longer
than the time limit, both transmission and loopback functions are disabled, and the JAB output pin will be
asserted. Once MTD907 enters the jabber state, it will exit it only if the TXE signal remains idle for a period of
250-750ms.
The jabber function of MTD907 can be disabled by externally pulling the LEDR pin low.
SQE Function
MTD907 supports the signal quality error (SQE) function, which can be disabled through DSQ input. If the SQE
function is enabled (DSQ=0), MTD907 will transmit the SQE signal after every successful 10BaseT
transmission. This SQE signal will be a 10 +/- 5 bit time assertion of the COL output pin. If the AUI port is
selected as the transmission media, the SQE is determined by the external MAU.
When using MTD907 in hub or switch applications, the SQE function must be disabled (DSQ=1).
Reception Function
MTD907’s reception function recovers both the clock and data from the incoming Manchester-encoded data
stream from either the AUI or TP port. The recovered clock and data are sent to the controller through the RXC
and RXD pins, respectively.
Internal filter and squelch functions are integrated in MTD907 in order to discriminate noise from valid TP
signals. No external reception filter is needed. If the incoming signal from either the AUI or TP input exceeds
the squelch requirements, the CRS pin will be asserted and internal timing recovery circuits will be activated. A
fast lock-on PLL will typically lock on to the input signal in 5-bit time. If the input signal drops below the squelch
threshold or signal transitions are absent for 8-bit time (typical), the internal circuit will return to its idle state.
TP Interface Polarity Correction Function
The MTD907 TP interface polarity correction function detects and corrects TP polarity error using both TP link
pulses and end-of-frame data. The TP polarity is internally decided as being reversed only if 8 consecutive link
pulses or end-of-frame data are received with a polarity opposite to the expected polarity. Upon detecting TP
polarity reversal, MTD907 will automatically exchange the received TP data polarity. This correction function is
always active.
Collision Detection Function
The collision detection function is applicable only if MTD907 is used as PLS/MAU in a standard 10BaseT
network. A collision is detected if valid data is present simultaneously on both TP transmission and TP
reception circuits. MTD907 reports this to the controller via the assertion of the COL output. If MTD907 is used
as PLS only, i.e. external MAU, then the collision detection is based on valid signals from the AUI port.
If MTD907 is configured to function as a full-duplex TP transceiver by externally pulling the LEDC pin low, the
collision detection function for TP will be disabled internally. Also, if the MTD907 LBK pin is driven high, all
collision function is disabled.
Loopback Function
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MTD907 has 4 different loopback modes. If the TP port and half-duplex mode are selected, MTD907 provides
the normal loopback function as defined in 10BaseT standards. If the TP port and full-duplex mode are
selected, the internal loopback is disabled, allowing external loopback through TP ports. If the AUI interface is
selected and LBK=0, the external AUI loopback mode is in effect. If LBK is driven high, the internal collision
detection function is disabled, and the transmission data is forced to loop back through internal Manchester
ENDEC with disregard as to which interface port is selected.
Link Integrity Test
The MTD907 link integrity test is implemented as specified in IEEE802.3 10BaseT standards. This function is
enabled when input pin 8 (LTE) is driven high. While LTE=1, MTD907 will recognize link integrity pulses
received in absence of a valid TP data packet. If both link integrity pulses and TP data packets are not detected
within 65-66ms, MTD907 will enter a link-fail state and will disable the transmission and normal loopback
functions. After it enters such a state, MTD907 will exit the link-fail state if one valid TP packet or 2 or more link
integrity pulses are received. Link integrity pulses received within an interval of 4ms will be ignored by MTD907.
Remote Signaling
The link integrity pulses transmitted by MTD907 include encoded local status information by varying the link
pulse intervals. This feature is implemented in such a way that MTD907 is compatible with any chip that uses
the same signaling scheme, such as many of the Level One products.
Three different pieces of status information are encoded and are described as follows. Local link-down is
encoded as link pulse interval sequences of 10ms-15ms-20ms. Local jabber is encoded as link pulse interval
sequences of 10ms-20ms-15ms. Remote-signaling capability is encoded as a link pulse interval sequence of
10ms-20ms. MTD907 will detect and decode link pulses, thus encoding and reporting them through the RLD,
RJAB and RCMPT output pins, respectively.
11.0 Comparison of MTD907 and Level One LXT901/LXT907
Waveform Synthesis Method
The main difference between MTD907 and Level One LXT901/LXT907 is the waveform synthesis method used.
Level One products use a table-look-up method with a 5-bit DAC operating at 70MHz. MTD907 uses a delay
cell based 16-tab FIR filter operating at 160MHz to synthesize the pre-distorted transmission waveforms
required by 10BaseT standards with much refined waveform.
Mode1 and Mode4 End-of-Frame RXC Timing
Eight end-of-frame RXC pulses are provided for better controller interfacing for Mode1 and Mode 4 style timing.
MTD907 vs LXT901
These 2 devices share the same functionality except for Pin 37. LXT901 uses this pin as a UTP/STP selection
input while MTD907 uses this pin as DSQ to disable or enable the built-in SQE function. For typical LXT901
UTP applications, this pin is tied high in order to select UTP interface. For these applications, MTD907 should
be a drop-in replacement for LXT901 if the attached controller does not check the SQE signal.
MTD907 vs LXT907
The only noticeable difference between these 2 devices is that when LXT907 enters the power-down mode, it
will drive the LEDL low periodically, while MTD907 disables all output pins once forced into the power-down
mode.
MTD907 Revision 4.5 01/23/1997
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MYSON
TECHNOLOGY
MTD907
12.0 APPLICATIONS
Please see the attached application schematics.
13.0 PACKAGE DIMENSION
44 PIN PLCC
Unit: Inch
0.045*45 0
0.180 MAX.
PIN #1 HOLE
0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005
0.610 +/-0.02
0.653 +/-0.003
0.500
70TYP.
0.010
0.050 TYP.
0.026~0.032 TYP.
0.070
0.070
0.653 +/-0.003
0.6902 +/-0.005
MTD907 Revision 4.5 01/23/1997
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