FUJITSU MB91F362GAPFVS

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16401-2E
32-bit RISC Microcontroller
CMOS
FR50 Family MB91360G Series
MB91FV360GA/F361GA/F362GA
■ DESCRIPTION
The Fujitsu MB91360G series is a standard microcontroller containing a wide range of I/O peripherals and bus
control functions. The MB91360G series features a 32-bit RISC CPU (FR50 series) core and is suitable for
embedded control applications requiring high-performance and high-speed CPU processing. The MB91360G
series also contains up to 4 Kbyte instruction cache memory and other internal memories to improve the execution
speed of the CPU.
■ FEATURES
• Execution time : down to 15.6 ns (64 MHz)
• FR50 series CPU : RISC architecture
The CPU has a general-purpose register architecture with improved numeric implementation whereby a wide
range of delayed branch instructions reduces losses in execution time due to pipeline breaks.
Bit manipulation instructions and memory access instructions have been enhanced resulting in improved code
efficiency and execution speed for control implementation.
• A five-stage pipeline structure provides high-speed processing (one instruction per cycle)
• 32-bit linear address space : 4 Gbytes
• Fixed 16-bit instruction size (basic instructions)
• High-speed multiplication/step division
• High-speed interrupt processing (6 cycles)
• General-purpose registers : 16 × 32 bits
(Continued)
■ PACKAGE
401-pin Ceramics PGA
208-pin plastic QFP
(PGA-401C-A02)
(FPT-208P-M04)
MB91360G Series
(Continued)
• External bus interface unit with a wide range of functions
Divides the external memory space into a maximum of eight areas. Chip select signal setting, data bus width
selection (8, 16, 32-bit) , and area size can be specified for each area.
• Address bus up to 32 bit wide
• Programmable auto-wait function
• Internal instruction cache
The MB91360G series contains up to 4-Kbyte instruction cache to improve the execution speed of external
programs.
• Two-way set associative caching
• DMAC
Direct memory access (DMA) can be used to perform various types of data transfer without going via the CPU.
This improves system performance.
• Eight channels (including up to 3 external channels)
• Three transfer modes supported : single/block, burst, continuous transfer
• Power consumption control mechanisms
The MB91360G series contains a number of functions for controlling the operating clock to reduce power
consumption.
• Software control : Sleep and stop/real time clock functions
• Hardware control : Hardware standby function
• Gear (divider) function : The CPU and peripheral clock frequencies can be set independently.
• Contains a range of peripheral functions
• UART, U-timer
• Real Time Clock (with optional subclock operation and subclock calibration module)
• Stepper Motor Control
• Sound Generator
• Serial IO (SIO) , SIO-Prescaler
• Power Down Reset
• Alarm Comparator
• IO-Timer
• I2C Interface
• 10 Bit D/A Converter
• CAN Interface
• 10-bit A/D converter
• 16-bit reload timer
• 16-bit PWM timer
• Watchdog timer
• Bit search module
• Interrupt controller
• External interrupt inputs
• I/O port function
• Interrupt levels
“16 maskable interrupt levels”
• Other
• Power supply voltage
• 5 V power supply used, the internal regulator creates internal supply of 3.3 V
• Package : MB91FV360GA uses a PGA401 package, MB91F361GA and MB91F362GA are delivered in a
QFP208 package.
2
MB91360G Series
■ PRODUCT LINEUP
Resource Channels
Memory Size
MB91FV360GA
MB91F361GA
MB91F362GA
4 KB / 4 KB
1 KB / 1 KB
- / 4 KB
D-bus RAM
16 KB
12 KB
12 KB
F-bus RAM
16 KB
4 KB
4 KB
Flash/ROM
512 KB on F-bus
512 KB on ext. bus
512 KB on F-bus
Boot ROM
2 KB
2 KB
2 KB
CAN
4 ch
3 ch
3 ch
Stepper Motor Control
4 ch
4 ch
4 ch
Sound Generator
1 ch
1 ch
1 ch
PPG
8 ch
8 ch
8 ch
Input Capture
4 ch
4 ch
4 ch
Output Compare
4 ch
4 ch
4 ch
Free Running Timer
2 ch
2 ch
2 ch
D/A Converter
2 ch
2 ch
2 ch
A/D Converter
16 ch
16 ch
16 ch
I2C 100 kHz
I2C 400 kHz
1 ch
1 ch
1 ch
Alarm Comparator
1 ch
1 ch
1 ch
SIO/SIO prescaler
2 ch
2 ch
2 ch
UART/U-Timer
3 ch
3 ch
3 ch
16-bit Reload Timer
6 ch
6 ch
6 ch
Ext. Interrupt
8 ch
8 ch
8 ch
Non maskable Interrupt
1


Real Time Clock
1
1
1
32 kHz subclock option for RTC
yes
no
no
subclock calibration
yes
no
no
LED port
8 bit
8 bit
8 bit
Power down Reset
1
1
1
Bit search Module
1
1
1
Watchdog timer
1
1
1
Ext. Address Bus
32 bit
21 bit
21 bit
Ext. Data Bus
32 bit
32 bit
32 bit
Ext. DMA
3 ch
1 ch
1 ch
64 MHz
64 MHz
64 MHz
Cache/Instruction RAM
Max. operating frequency
3
MB91360G Series
■ PIN ASSIGNMENTS
• MB91FV360GA
(BOTTOM VIEW)
23
24
69
119
174
230
173
118
68
22
172
117
67
21
20
170
115
65
19
114
64
18
168
113
63
17
112
62
16
166
111
61
15
110
60
14
164
109
59
13
108
58
12
162
107
57
106
160
386
342
387
343
388
242
295
344
389
187
243
296
345
390
346
391
393
349
377
394
350
376
395
351
375
396
352
374
397
353
398
373
354
399
372
355
400
371
356
401
370
357
368
369
321
270
320
269
214
158
105
367
56
267
156
103
313
207
98
49
(PGA-401C-A02)
312
206
204
95
203
94
45
1
138
39
87
139
40
88
140
41
89
141
42
90
142
43
91
143
44
92
144
201
202
146
93
38
86
200
257
258
147
46
2
310
137
199
256
309
259
148
47
3
311
205
96
358
260
149
48
4
359
261
150
97
5
360
262
151
50
6
314
208
99
361
263
152
51
7
315
209
100
362
264
153
52
8
316
210
101
363
265
154
53
9
317
211
102
364
266
155
54
10
365
318
212
213
55
11
319
268
157
104
366
37
85
198
255
308
136
197
254
307
36
84
196
253
306
135
195
252
305
35
83
194
251
304
134
193
250
303
34
82
192
249
302
133
191
248
301
81
190
247
300
132
189
246
299
348
188
245
298
392
378
244
297
347
215
159
4
241
294
186
379
322
271
216
385
341
240
293
185
131
323
272
217
384
340
239
292
184
130
324
273
218
161
383
339
238
291
183
129
80
325
274
219
382
338
237
290
182
128
79
326
275
220
163
337
236
289
181
127
78
327
276
221
235
288
180
126
77
33
328
277
222
165
336
179
125
76
32
329
278
223
234
124
75
31
330
279
224
167
178
287
381
123
74
30
331
280
225
335
73
29
332
281
226
169
286
28
333
282
227
177
233
232
380
122
121
27
72
71
176
285
334
283
228
171
116
66
229
175
231
284
70
120
26
25
145
INDEX
MB91360G Series
• MB91F361GA/F362GA
(TOP VIEW)
208
OCU
PI [6:0]
PH [7:0]
PG [7:0]
P3 [7:0]
P4 [7:0]
P5 [7:0]
P6 [4:0] P7 [4:6]
P8 [7:0]
P9 [7:0]
ext. Bus Data
ext. Bus Address
Chip
Select
ext. Bus Control
ICU
ext. Int.
LED
PJ [7:0]
PR [7:0]
PS [7:0]
P0 [7:0]
INDEX
DAC
ADC
PL [7:0]
104
IN2
IN1
IN0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
VSS
VDD
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
LTEST
CPUTEST
TEST
ATG
VDD
VSS
ALARM
DA1
DA0
AVSS
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AVRH
AVCC
DEOP0
DACK0
DREQ0
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
DMA
PN [5:0] PM [3:0]
PK [7:0]
PO [7:0]
P1 [7:0]
PP [5:0]
,,,
105
ADC
Mode
,,,
,,,
,,,,
,,,
,,
PQ [5:0]
1
I2C Sound XTAL + PLL
P2 [7:0]
SOT2
VSS
VCC3C
VDD
HVSS
PWM1P0
PWM1M0
PWM2P0
PWM2M0
HVDD
PWM1P1
PWM1M1
PWM2P1
PWM2M1
HVSS
PWM1P2
PWM1M2
PWM2P2
PWM2M2
HVDD
PWM1P3
PWM1M3
PWM2P3
PWM2M3
HVSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
VDD
VSS
D15
D16
D17
D18
D19
D20
D21
D22
D23
SIO
D24
D25
D26
D27
D28
D29
D30
D31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VDD
VSS
A16
A17
A18
A19
A20
CS4
CS5
CS6
RDY
BGRNT
BRQ
RD
WR0
WR1
WR2
WR3
AS
ALE
CLK
AH/BOOT
CS0
CS1
CS2
CS3
VDD
VSS
SMC
157
PPG
PB [2:0]
156
CAN
SIN2
SOT1
SIN1
SOT0
SIN0
RX2
TX2
RX1
TX1
RX0
TX0
VSS
VDD
OCPA7
OCPA6
OCPA5
OCPA4
OCPA3
OCPA2
OCPA1
OCPA0
SCK3
SOT3
SIN3
SCK4
SIN4
SOT4
SCL
SDA
SGA
SGO
VCI
CPO
VSS
X1A
X0A
X1
X0
VDD
SELCLK
MONCLK
INIT
HST
MD2
MD1
MD0
VSS
OUT3
OUT2
OUT1
OUT0
IN3
UART
53
52
Chip
Select
(FPT-208P-M04)
5
MB91360G Series
■ PIN DESCRIPTIONS
Pin No.
Pin No.
QFP208
PGA401
9
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
202
A0
I/O

Q
Q
Ext. Bus Address Bit 0
10
310
A1
I/O

Q
Q
Ext. Bus Address Bit 1
11
201
A2
I/O

Q
Q
Ext. Bus Address Bit 2
12
357
A3
I/O

Q
Q
Ext. Bus Address Bit 3
26
358
VSS





25
401
VDD





13
257
A4
I/O

Q
Q
Ext. Bus Address Bit 4
14
144
A5
I/O

Q
Q
Ext. Bus Address Bit 5
15
309
A6
I/O

Q
Q
Ext. Bus Address Bit 6
16
256
A7
I/O

Q
Q
Ext. Bus Address Bit 7
17
200
A8
I/O

Q
Q
Ext. Bus Address Bit 8
18
356
A9
I/O

Q
Q
Ext. Bus Address Bit 9
19
308
A10
I/O

Q
Q
Ext. Bus Address Bit 10
20
92
A11
I/O

Q
Q
Ext. Bus Address Bit 11

400
VSS





21
44
A12
I/O

Q
Q
Ext. Bus Address Bit 12
22
255
A13
I/O

Q
Q
Ext. Bus Address Bit 13
23
143
A14
I/O

Q
Q
Ext. Bus Address Bit 14
24
199
A15
I/O

Q
Q
Ext. Bus Address Bit 15
27
307
A16
I/O

Q
Q
Ext. Bus Address Bit 16

355
28
91
A17
I/O

Q
Q
Ext. Bus Address Bit 17
29
142
A18
I/O

Q
Q
Ext. Bus Address Bit 18
30
254
A19
I/O

Q
Q
Ext. Bus Address Bit 19

399
VSS





31
43
A20
I/O

Q
Q
Ext. Bus Address Bit 20

198
A21
I/O

Q

Ext. Bus Address Bit 21

141
A22
I/O

Q

Ext. Bus Address Bit 22

90
A23
I/O

Q

Ext. Bus Address Bit 23

197
A24
I/O
P70
Q

Ext. Bus Address Bit 24

306
A25
I/O
P71
Q

Ext. Bus Address Bit 25

42
A26
I/O
P72
Q

Ext. Bus Address Bit 26

253
DREQ2
I/O
P73
A

DMA Request 2
FV360GA
F361GA
F362GA
Function
not connected
(Continued)
6
MB91360G Series
(Continued)
Pin No.
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
QFP208
PGA401
32
140
CS4
I/O
P74
A
A
Chip Select 4

398
VSS






354
VDD





33
196
CS5
I/O
P75
A
A
Chip Select 5
34
89
CS6
I/O
P76
A
A
Chip Select 6

41
CS7
I/O
P77
A

Chip Select 7 (CANs)
35
305
RDY
I/O

S
S
Ext. Bus Control
36
139
BGRNT
I/O
P81
A
A
Ext. Bus Control
37
88
BRQ
I/O
P82
A
A
Ext. Bus Control
38
40
RD
I/O

S
S
Ext. Bus Control
39
304
WR0
I/O

S
S
Ext. Bus Control

353
VSS





40
39
WR1
I/O

S
S
Ext. Bus Control
41
252
WR2
I/O

S
S
Ext. Bus Control
42
251
WR3
I/O

S
S
Ext. Bus Control
43
87
AS
I/O
P90
A
A
Ext. Bus Control
44
38
ALE
I/O
P91
A
A
(Ext. Bus Control, not yet
implemented)

397
45
194
CLK
I/O

A
A
Ext. Bus Clk
46
195
AH/BOOT
I/O
P93
A
A
Test Signal/Boot Signal
47
137
CS0
I/O
P94
A
A
Chip select 0
52
352
VSS





48
250
CS1
I/O
P95
A
A
Chip Select 1
49
351
CS2
I/O
P96
A
A
Chip Select 2
50
138
CS3
I/O
P97
A
A
Chip Select 3
53
37
AN8
I/O
PG0
B
B
ADC Input 8
54
86
AN9
I/O
PG1
B
B
ADC Input 9
55
136
AN10
I/O
PG2
B
B
ADC Input 10
56
303
AN11
I/O
PG3
B
B
ADC Input 11
57
302
AN12
I/O
PG4
B
B
ADC Input 12
58
36
AN13
I/O
PG5
B
B
ADC Input 13

396
VSS





51
350
VDD





not connected
(Continued)
7
MB91360G Series
(Continued)
Pin No.
8
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
QFP208
PGA401
59
85
AN14
I/O
PG6
B
B
ADC Input 14
60
249
AN15
I/O
PG7
B
B
ADC Input 15
61
193
DREQ0
I/O
PB0
A
A
DMA Request 0
62
135
DACK0
I/O
PB1
A
A
DMA Acknowledge 0
63
84
DEOP0
I/O
PB2
A
A
DMA EOP 0

301
DREQ1
I/O
PB3
A

DMA Request 1

192
DACK1
I/O
PB4
A

DMA Acknowledge 1

191
DEOP1
I/O
PB5
A

DMA EOP 1

395
VSS






35
DACK2
I/O
PB6
A

DMA Acknowledge 2

349
DEOP2
I/O
PB7
A

DMA EOP 2
64
83
AVCC




Analog VCC
65
300
AVRH


R
R
Analog Reference High
66
248
AN0
I/O
PH0
B
B
ADC Input 0

393
67
82
AN1
I/O
PH1
B
B
ADC Input 1
68
134
AN2
I/O
PH2
B
B
ADC Input 2
69
34
AN3
I/O
PH3
B
B
ADC Input 3

394
VSS





70
190
AN4
I/O
PH4
B
B
ADC Input 4
71
247
AN5
I/O
PH5
B
B
ADC Input 5
72
81
AN6
I/O
PH6
B
B
ADC Input 6
73
133
AN7
I/O
PH7
B
B
ADC Input 7

299
AVRL


R

Analog Reference Low
74
348
AVSS




Analog VSS
75
246
DA0
O

C
C
DAC Output
76
189
DA1
O

C
C
DAC Output
77
132
ALARM
I

D
D
Alarm Comparator Input
78
392
VSS





79
347
VDD





80
298
ATG
I/O
PI3
A
A
ADC Trigger Input
81
245
TEST
I

E
E
Test Input
82
188
CPUTEST
I

E
E
Test Input
83
297
LTEST
I

E
E
Test Input
(Continued)
not connected
MB91360G Series
(Continued)
Pin No.
Pin No.
Pin Name
I/O
General
Purpose
IO Port
Circuit Type
FV360GA
F361GA
F362GA
Function
QFP208
PGA401

244
84
346
LED0
I/O
PJ0
J
J
LED Port 0
85
187
LED1
I/O
PJ1
J
J
LED Port 1
86
345
LED2
I/O
PJ2
J
J
LED Port 2

391
VSS






390
87
243
LED3
I/O
PJ3
J
J
LED Port 3
88
131
LED4
I/O
PJ4
J
J
LED Port 4
89
296
LED5
I/O
PJ5
J
J
LED Port 5
90
242
LED6
I/O
PJ6
J
J
LED Port 6
91
186
LED7
I/O
PJ7
J
J
LED Port 7
94
344
INT0
I/O
PK0
A
A
Ext. Interrupt 0
95
295
INT1
I/O
PK1
A
A
Ext. Interrupt 1
96
80
INT2
I/O
PK2
A
A
Ext. Interrupt 2
93
389
VSS





97
33
INT3
I/O
PK3
A
A
Ext. Interrupt 3
98
241
INT4
I/O
PK4
A
A
Ext. Interrupt 4
99
130
INT5
I/O
PK5
A
A
Ext. Interrupt 5
100
185
INT6
I/O
PK6
A
A
Ext. Interrupt 6
101
294
INT7
I/O
PK7
A
A
Ext. Interrupt 7
92
343
VDD





102
79
IN0
I/O
PL0
A
A
ICU Input 0
103
129
IN1
I/O
PL1
A
A
ICU Input 1
104
240
IN2
I/O
PL2
A
A
ICU Input 2
110
388
VSS





105
32
IN3
I/O
PL3
A
A
ICU Input 3
106
184
OUT0
I/O
PL4
A
A
OCU Output 0
107
128
OUT1
I/O
PL5
A
A
OCU Output 1
108
78
OUT2
I/O
PL6
A
A
OCU Output 2
109
183
OUT3
I/O
PL7
A
A
OCU Output 3
111
293
MD0
I

T
T
Mode Pin 0
112
31
MD1
I

T
T
Mode Pin 1
113
239
MD2
I

T
T
Mode Pin 2

127
NMI
I

E

not connected
not connected
Non maskable Interrupt
(Continued)
9
MB91360G Series
(Continued)
Pin No.
10
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
VSS





QFP208
PGA401

387

342
114
182
HST
I

E
E
Hardware Standby

77
RST
I

E

Reset Pin
115
30
INIT
I

U
U
Initial Pin
116
292
MONCLK
O

G
G
System Clock Output
117
126
SELCLK
I

F
F
Clock Selection
118
76
VDD





119
29
X0


H
H
4 MHz Oscillator Pin
120
291
X1


H
H
4 MHz Oscillator Pin

341
VSS






28
ICLK
IO

L

ICE CLK

238
ICS0
O

G

ICE Status

237
ICS1
O

G

ICE Status

75
ICS2
O

G

ICE Status

27
ICD0
I/O

N

ICE Data

386
VDD






180
ICD1
I/O

N

ICE Data

181
ICD2
I/O

N

ICE Data

124
ICD3
I/O

N

ICE Data

340
VSS






236
BREAK
I

O

ICE Break

339
TDT0
I/O

W

Trace Data

125
TDT1
I/O

W

Trace Data

26
TDT2
I/O

W

Trace Data

74
TDT3
I/O

W

Trace Data

123
TDT4
I/O

W

Trace Data

290
TDT5
I/O

W

Trace Data

289
TDT6
I/O

W

Trace Data

25
TDT7
I/O

W

Trace Data

385
VSS3






338
VDD3






73
TDT8
I/O

W

Trace Data

235
TDT9
I/O

W

Trace Data
(Continued)
not connected
MB91360G Series
(Continued)
Pin No.
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
QFP208
PGA401

179
TDT10
I/O

W

Trace Data

122
TDT11
I/O

W

Trace Data

72
TDT12
I/O

W

Trace Data

288
TDT13
I/O

W

Trace Data

178
TDT14
I/O

W

Trace Data

177
TDT15
I/O

W

Trace Data

384
VSS3






24
TDT16
I/O

W

Trace Data

337
TDT17
I/O

W

Trace Data

71
TDT18
I/O

W

Trace Data

287
TDT19
I/O

W

Trace Data

234
TDT20
I/O

W

Trace Data

382

70
TDT21
I/O

W

Trace Data

121
TDT22
I/O

W

Trace Data

23
TDT23
I/O

W

Trace Data

383
VSS3






176
TDT24
I/O

W

Trace Data

233
TDT25
I/O

W

Trace Data

69
TDT26
I/O

W

Trace Data

120
TDT27
I/O

W

Trace Data

286
TDT28
I/O

W

Trace Data

336
TDT29
I/O

W

Trace Data

232
TDT30
I/O

W

Trace Data

175
TDT31
I/O

W

Trace Data

119
TDT32
I/O

W

Trace Data

381
VSS3






335
VDD3






285
TDT33
I/O

W

Trace Data

231
TDT34
I/O

W

Trace Data

174
TDT35
I/O

W

Trace Data

284
TDT36
I/O

W

Trace Data

230
TDT37
I/O

W

Trace Data

334
TDT38
I/O

W

Trace Data
(Continued)
not connected
11
MB91360G Series
(Continued)
Pin No.
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
QFP208
PGA401

173
TDT39
I/O

W

Trace Data

333
TDT40
I/O

W

Trace Data

380
VSS3






379

229
TDT41
I/O

W

Trace Data

118
TDT42
I/O

W

Trace Data

283
TDT43
I/O

W

Trace Data

228
TDT44
I/O

W

Trace Data

172
TDT45
I/O

W

Trace Data

332
TDT46
I/O

W

Trace Data

282
TDT47
I/O

W

Trace Data

68
TDT48
I/O

W

Trace Data

378
VSS3






22
TDT49
I/O

W

Trace Data

227
TDT50
I/O

W

Trace Data

117
TDT51
I/O

W

Trace Data

171
TDT52
I/O

W

Trace Data

281
TDT53
I/O

W

Trace Data

331
VDD3






67
TDT54
I/O

W

Trace Data

116
TDT55
I/O

W

Trace Data

226
TDT56
I/O

W

Trace Data

377
VSS3






21
TDT57
I/O

W

Trace Data

170
TDT58
I/O

W

Trace Data

115
TDT59
I/O

W

Trace Data

66
TDT60
I/O

W

Trace Data

169
TDT61
I/O

W

Trace Data

280
TDT62
I/O

W

Trace Data

20
TDT63
I/O

W

Trace Data

225
TDT64
I/O

W

Trace Data

114
TDT65
I/O

W

Trace Data

376
VSS3






330
not connected
not connected
(Continued)
12
MB91360G Series
(Continued)
Pin No.
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
QFP208
PGA401

168
TDT66
I/O

W

Trace Data

65
TDT67
I/O

W

Trace Data

19
TDT68
I/O

W

Trace Data

279
TAD0
O

X

Trace Address

113
TAD1
O

X

Trace Address

64
TAD2
O

X

Trace Address

18
TAD3
O

X

Trace Address

278
TAD4
O

X

Trace Address

329
VSS3






17
TAD5
O

X

Trace Address

224
TAD6
O

X

Trace Address

223
TAD7
O

X

Trace Address

63
TAD8
O

X

Trace Address

16
TAD9
O

X

Trace Address

375
VDD3






166
TAD10
O

X

Trace Address

167
TAD11
O

X

Trace Address

111
TAD12
O

X

Trace Address

328
VSS3






222
TAD13
O

X

Trace Address

327
TAD14
O

X

Trace Address

112
TAD15
O

X

Trace Address

15
TWR
O

X

Trace Control

62
TOE
O

X

Trace Control

110
TCLK
I/O

W

Trace Control

277
TCE1
O

X

Trace Control

276
TADSC
O

X

Trace Control

14
EXRAM
I

P

Trace Control

374
VSS






326
VDD





126
61
SGO
I/O
PM0
A
A
Sound Generator SGO
127
221
SGA
I/O
PM1
A
A
Sound Generator SGA
128
165
SDA
I/O
PM2
Y
Y
I2C SDA
129
109
SCL
I/O
PM3
Y
Y
I2C SCL
(Continued)
13
MB91360G Series
(Continued)
Pin No.
14
Pin No.
QFP208
PGA401

60

275
Pin Name
I/O
General
Purpose
IO Port
Circuit Type
FV360GA
F361GA
F362GA
Function
not connected
VDD





32 kHz Oscillator Pin
121
164
X0A
I

I
reserved
should be
connected
to be VSS
122
163
X1A
O

I
reserved
should be
left open
32 kHz Oscillator Pin
123
373
VSS






13
VDD





124
325
CPO
not connected
reserved
should be
left open

not connected
reserved
should be
connected
to be VSS

125
59
VCI

274

220

371
130
58
SOT4
I/O
PN0
A
A
SIO Output
131
108
SIN4
I/O
PN1
A
A
SIO Input
132
12
SCK4
I/O
PN2
A
A
SIO Clock

372
VSS






162
VDD





133
219
SIN3
I/O
PN3
A
A
SIO Input
134
57
SOT3
I/O
PN4
A
A
SIO Output
135
107
SCK3
I/O
PN5
A
A
SIO Clock

273
VSS






324
VDD





136
218
OCPA0
I/O
PO0
A
A
PPG Output
137
161
OCPA1
I/O
PO1
A
A
PPG Output
138
106
OCPA2
I/O
PO2
A
A
PPG Output

370
VSS






323
VDD





139
272
OCPA3
I/O
PO3
A
A
not connected
VSS





not connected
PPG Output
(Continued)
MB91360G Series
(Continued)
Pin No.
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
QFP208
PGA401
140
217
OCPA4
I/O
PO4
A
A
PPG Output
141
160
OCPA5
I/O
PO5
A
A
PPG Output

271
VSS





144
216
VDD





142
322
OCPA6
I/O
PO6
A
A
PPG Output
143
159
OCPA7
I/O
PO7
A
A
PPG Output
146
321
TX0
I/O
PP0
Q
Q
CAN 0 TX
145
369
VSS






368
147
215
RX0
I/O
PP1
Q
Q
CAN 0 RX
148
105
TX1
I/O
PP2
Q
Q
CAN 1 TX
149
270
RX1
I/O
PP3
Q
Q
CAN 1 RX

214
VSS






158
VDD





150
320
TX2
I/O
PP4
Q
Q
CAN 2 TX
151
269
RX2
I/O
PP5
Q
Q
CAN 2 RX

56
TX3
I/O
PP6
Q

CAN 3 TX

367
VSS






11
VDD






213
RX3
I/O
PP7
Q

CAN 3 RX
152
104
SIN0
I/O
PQ0
A
A
UART 0 Input
153
157
SOT0
I/O
PQ1
A
A
UART 0 Output

268
VSS






319
VDD





154
55
SIN1
I/O
PQ2
A
A
UART 1 Input
155
103
SOT1
I/O
PQ3
A
A
UART 1 Output
156
212
SIN2
I/O
PQ4
A
A
UART 2 Input

366
VSS





160
10
VDD




VDD
157
156
SOT2
I/O
PQ5
A
A
UART 2 Output
159
102
VCC3C


C
C
Bypass Capacitor Pin

54
158
155



267
not connected
not connected
VSS



not connected
(Continued)
15
MB91360G Series
(Continued)
Pin No.
Pin No.
Circuit Type
Pin Name
I/O
General
Purpose
IO Port
FV360GA
F361GA
F362GA
Function
QFP208
PGA401
162
9
PWM1P0
I/O
PR0
K
K
SMC 0
163
211
PWM1M0
I/O
PR1
K
K
SMC 0
164
101
PWM2P0
I/O
PR2
K
K
SMC 0
161
365
HVSS






318
165
154
PWM2M0
I/O
PR3
M
M
SMC 0
167
53
PWM1P1
I/O
PR4
K
K
SMC 1
168
8
PWM1M1
I/O
PR5
K
K
SMC 1

266
HVSS





166
100
HVDD





169
52
PWM2P1
I/O
PR6
K
K
SMC 1
170
7
PWM2M1
I/O
PR7
M
M
SMC 1

265
171
317
HVSS






6
HVDD





172
210
PWM1P2
I/O
PS0
K
K
SMC 2
173
209
PWM1M2
I/O
PS1
K
K
SMC 2
174
51
PWM2P2
I/O
PS2
K
K
SMC 2

5
HVSS






364
175
152
PWM2M2
I/O
PS3
M
M
SMC 2
177
153
PWM1P3
I/O
PS4
K
K
SMC 3
178
98
PWM1M3
I/O
PS5
K
K
SMC 3
181
316
HVSS





176
208
HVDD





179
315
PWM2P3
I/O
PS6
K
K
SMC 3
180
99
PWM2M3
I/O
PS7
M
M
SMC 3

4

50
VSS





182
97
VDD





183
264
D0
I/O

Q
Q
Ext. Bus Data Bit 0
184
263
D1
I/O

Q
Q
Ext. Bus Data Bit 1
185
3
D2
I/O

Q
Q
Ext. Bus Data Bit 2

363
VSS





not connected
not connected
not connected
not connected
(Continued)
16
MB91360G Series
(Continued)
Pin No.
Pin No.
Pin Name
I/O
General
Purpose
IO Port
Circuit Type
FV360GA
F361GA
F362GA
Function
QFP208
PGA401

314
186
49
D3
I/O

Q
Q
Ext. Bus Data Bit 3
187
207
D4
I/O

Q
Q
Ext. Bus Data Bit 4
188
151
D5
I/O

Q
Q
Ext. Bus Data Bit 5
189
96
D6
I/O

Q
Q
Ext. Bus Data Bit 6
190
48
D7
I/O

Q
Q
Ext. Bus Data Bit 7
191
262
D8
I/O

Q
Q
Ext. Bus Data Bit 8
192
150
D9
I/O

Q
Q
Ext. Bus Data Bit 9
193
149
D10
I/O

Q
Q
Ext. Bus Data Bit 10

362
VSS





194
2
D11
I/O

Q
Q
Ext. Bus Data Bit 11
195
313
D12
I/O

Q
Q
Ext. Bus Data Bit 12
196
47
D13
I/O

Q
Q
Ext. Bus Data Bit 13
197
261
D14
I/O

Q
Q
Ext. Bus Data Bit 14
200
206
D15
I/O

Q
Q
Ext. Bus Data Bit 15
198
360
VDD





201
46
D16
I/O

Q
Q
Ext. Bus Data Bit 16
202
95
D17
I/O

Q
Q
Ext. Bus Data Bit 17
203
1
D18
I/O

Q
Q
Ext. Bus Data Bit 18
199
361
VSS





204
148
D19
I/O

Q
Q
Ext. Bus Data Bit 19
205
205
D20
I/O

Q
Q
Ext. Bus Data Bit 20
206
45
D21
I/O

Q
Q
Ext. Bus Data Bit 21
207
94
D22
I/O

Q
Q
Ext. Bus Data Bit 22
208
260
D23
I/O

Q
Q
Ext. Bus Data Bit 23
1
312
D24
I/O

Q
Q
Ext. Bus Data Bit 24
2
204
D25
I/O

Q
Q
Ext. Bus Data Bit 25
3
147
D26
I/O

Q
Q
Ext. Bus Data Bit 26
4
93
D27
I/O

Q
Q
Ext. Bus Data Bit 27

359
VSS






311
5
259
D28
I/O

Q
Q
Ext. Bus Data Bit 28
6
203
D29
I/O

Q
Q
Ext. Bus Data Bit 29
7
146
D30
I/O

Q
Q
Ext. Bus Data Bit 30
8
258
D31
I/O

Q
Q
Ext. Bus Data Bit 31
not connected
not connected
17
MB91360G Series
■ I/O CIRCUIT TYPE
Type
A
Circuit type
R
P
Digital output
N
Digital output
Remarks
• I/O,
CMOS Automotive Schmitt-Trigger Input,
STOP control,
IOH = 4 mA, IOL = 4 mA
VSS
Digital input
Stop control
Analog input
R
P
Digital output
R
N
Digital output
B
• I/O,
CMOS Automotive Schmitt-Trigger Input,
Analog Input,
STOP control,
IOH = 4 mA, IOL = 4 mA
VSS
Digital input
Stop control
• Analog output
VCC
P
C
N
VSS
Analog output
• Analog Input
VCC
P
D
R
N
VSS
Analog input
(Continued)
18
MB91360G Series
(Continued)
Type
Circuit type
VCC
VCC
P
E
Remarks
• CMOS Schmitt-Trigger Input,
Pullup Resistor: 50 kΩ
P
N
R
VSS
VSS
Digital input
• CMOS Schmitt-Trigger Input
VCC
P
F
R
N
VSS
Digital input
• Tristate Output,
IOH = 4 mA, IOL = 4 mA
VCC
P
Digital output
N
Digital output
G
VSS
• 4 MHz Oscillator Pin
X1
Clock input
H
X0
Stop control
(Continued)
19
MB91360G Series
(Continued)
Type
Circuit type
Remarks
• 32 kHz Oscillator Pin
X1A
Clock input
I
X0A
Stop control
J
R
P
Digital output
N
Digital output
• I/O,
CMOS Automotive Schmitt-Trigger Input,
STOP control (LED) ,
IOH = 14 mA, IOL = 24 mA
VSS
Digital input
Stop control
K
R
P
Digital output
N
Digital output
• I/O,
CMOS Automotive Schmitt-Trigger Input,
STOP control (SMC) ,
IOH = 30 mA, IOL = 30 mA
• Typ. slew rate of 40 ns
VSS
Digital input
Stop control
VCC
L
R
P
Digital output
N
Digital output
• I/O,
CMOS Input; 5 V or 3 V input,
IOH = 4 mA, IOL = 4 mA
VSS
Digital input
(Continued)
20
MB91360G Series
(Continued)
Type
Circuit type
Remarks
Analog input
R
P
Digital output
R
N
Digital output
M
• I/O,
CMOS Automotive Schmitt-Trigger Input,
Analog Input, STOP control (SMC) ,
IOH = 30 mA, IOL = 30 mA
• Typ. slew rate of 40 ns
VSS
Digital input
Stop control
Digital input
VCC
R
N
N
P
Digital output
N
Digital output
• I/O,
CMOS Input,
Pulldown Resistor: 50 kΩ,
5 V or 3 V input,
IOH = 4 mA, IOL = 4 mA
VSS
Digital input
VCC
R
• CMOS Input,
Pulldown Resistor: 50 kΩ,
5 V or 3 V input
VCC
P
O
N
N
VSS
VSS
• CMOS Input; 3 V input
VCC
P
P
R
N
VSS
Digital input
(Continued)
21
MB91360G Series
(Continued)
Type
Q
Circuit type
R
Remarks
P
Digital output
N
Digital output
• I/O CMOS Input,
STOP control,
IOH = 4 mA, IOL = 4 mA
VSS
Digital input
Stop control
VCC
P
S
R
P
Digital output
N
Digital output
• I/O,
CMOS Schmitt-Trigger Input,
STOP control,
Pullup Resistor : 10 kΩ,
IOH = 4 mA, IOL = 4 mA
VSS
Digital input
Stop control
• CMOS Input
• can withstand high VID for flash
programming
T
Control signal
MD Input
R
VCC
VCC
P
U
P
• CMOS Schmitt-Trigger Input,
Pullup Resistor: 50 kΩ,
3 V and 5 V input to the core
N
R
VSS
VSS
Digital input
(Continued)
22
MB91360G Series
(Continued)
Type
Circuit type
Remarks
VCC
P
V
R
P
Digital output
N
Digital output
• I/O,
CMOS Schmitt-Trigger Input,
STOP control,
Pullup Resistor: 50 kΩ,,
IOH = 4 mA, IOL = 4 mA
VSS
Digital input
Stop control
• I/O,
CMOS Input; 3 V input
3V
W
R
P
Digital output
N
Digital output
VSS
Digital input
• Tristate Output, 3 V
3V
P
Digital output
N
Digital output
X
VSS
Y
R
P
Digital output
N
Digital output
• I/O CMOS Input,
STOP control,
IOH = 3 mA, IOL = 3 mA,
in I2C mode operating as open drain
outputs
VSS
Digital input
Stop control
Note : Symbols used in circuit types (Common to all circuit diagrams)
P : P channel transistor
N : N channel transistor
R : Diffusion resistor
23
MB91360G Series
Circuit
Type
24
Description
A
I/O, IOH = 4 mA / IOL = 4 mA, CMOS Automotive Schmitt-Trigger Input, STOP control
B
I/O, IOH = 4 mA / IOL = 4 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control
C
Analog Output
D
Analog Input
E
CMOS Schmitt-Trigger Input, Pull-up Resistor: 50 kΩ,
F
CMOS Schmitt-Trigger Input
G
Tristate Output, IOH = 4 mA / IOL = 4 mA
H
4 MHz Oscillator Pin
I
32 kHz Oscillator pin
J
I/O, IOH = 14 mA / IOL = 24 mA, CMOS Automotive Schmitt-Trigger Input, STOP control (LED)
K
I/O, IOH = 30 mA / IOL = 30 mA, CMOS Automotive Schmitt-Trigger Input, STOP control, slew rate
improved for EMC (SMC)
L
I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input; 5 V or 3 V input
M
I/O, IOH = 30 mA / IOL = 30 mA, CMOS Automotive Schmitt-Trigger Input, Analog Input, STOP control,
slew rate improved for EMC (SMC)
N
I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, Pulldown Resistor: 50 kΩ,; 5 V or 3 V input
O
CMOS Input, Pulldown Resistor: 50 kΩ,; 5 V or 3 V input
P
CMOS Input; 3 V input
Q
I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, STOP control
R
AVRL / AVRH Input
S
I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input, STOP control, Pull-up Resistor: 10 kΩ,
T
CMOS Input, can withstand VID for flash programming
U
CMOS Schmitt-Trigger Input, Pull-up Resistor: 50 kΩ,, 3.3 V and 5 V inputs to core
W
I/O, IOH = 4 mA / IOL = 4 mA, CMOS Input; 3 V input
X
Tristate Output, IOH = 4 mA / IOL = 4 mA, 3 V
Y
I/O, IOH = 3 mA / IOL = 3 mA (I2C) , CMOS Input, STOP control
MB91360G Series
■ HANDLING DEVICES
1. Preventing latch-up
Latch-up may occur in a CMOS IC if a voltage greater than VDD or less than VSS is applied to an input or output
pin or if the voltage applied between VDD and VSS exceeds the rating. If latch-up occurs, the power supply current
increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are
not exceeded in circuit operation.
2. Connecting unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be tied to VDD or VSS through resistors. In this case those resistors should be more
than 2 KOhm.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
The resistor of more than 2 KOhm is used to limit currents through the protection diodes. In case of voltages at
the not used pin of 0.3 V or more below VSS or 0.3 V or more above VDD currents which could cause latch-up will
flow through those diodes.
3. External reset input
When inputting an “L” level to the INIT pin, hold this low level at the INIT pin long enough so that after release
of the low level at INIT and the passing of the built in waiting time stable oscillation of the oscillation circuit is
achieved. INIT must be pulled low for at least 8 cycles of the 4 MHz oscillation clock.
4. Power supply pins
All VDD pins should be connected to the same potential (exception can be the external bus interface on F361GA
and F362GA) . The analogue supply voltage (AVCC) must not be turned on before the digital supply voltage. If
the external bus interface is supplied with 3.3 V this voltage also must not be turned on before the 5 V digital
voltage has been switched on. If the supply voltage to the external bus interface is switched off (it may not be
tristate but should be pulled low) it must be made sure that all related signals do not have a voltage higher than
this pulled down supply.
When multiple VDD and VSS pins are provided, be sure to connect all VDD and VSS pins to the power supply or
ground externally. Although pins at the same potential are connected together in the internal device design so
as to prevent malfunctions such as latch-up, connecting all VDD and VSS pins appropriately minimizes unwanted
radiation, prevents malfunction of strobe signals due to increases in the ground level, and keeps the overall
output current rating.
Also, take care to connect VDD and VSS to current source in the lowest possible impedance.
Connection of a ceramic bypass capacitor of approximately 0.1 µF between VDD and VSS close to the device is
recommended.
The MB91360G series contains a regulator. To use the device with the 5-V power supply, supply 5-V power to
the VCC pins and be sure to connect a bypass capacitor of 10 µF parallel to 10 nF to the VCC3C pin for the regulator.
[Use with 5-V power supply]
5V
VCC
5V
AVCC
VCC3C
10 µF
10 nF
AVRH
AVSS
VSS
GND
25
MB91360G Series
5. Crystal oscillator circuit
Noise in the vicinity of the X0 and X1 pins can be a cause of device malfunction. Design the circuit board so that
X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to
the device as possible.
A printed circuit board design that surrounds the X0 and X1 pins with ground provides for stable operation and
is strongly recommended.
6. Mode pins
Connect the mode pins (MD0 to MD2) directly to VDD or VSS.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the mode pins to VDD or VSS and to provide a low-impedance connection.
7. Turning the power supply on
Immediately after power on always execute INIT at the INIT pin (start with a low level at the INIT pin) . Hold this
low level at the INIT pin long enough so that after release of the low level at INIT and the passing of the built in
waiting time stable oscillation of the oscillation circuit is achieved. INIT must be pulled low for at least 8 cycles
of the 4 MHz oscillation clock.
The analogue supply voltage (AVCC) must not be turned on before the digital supply voltage. If the external bus
interface is supplied with 3.3 V this voltage also must not be turned on before the 5 V digital voltage has been
switched on.
8. A state in turning power on
Output pin level is not guranteed while supply voltage does not reach minimum operation voltage in turning
power on.
26
MB91360G Series
■ BLOCK DIAGRAM
Clock
Generation
FR50
Core
User RAM
D-bus
32
Watchdog
Timer
Instruction
Cache/RAM
32
Bit Search
Module
Boot ROM
2 KB
F-bus RAM
32
DMA
Controller
Bus
Converter
32
on FV360GA, F362GA
Flashmemory
on F361GA
32
External Bus
Interface
R-Bus
Adapter
16
SIO Prescaler/
SIO
ADC
DAC
CAN
External
Interrupt
U-Timer/
UART
Subclock
Calibration
I2C
Reload
Timer
Alarm
Comparator
Real Time
Clock
Power Down
Reset
ICU
FreeRunning
Timer
OCU
Voltage
regulator
LED
Sound
Generator
Stepper Motor
Control
Prog. Pulse
Generator
27
MB91360G Series
■ CPU CORE
1. Memory Space
00 : 0000
Direct
00 : 03FF
Direct (short) addressing
0..0FF : Byte access
0..1FF : Halfword access (16 bit)
0..3FF : Word access (32 bit)
IO Area
00 : 07FF
00 : 1000
DMA
Internal memory area
00 : 1024
01 : 1000
I-RAM
01 : 1000 - 01 : 1400 on F361GA
01 : 1FFF
03 : C000
D-bus RAM
03 : D000 - 03 : FFFF on F361GA, F362GA
03 : FFFF
04 : 0000
F-bus RAM
04 : 0000 - 04 : 0FFF on F361GA, F362GA
Boot ROM
0F : F000 - 0F : F7FF on F361GA
04 : 3FFF
05 : 0000
05 : 07FF
08 : 0000
128 K
Flash Memory
on F-bus
(FV360GA, F362GA)
128 K
128 K
64 K
0F : 4000
0F : FFFF
16 K
16 K
Bootsector
32 K
Fixed Reset Vector
10 : 0000
CAN
10 : 07FF
18 : 0000
128 K
128 K
128 K
Flash Memory
on external bus
(F361GA)
64 K
16 K
28
1F : 4000
16 K
1F : FFFF
32 K
Bootsector
Addresses for CAN and flash
memory on external bus depend
on settings for the chip select areas
CS7 and CS1 respectively.
The addresses given here are valid
for the CS1 and CS7 settings done
in the Boot ROM.
MB91360G Series
2. Dedicated Registers
Each of the dedicated registers is used for a particular purpose. The dedicated registers consist of the program
counter (PC) , program status (PS) , table base register (TBR) , return pointer (RP) , system stack pointer (SS
P) , user stack pointer (USP) , and multiplication and division result registers (MDH/MDL) .
32 bits
Program counter
PC
Program status
PS
Table base register
Initial value
XXXX XXXXH (Indeterminate)
000F FC00H
TBR
Return pointer
XXXX XXXXH (Indeterminate)
RP
System stack pointer
SSP
0000 0000H
User stack pointer
USP
XXXX XXXXH (Indeterminate)
Multiplication and division
results resisters
MDH
XXXX XXXXH (Indeterminate)
MDL
XXXX XXXXH (Indeterminate)
(1) Program status (PS)
Bit position
31
20
16

10
0
8 7

ILM
SCR
CCR
CCR : Condition Code Register
SCR : System Condition Code Register
ILM : Interrupt Level Mask
29
MB91360G Series
(2) Condition Code Register (CCR)
(Bit)
7
6
5
4
3
2
1
0
Initial value


S
I
N
Z
V
C
--00XXXXB
(3) System Condition Code Register (SCR)
(Bit) 10
9
8
Initial value
D1
D0
T
XX0B
19
18
17
(4) Interrupt Level Mask Register (ILM)
(Bit)
20
16
ILM4 ILM3 ILM2 ILM1 ILM0
30
Initial value
01111B
MB91360G Series
3. General-Purpose Registers
The general-purpose registers are CPU registers R0 to R15. The register are used as the accumulator for
operations and as pointers (a field indicating an address) for memory access. The user can specify the purpose
for which the general-purpose registers are used.
Register bank structure
32-bits
R0
Initial value
XXXX XXXXH
R1
R12
R13
AC (Accumulator)
R14
FP (Frame Pointer)
XXXX XXXXH
R15
SP (Stack Pointer)
0000 0000H
Among 16 general-purpose registers, the following registers assume a special purpose. This enhances some
instructions.
R13 : Virtual accumulator (AC)
R14 : Frame pointer (FP)
R15 : Stack pointer (SP)
The initial value of R0 to R14 after a reset is indeterminate. The initial value of R15 is 00000000H (SSP value) .
31
MB91360G Series
■ MODE SETTING
The FR50 series of devices uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation
mode.
(1) Mode Pins
Three mode pins (MD2 to MD0) are used to specify the reset mode vector access area.
Mode Pins
Reset vector
Mode name
Remarks
access area
MD2
MD1
MD0
0
0
0
Internal ROM mode vector
Internal
0
0
1
External ROM mode vector
External


remaining settings
The mode register is used to set the bus
width.
Reserved
(2) Mode Register (MODR)
The data to be written to 0000_7FDH using mode vector fetch is called mode data.
MODR is located at 0000_07FDH. After an operation mode has been set in MODR, the device operates in this
operation mode. MODR is set only when a reset factor (INIT level) occurs. User programs cannot write data to
MODR.
< Mode Register (MODR) >
Address
0000 07FDH
7
6
5
4
3
2
1
0
0
0
0
0
0
ROMA
WTH1
WTH0
Initial value
XXXXXXXX
Operation mode setting bit
[Bits 7 to 3] : (Reserved bits)
Always set 00000 at bits 7 to 3. Operation is not guaranteed when other values are set.
[Bit 2] : ROMA (internal ROM enable bit)
The ROMA bit is used to set whether to validate the internal ROM area (Fbus memory area) .
ROMA
Function
Remarks
32
0
External ROM mode
1
Internal ROM mode
Access to the Fbus area is external.
MB91360G Series
[Bits 1 and 0] : WTH1 and WTH0 (bus width/single chip mode specifying bits)
The WTH1 and WTH0 bits are used to set the bus width (valid when operation mode is external bus mode) and
the single chip mode. When the operation mode is the external bus mode, this value is set at the BW1 and BW0
bits of AMD0 (CS0 area) .
WTH1
WTH0
Function
Remarks
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
32-bit bus width
External bus mode
1
1
Single chip mode
(3) Fixed Vector
If MB91360 series devices are started in mode MD[2 : 0] = 000, the internal fixed mode vector (FMV = 0x06)
and the fixed reset vector are used. The fixed reset vector points to the start address of the internal Boot ROM.
This enables access to the F-bus area, to the internal CAN modules and the internal flash memory.
See also section Boot ROM.
33
MB91360G Series
■ I/O MAP
Address
Register
+0
+1
+2
+3
000000H
reserved
reserved
reserved
reserved
000004H
reserved
reserved
reserved
PDR7 [R/W]
-111 - - - -
000008H
PDR8 [R/W]
- - - - - XX -
PDR9 [R/W]
XXXXXXX1

PDRB [R/W]
- - - - - XXX
Block
T-unit
Port Data
Register

00000CH
000010H
PDRG [R/W]
XXXXXXXX
PDRH [R/W]
XXXXXXXX
PDRI [R/W]
X---X---
PDRJ [R/W]
XXXXXXXX
000014H
PDRK [R/W]
XXXXXXXX
PDRL [R/W]
XXXXXXXX
PDRM [R/W]
- - - - XXXX
PDRN [R/W]
- - XXXXXX
000018H
PDRO [R/W]
XXXXXXXX
PDRP [R/W]
- - XXXXX
PDRQ [R/W]
- - XXXXX
PDRR [R/W]
XXXXXXXX
00001CH
PDRS [R/W]
XXXXXXXX



000020H
to
00003CH

000040H
EIRR [R/W]
00000000
ENIR [R/W]
00000000
000044H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
R-bus
Port Data
Register
Reserved
ELVR [R/W]
00000000 00000000
CLKR2 [R/W]
- - - - - 000
reserved
000048H
TMRLR0 [W]
XXXXXXXX XXXXXXXX
TMR0 [R]
XXXXXXXX XXXXXXXX
00004CH

TMCSR0 [R/W]
- - - - 0000 - - - 00000
000050H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
TMR1 [R]
XXXXXXXX XXXXXXXX
000054H

TMCSR1 [R/W]
- - - - 0000 - - - 00000
000058H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
TMR2 [R]
XXXXXXXX XXXXXXXX
00005CH

TMCSR2 [R/W]
- - - - 0000 - - - 00000
000060H
SSR0 [R/W]
00001 - 00
SIDR0 [R/W]
XXXXXXXX
SCR0 [R/W]
00000100
SMR0 [R/W]
00 - - 0 - 0 -
000064H
ULS0 [R/W]
- - - - 0000



Ext int/NMI
DLYI/I-unit
RTC
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0
(Continued)
34
MB91360G Series
(Continued)
Address
000068H
Register
+0
+1
UTIM0/UTIMR0 [R/W]
00000000 00000000
+2
+3
DRCL0 [W]
--------
UTIMC0 [R/W]
0 - - - 0 - 01
00006CH
SSR1 [R/W]
00001 - 00
SIDR1 [R/W]
XXXXXXXX
SCR1 [R/W]
00000100
SMR1 [R/W]
00 - - 0 - 0 -
000070H
ULS1 [R/W]
- - - - 0000



DRCL1 [W]
--------
UTIMC1 [R/W]
0 - - - - - 01
000074H
UTIM1/UTIMR1 [R/W]
00000000 00000000
000078H
SSR2 [R/W]
00001 - 00
SIDR2 [R/W]
XXXXXXXX
SCR2 [R/W]
00000100
SMR2 [R/W]
00 - - 0 - 0 -
00007CH
ULS2 [R/W]
- - - - 0000



Block
U-TIMER 0
UART1
U-TIMER 1
UART2
000080H
UTIM2/UTIMR2 [R/W]
00000000 00000000
DRCL2 [W]
--------
UTIMC2 [R/W]
0 - - - 0 - 01
U-TIMER2
000084H
SMCS0 [R/W]
00000010 - - - - 00-0
SES0 [R/W]
- - - - - - 00
SDR0 [R/W]
00000000
SIO 0
000088H
SMCS1 [R/W]
00000010 - - - - 00 - 0
SES1 [R/W]
- - - - - - 00
SDR1 [R/W]
00000000
SIO 1
CDCR1 [R/W]
0 - - - 1111
Reserved
SIO 0/1
Prescaler
00008CH
CDCR0 [R/W]
0 - - - 1111
Reserved

000090H
Reserved
000094H
IBCR [R/W]
00000000
IBSR [R]
00000000
IADR [R/W]
-XXXXXXX
ICCR [R/W]
- - 0XXXXX
I2C (old)
000098H

IDAR [R/W]
XXXXXXXX

IDBL [R/W]
-------0
→ new I2C
from addr 0x184
00009CH
ADMD [R/W, W]
- - - X0000
ADCH [R/W]
00000000

ADCS [R/W, W]
0000 - - 00

ADBL [R/W]
-------0
0000A0H
0000A4H
0000A8H
0000ACH
ADCD [R/W]
000000XX XXXXXXXX

DACR [R/W]
- - - - - 000
DADR1 [R/W]
- - - - - - XX XXXXXXXX
IOTDBL0 [R/W]
- - - - - 000
ICS01 [R/W]
00000000
DADR0 [R/W]
- - - - - - XX XXXXXXXX

DDBL [R/W]
-------0
IOTDBL1 [R/W]
- - - - - 000
ICS23 [R/W]
00000000
0000B0H
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
0000B4H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
A/D Converter
DAC
Input Capture
0, 1, 2, 3
(Continued)
35
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
0000B8H
OCS0/1 [R/W]
- - - 0 - - 00 0000 - - 00
reserved
0000BCH
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
0000C0H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX

0000C4H
Block
Output Compare
0, 1, 2.3
Reserved
0000C8H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX

TCCS0 [R/W]
- 0000000
Free Running
Counter 0 for
ICU/OCU
0000CCH
TCDT1 [R/W]
XXXXXXXX XXXXXXXX

TCCS1 [R/W]
- 0000000
Free Running
Counter 1 for
ICU/OCU
0000D0H
ZPD0 [R/W]
00000010
PWC0 [R/W]
- - 000 - - 0
ZPD1 [R/W]
00000010
PWC1 [R/W]
00000 - - 0
SMC 0, 1
0000D4H
ZPD2 [R/W]
00000010
PWC2 [R/W]
- - 000 - - 0
ZPD3 [R/W]
00000010
PWC3 [R/W]
00000 - - 0
SMC 2, 3
0000D8H
PWC20 [R/W]
XXXXXXXX
PWC10 [R/W]
XXXXXXXX
PWS20 [R/W]
- 0000000
PWS10 [R/W]
- - 000000
SMC 0
0000DCH
PWC21 [R/W]
XXXXXXXX
PWC11 [R/W]
XXXXXXXX
PWS21 [R/W]
- 0000000
PWS11 [R/W]
- - 000000
SMC 1
0000E0H
PWC22 [R/W]
XXXXXXXX
PWC12 [R/W]
XXXXXXXX
PWS22 [R/W]
- 0000000
PWS12 [R/W]
- - 000000
SMC 2
0000E4H
PWC23 [R/W]
XXXXXXXX
PWC13 [R/W]
XXXXXXXX
PWS23 [R/W]
- 0000000
PWS13 [R/W]
- - 000000
SMC 3
0000E8H
SMDBL0 [R/W]
-------0
SMDBL1 [R/W]
------0
SMDBL2 [R/W]
-------0
SMDBL3 [R/W]
-------0
SMC 0, 1, 2, 3
0000ECH

SGDBL [R/W]
-------0
0000F0H
SGAR [R/W]
00000000
SGFR [R/W]
XXXXXXXX
0000F4H

WTDBL [R/W]
-------0
0000F8H

0000FCH
WTHR [R/W]
- - - 00000
000100H
000104H
SGCR [R, R/W]
0 - - - - - 00 000 - - 000
SGTR [R/W]
XXXXXXXX
SGDR [R/W]
XXXXXXXX
WTCR [R, R/W]
00000000 000 - 0000
WTBR [R/W]
- - XXXXXX XXXXXXXX XXXXXXXX
WTMR [R/W]
- - 000000
Sound
generator
WTSR [R/W]
- - 000000
Real Time Clock
(WatchTimer)

TMRLR3 [W]
XXXXXXXX XXXXXXXX
TMR3 [R]
XXXXXXXX XXXXXXXX

TMCSR3 [R/W]
- - - - XX - - - - - XXXXX
Reload Timer 3
(Continued)
36
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
Block
000108H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
TMR4 [R]
XXXXXXXX XXXXXXXX
00010CH

TMCSR4 [R/W]
- - - - XX - - - - - XXXXX
000110H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
TMR5 [R]
XXXXXXXX XXXXXXXX
000114H

TMCSR5 [R/W]
- - - - XX - - - - - XXXXX
000118H
GCN10 [R/W]
00110010 00010000
PDBL0 [R/W]
- - - 00000
GCN20 [R/W]
- - - - 0000
PWM Control 0
00011CH
GCN11 [R/W]
00110010 00010000
PDBL1 [R/W]
- - - 00000
GCN21 [R/W]
- - - - 0000
PWM Control 1
000120H
PTMR0 [R]
11111111 11111111
000124H
PDUT0 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR1 [R]
11111111 11111111
00012CH
PDUT1 [W]
XXXXXXXX XXXXXXXX
000130H
PTMR2 [R]
11111111 11111111
000134H
PDUT2 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR3 [R]
11111111 11111111
00013CH
PDUT3 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR4 [R]
11111111 11111111
000144H
PDUT4 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR5 [R]
11111111 11111111
00014CH
PDUT5 [W]
XXXXXXXX XXXXXXXX
000150H
PTMR6 [R]
11111111 11111111
000154H
PDUT 6 [W]
XXXXXXXX XXXXXXXX
PCSR0 [W]
XXXXXXXX XXXXXXXX
PCNH0 [R/W]
0000000 -
PCNL0 [R/W]
000000 - 0
PCSR1 [W]
XXXXXXXX XXXXXXXX
PCNH1 [R/W]
0000000 -
PCNL1 [R/W]
000000 - 0
PCSR2 [W]
XXXXXXXX XXXXXXXX
PCNH2 [R/W]
0000000 -
PCNL2 [R/W]
000000 - 0
PCSR3 [W]
XXXXXXXX XXXXXXXX
PCNH3 [R/W]
0000000 -
PCNL3 [R/W]
000000 - 0
PCSR4 [W]
XXXXXXXX XXXXXXXX
PCNH4 [R/W]
0000000 -
PCNL4 [R/W]
000000 - 0
PCSR5 [W]
XXXXXXXX XXXXXXXX
PCNH5 [R/W]
0000000 -
PCNL5 [R/W]
000000 - 0
PCSR6 [W]
XXXXXXXX XXXXXXXX
PCNH6 [R/W]
0000000 -
PCNL6 [R/W]
000000 - 0
Reload Timer 4
Reload Timer 5
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
(Continued)
37
MB91360G Series
(Continued)
Address
Register
+0
+1
000158H
PTMR7 [R]
11111111 11111111
00015CH
PDUT7 [W]
XXXXXXXX XXXXXXXX
+2
+3
PCSR7 [W]
XXXXXXXX XXXXXXXX
PCNH7 [R/W]
0000000 -
PCNL7 [R/W]
000000 - 0

000160H
Block
PWM7
Reserved
000164H
CMCR [R/W]
11111111 0000000
CMPR [R/W]
- - - -1001 1 - - -0001
000168H
CMLS0 [R/W]
01110111 1111111
CMLS1 [R/W]
01110111 1111111
00016CH
CMLS2 [R/W]
01110111 1111111
CMLS3 [R/W]
01110111 1111111
000170H
CMLT0 [R/W]
- - - - -100 00000010
CMLT1 [R/W]
11110100 00000010
000174H
CMLT2 [R/W]
- - - - -100 00000010
CMLT3 [R/W]
- - - - -100 00000010
000178H
CMAC [R/W]
11111111 1111111
CMTS [R/W]
- -000001 01111111
Clock Modulation
00017CH

PDRCR [R/W]
- - - - - 000


Power down reset
000180H
ACCDBL[R/W]
-------0
ACSR [R, R/W]
- - - XXX00


Alarm comparator
000184H
IBCR2 [R/W, W]
00000000
IBSR2 [R]
00000000
ITBAH [R/W]
- - - - - - 00
ITBAL [R/W]
00000000
000188H
ITMKH [R/W, W]
00 - - - - 11
ITMKL [R/W]
11111111
ISMK [R/W]
01111111
ISBA [R/W]
- 0000000
00018CH
IDARH [-]
00000000
IDAR2 [R/W]
00000000
ICCR2 [R/W]
- 0011111
IDBL2 (*) [R/W]
-------0
000190H
CUCR [R, R/W]
- - - - - - - - - - - 0 - -00
CUTD [R/W]
10000000 00000000
000194H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
000198H
to
0001F8H
0001FCH



I2C (new)
Calibration Unit of
32 kHz oscillator
Reserved
F362MD [R/W]
00000000
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX

F362GA
Mode Register
DMAC
* : Old and new I2C share this bit.
(Continued)
38
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH

000240H
DMACR [R/W]
00 - - 0000 - - - - - - - - - - - - - - - - - - - - - - - -
000244H
to
0002FCH

000300H
IRBS
00000000 00000001 00100000 - - - - - - - -
000304H
000308H
to
0003E0H
0003E4H
0003E8H
to
0003ECH
DMAC
Reserved
ISIZE [R/W]
- - - - - -11



Instruction Cache
Reserved
ICHRC
0-000000

Block
Instruction Cache
Reserved
(Continued)
39
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit Search
Module
000400H
DDRG [R/W]
00000000
DDRH [R/W]
00000000
DDRI [R/W]
- - - -0- - -
DDRJ [R/W]
00000000
000404H
DDRK [R/W]
00000000
DDRL [R/W]
00000000
DDRM [R/W]
- - - -0000
DDRN [R/W]
- -000000
000408H
DDRO [R/W]
00000000
DDRP [R/W]
- - - -0000
DDRQ [R/W]
- -000000
DDRR [R/W]
00000000
00040CH
DDRS [R/W]
00000000



000410H
PFRG [R/W]
00000000
PFRH [R/W]
00000000
PFRI [R/W]
- - - -0- - -
PFRJ [R/W]
00000000
000414H
PFRK [R/W]
00000000
PFRL [R/W]
00000000
PFRM [R/W]
- - - -0000
PFRN [R/W]
- -000000
000418H
PFRO [R/W]
00000000
PFRP [R/W]
00000000
PFRQ [R/W]
- -000000
PFRR [R/W]
00000000
00041CH
PFRS [R/W]
00000000



000420H
to
00043CH
Block

R-bus
Port Direction
Register
R-bus
Port Function
Register
Reserved
000440H
ICR00 [R, R/W]
- - -11111
ICR01 [R, R/W]
- - -11111
ICR02 [R, R/W]
- - -11111
ICR03 [R, R/W]
- - -11111
000444H
ICR04 [R, R/W]
- - -11111
ICR05 [R, R/W]
- - -11111
ICR06 [R, R/W]
- - -11111
ICR07 [R, R/W]
- - -11111
000448H
ICR08 [R, R/W]
- - -11111
ICR09 [R, R/W]
- - -11111
ICR10 [R, R/W]
- - -11111
ICR11 [R, R/W]
- - -11111
00044CH
ICR12 [R, R/W]
- - -11111
ICR13 [R, R/W]
- - -11111
ICR14 [R, R/W]
- - -11111
ICR15 [R, R/W]
- - -11111
000450H
ICR16 [R, R/W]
- - -11111
ICR17 [R, R/W]
- - -11111
ICR18 [R, R/W]
- - -11111
ICR19 [R, R/W]
- - -11111
000454H
ICR20 [R, R/W]
- - -11111
ICR21 [R, R/W]
- - -11111
ICR22 [R, R/W]
- - -11111
ICR23 [R, R/W]
- - -11111
000458H
ICR24 [R, R/W]
- - -11111
ICR25 [R, R/W]
- - -11111
ICR26 [R, R/W]
- - -11111
ICR27 [R, R/W]
- - -11111
Interrupt Control
unit
(Continued)
40
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
00045CH
ICR28 [R, R/W]
- - -11111
ICR29 [R, R/W]
- - -11111
ICR30 [R, R/W]
- - -11111
ICR31 [R, R/W]
- - -11111
000460H
ICR32 [R, R/W]
- - -11111
ICR33 [R, R/W]
- - -11111
ICR34 [R, R/W]
- - -11111
ICR35 [R, R/W]
- - -11111
000464H
ICR36 [R, R/W]
- - -11111
ICR37 [R, R/W]
- - -11111
ICR38 [R, R/W]
- - -11111
ICR39 [R, R/W]
- - -11111
000468H
ICR40 [R, R/W]
- - -11111
ICR41 [R, R/W]
- - -11111
ICR42 [R, R/W]
- - -11111
ICR43 [R, R/W]
- - -11111
00046CH
ICR44 [R, R/W]
- - -11111
ICR45 [R, R/W]
- - -11111
ICR46 [R, R/W]
- - -11111
ICR47 [R, R/W]
- - -11111
000470H
to
00047CH

RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
X0000X00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
00000000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000





000604H



DDR7 [R/W]
00000000
000608H
DDR8 [R/W]
00000000
DDR9 [R/W]
00000000

DDRB [R/W]
00000000
T-unit
Port Direction
Register

00060CH
000610H




000614H



PFR7 [R/W]
00001111
000618H
PFR8 [R/W]
111110-0
PFR9 [R/W]
11110101

PFRB [R/W]
00000000
00061CH

000620H

000628H
to
00063FH
Clock Control unit
Reserved
000600H
000624H
Interrupt Control
unit
Reserved
000480H
000488H
to
0005FCH
Block
T-unit
Port Function
Register
PFR27 [R/W]
1111-00-


Reserved
(Continued)
41
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
000640H
ASR0 [W]
00000000 00000000
AMR0 [W]
11111000 11111111
000644H
ASR1 [W]
00000000 00000000
AMR1 [W]
00000000 00000000
000648H
ASR2 [W]
00000000 00000000
AMR2 [W]
00000000 00000000
00064CH
ASR3 [W]
00000000 00000000
AMR3 [W]
00000000 00000000
000650H
ASR4 [W]
00000000 00000000
AMR4 [W]
00000000 00000000
000654H
ASR5 [W]
00000000 00000000
AMR5 [W]
00000000 00000000
000658H
ASR6 [W]
00000000 00000000
AMR6 [W]
00000000 00000000
00065CH
ASR7 [W]
00000000 00000000
AMR7 [W]
00000000 00000000
000660H
AMD0 [R/W]
-00XX111
AMD1 [R/W]
-XXXXXXX
AMD2 [R/W]
- -XXXXXX
AMD3 [R/W]
- -XXXXXX
000664H
AMD4 [R/W]
- -XXXXXX
AMD5 [R/W]
- -XXXXXX
AMD6 [R/W]
-XXXXXXX
AMD7 [R/W]
-XXXXXXX
000668H
CSE [R/W]
11000011




00066CH
000670H
CHE [R/W]
11111111




T-unit

000674H
to
0007F8H
0007FCH
Block
MODR [W]
XXXXXXXX
000800H
to
000AFCH
Reserved



Mode Register
Reserved
000B00H
ESTS0
X0000000
ESTS1
XXXXXXXX
ESTS2
XXXXXXXX

000B04H
ECTL0
0X000000
ECTL1
00000000
ECTL2
000X0000
ECTL3
00000X11
000B08H
ECNT0
XXXXXXXX
ECNT1
XXXXXXXX
EUSA
XXX0000X
EDTC
0000XXXX
DSU
(Continued)
42
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
000B0CH
EWPT
XXXXXXXX XXXXXXXX

000B10H
EDTR0
XXXXXXXX XXXXXXXX
EDTR1
XXXXXXXX XXXXXXXX
000B14H
to
000B1CH

000B20H
EIA0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B24H
EIA1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B28H
EIA2
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B2CH
EIA3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B30H
EIA4
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B34H
EIA5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B38H
EIA6
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B3CH
EIA7
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B40H
EDTA
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B44H
EDTM
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B48H
EOA0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B4CH
EOA1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B50H
EPCR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B54H
EPSR
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B58H
EIAM0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B5CH
EIAM1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B60H
EOAM0/EODM0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
DSU
(Continued)
43
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
Block
000B64H
EOAM1/EODM1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B68H
EOD0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B6CH
EOD1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
003FFCH

Reserved
004000H
to
006FFFH

Reserved
DSU
DMAC
007000H
FMCS [R/W]
1110X000



007004H
FMWT [R/W]
- -000011



007008H
to
00FFFCH

Flash Memory
Control
Register
on F362GA/
FV360GA
Reserved
(Continued)
44
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
Block
010000H
to
010FFCH
(for exact address range see “■ PERIPHERAL RESOURCES
1. INSTRUCTION CACHE”)
on F361GA only 1 K Cache is available,
on F362GA no cache, but 4 K I-RAM are available
I-Cache 4 KB
011000H
to
011FFCH

Reserved
012000H
to
01FFFCH

Reserved
020000H
to
03BFFCH

Reserved
03C000H
to
03FFFCH
Only first 12 KB are available on F362GA and F361GA
User RAM
16 KB
(D-Bus)
040000H
to
043FFCH
Only first 4 K are available on F362GA and F361GA
Fast RAM
16 KB
(F-Bus)
044000H
to
0FEFFC

Reserved
050000H
to
0507FCH

Boot ROM
2 KB
(F-Bus)
050800H
to
07FFF4H

reserved
080000H
to
09FFFCH
Sector 0
64 KB
Sector 7
64 KB
0A0000H
to
0BFFFC
Sector 1
64 KB
Sector 8
64 KB
0C0000H
to
0DFFFC
Sector 2
64 KB
Sector 9
64 KB
0E0000H
to
0EFFFC
Sector 3
32 KB
Sector 10
32 KB
0F0000H
to
0F3FFCH
Sector 4
8 KB
Sector 11
8 KB
Flash Memory
512 K
on F-Bus on
FV360GA and
F362GA
(Continued)
45
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
Block
0F4000H
to
0F7FFCH
Sector 5
8 KB
Sector 12
8 KB
Flash Memory
512 K
0F8000H
to
0FFFF4H
Sector 6
16 KB
Sector 13
16 KB
on F-Bus on
FV360GA and
F362GA
0FFFF8H
FMV [R]
06 00 00 00H
0FFFFCH
FRV [R]
00 05 00 00H on FV360GA/F362GA / 00 FF 00 00 on F361GA
Fixed
Reset/Mode
Vector
Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values
shown above will be read.
(Continued)
46
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
100000H
BVALR0 [R/W]
00000000 00000000
TREQR0 [R/W]
00000000 00000000
100004H
TCANR0 [W]
00000000 00000000
TCR0 [R/W]
00000000 00000000
100008H
RCR0 [R/W]
00000000 00000000
RRTRR0 [R/W]
00000000 00000000
10000CH
ROVRR0 [R/W]
00000000 00000000
RIER0 [R/W]
00000000 00000000
100010H
CSR0 [R/W, R]
00000000 00000001

100014H
RTEC0 [R]
00000000 00000000
BTR0 [R/W]
-1111111 11111111
100018H
IDER0 [R/W]
XXXXXXXX XXXXXXXX
TRTRR0 [R/W]
00000000 00000000
10001CH
RFWTR0 [R/W]
XXXXXXXX XXXXXXXX
TIER0 [R/W]
00000000 00000000
Block
LEIR0 [R/W]
000-0000
100020H
AMSR0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100024H
AMR00 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100028H
AMR10 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10002CH
to
10004BH
GENERAL PURPOSE RAM [R/W]
10004CH
IDR00 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100050H
IDR10 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100054H
IDR20 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100058H
IDR30 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10005CH
IDR40 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100060H
IDR50 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100064H
IDR60 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100068H
IDR70 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
CAN 0
Remark :
Address range for
CAN 0 to CAN 3
depends on chip
select range.
Mentioned
addresses are
default values,
determined by
boot ROM
contents.
(Continued)
47
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
10006CH
IDR80 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100070H
IDR90 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100074H
IDR100 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100078H
IDR110 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10007CH
IDR120 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100080H
IDR130 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100084H
IDR140 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100088H
IDR150 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
+3
10008CH
DLCR00 [R/W]
- - - - - - - - - - - - XXXX
DLCR10 [R/W]
- - - - - - - - - - - - XXXX
100090H
DLCR20 [R/W]
- - - - - - - - - - - - XXXX
DLCR30 [R/W]
- - - - - - - - - - - - XXXX
100094H
DLCR40 [R/W]
- - - - - - - - - - - - XXXX
DLCR50 [R/W]
- - - - - - - - - - - - XXXX
100098H
DLCR60 [R/W]
- - - - - - - - - - - - XXXX
DLCR70 [R/W]
- - - - - - - - - - - - XXXX
10009CH
DLCR80 [R/W]
- - - - - - - - - - - - XXXX
DLCR90 [R/W]
- - - - - - - - - - - - XXXX
1000A0H
DLCR100 [R/W]
- - - - - - - - - - - - XXXX
DLCR110 [R/W]
- - - - - - - - - - - - XXXX
1000A4H
DLCR120 [R/W]
- - - - - - - - - - - - XXXX
DLCR130 [R/W]
- - - - - - - - - - - - XXXX
1000A8H
DLCR140 [R/W]
- - - - - - - - - - - - XXXX
DLCR150 [R/W]
- - - - - - - - - - - - XXXX
1000ACH
DTR00 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000B4H
DTR10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000BCH
DTR20 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
CAN 0
(Continued)
48
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
1000C4H
DTR30 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000CCH
DTR40 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000D4H
DTR50 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000DCH
DTR60 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000E4H
DTR70 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000ECH
DTR80 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000F4H
DTR90 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1000FCH
DTR100 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100104H
DTR110 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10010CH
DTR120 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100114H
DTR130 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10011CH
DTR140 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100124H
DTR150 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10012CH
CREG0 [R/W]
00000000 00000110
Block
CAN 0

(Continued)
49
MB91360G Series
(Continued)
Address
100180H
Register
+0
+1
FMCS [R/W]
1 - - 0X000
+2
+3
Block
Flash Memory
control for
F361GA
------------------------
100200H
BVALR1 [R/W]
00000000 00000000
TREQR1 [R/W]
00000000 00000000
100204H
TCANR1 [W]
00000000 00000000
TCR1 [R/W]
00000000 00000000
100208H
RCR1 [R/W]
00000000 00000000
RRTRR1 [R/W]
00000000 00000000
10020CH
ROVRR1 [R/W]
00000000 00000000
RIER1 [R/W]
00000000 00000000
100210H
CSR1 [R/W]
00000000 00000001

100214H
RTEC1 [R]
00000000 00000000
BTR1 [R/W]
-1111111 11111111
100218H
IDER1 [R/W]
XXXXXXXX XXXXXXXX
TRTRR1 [R/W]
00000000 00000000
10021CH
RFWTR1 [R/W]
XXXXXXXX XXXXXXXX
TIER1 [R/W]
00000000 00000000
LEIR1 [R/W]
000-0000
100220H
AMSR1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100224H
AMR01 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100228H
AMR11 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10022CH
to
100248H
GENERAL PURPOSE RAM [R/W]
10024CH
IDR01 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100250H
IDR11 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100254H
IDR21[R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100258H
IDR31 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX-
10025CH
IDR41 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100260H
IDR51 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
CAN 1
Remark :
Address range for
CAN 0 to CAN 3
depends on chip
select range.
Mentioned
addresses are
default values,
determined by
boot ROM
contents.
(Continued)
50
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
100264H
IDR61 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100268H
IDR71 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10026CH
IDR81 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100270H
IDR91 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100274H
IDR101 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100278H
IDR111 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10027CH
IDR121 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - -
100280H
IDR131 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100284H
IDR141 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100288H
IDR151 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
+3
10028CH
DLCR01 [R/W]
- - - - - - - - - - - - XXXX
DLCR11 [R/W]
- - - - - - - - - - - - XXXX
100290H
DLCR21 [R/W]
- - - - - - - - - - - - XXXX
DLCR31 [R/W]
- - - - - - - - - - - - XXXX
100294H
DLCR41 [R/W]
- - - - - - - - - - - - XXXX
DLCR51 [R/W]
- - - - - - - - - - - - XXXX
100298H
DLCR61 [R/W]
- - - - - - - - - - - - XXXX
DLCR71 [R/W]
- - - - - - - - - - - - XXXX
10029CH
DLCR81[R/W]
- - - - - - - - - - - - XXXX
DLCR91 [R/W]
- - - - - - - - - - - - XXXX
1002A0H
DLCR101 [R/W]
- - - - - - - - - - - - XXXX
DLCR111 [R/W]
- - - - - - - - - - - - XXXX
1002A4H
DLCR121 [R/W]
- - - - - - - - - - - - XXXX
DLCR131 [R/W]
- - - - - - - - - - - - XXXX
1002A8H
DLCR141 [R/W]
- - - - - - - - - - - - XXXX
DLCR151 [R/W]
- - - - - - - - - - - - XXXX
1002ACH
Block
CAN 1
DTR01 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
51
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
1002B4H
DTR11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002BCH
DTR21 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002C4H
DTR31 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002CCH
DTR41 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002D4H
DTR51 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002DCH
DTR61 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002E4H
DTR71 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002ECH
DTR81 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002F4H
DTR91 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1002FCH
DTR101 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100304H
DTR111 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10030CH
DTR121 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100314H
DTR131 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10031CH
DTR141 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
CAN 1
(Continued)
52
MB91360G Series
(Continued)
Address
100324H
Register
+0
+1
+2
+3
DTR151 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10032CH
CREG1 [R/W]
00000000 00000110

100400H
BVALR2 [R/W]
00000000 00000000
TREQR2 [R/W]
00000000 00000000
100404H
TCANR2 [W]
00000000 00000000
TCR2 [R/W]
00000000 00000000
100408H
RCR2 [R/W]
00000000 00000000
RRTRR1 [R/W]
00000000 00000000
10040CH
ROVRR2 [R/W]
00000000 00000000
RIER2 [R/W]
00000000 00000000
100410H
CSR2 [R/W]
00000000 00000001

100414H
RTEC2 [R]
00000000 00000000
BTR2 [R/W]
-1111111 11111111
100418H
IDER2 [R/W]
XXXXXXXX XXXXXXXX
TRTRR2 [R/W]
00000000 00000000
10041CH
RFWTR2 [R/W]
XXXXXXXX XXXXXXXX
TIER2 [R/W]
00000000 00000000
Block
CAN 1
LEIR2 [R/W]
000-0000
100420H
AMSR2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100424H
AMR02 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100428H
AMR12 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10042CH
to
100448H
GENERAL PURPOSE RAM [R/W]
10044CH
IDR02 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100450H
IDR12 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100454H
IDR22[R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100458H
IDR32 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX-
10045CH
IDR42 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
CAN 2
Remark :
Address range for
CAN 0 to CAN 3
depends on chip
select range.
Mentioned
addresses are
default values,
determined by
boot ROM
contents.
(Continued)
53
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
100460H
IDR52 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100464H
IDR62 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100468H
IDR72 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10046CH
IDR82 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100470H
IDR92 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100474H
IDR102 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100478H
IDR112 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10047CH
IDR122 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - -
100480H
IDR132 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100484H
IDR142 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100488H
IDR152 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
+3
10048CH
DLCR02 [R/W]
- - - - - - - - - - - - XXXX
DLCR12 [R/W]
- - - - - - - - - - - - XXXX
100490H
DLCR22 [R/W]
- - - - - - - - - - - - XXXX
DLCR32 [R/W]
- - - - - - - - - - - - XXXX
100494H
DLCR42 [R/W]
- - - - - - - - - - - - XXXX
DLCR52 [R/W]
- - - - - - - - - - - - XXXX
100498H
DLCR62 [R/W]
- - - - - - - - - - - - XXXX
DLCR72 [R/W]
- - - - - - - - - - - - XXXX
10049CH
DLCR82[R/W]
- - - - - - - - - - - - XXXX
DLCR92 [R/W]
- - - - - - - - - - - - XXXX
1004A0H
DLCR102 [R/W]
- - - - - - - - - - - - XXXX
DLCR112 [R/W]
- - - - - - - - - - - - XXXX
1004A4H
DLCR122 [R/W]
- - - - - - - - - - - - XXXX
DLCR132 [R/W]
- - - - - - - - - - - - XXXX
1004A8H
DLCR142 [R/W]
- - - - - - - - - - - - XXXX
DLCR152 [R/W]
- - - - - - - - - - - - XXXX
1004ACH
Block
CAN 2
DTR02 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
54
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
1004ACH
DTR02 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004B4H
DTR12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004BCH
DTR22 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004C4H
DTR32 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004CCH
DTR42 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004D4H
DTR52 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004DCH
DTR62 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004E4H
DTR72 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004ECH
DTR82 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004F4H
DTR92 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1004FCH
DTR102 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100504H
DTR112 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10050CH
DTR122 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100514H
DTR132 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
CAN 2
(Continued)
55
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
+3
10051CH
DTR142 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100524H
DTR152 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10052CH
CREG2 [R/W]
00000000 00000110

100600H
BVALR3 [R/W]
00000000 00000000
TREQR3 [R/W]
00000000 00000000
100604H
TCANR3 [W]
00000000 00000000
TCR3 [R/W]
00000000 00000000
100608H
RCR3 [R/W]
00000000 00000000
RRTRR31 [R/W]
00000000 00000000
10060CH
ROVRR3 [R/W]
00000000 00000000
RIER3 [R/W]
00000000 00000000
100610H
CSR3 [R/W]
00000000 00000001

100614H
RTEC3 [R]
00000000 00000000
BTR3 [R/W]
-1111111 11111111
100618H
IDER3 [R/W]
XXXXXXXX XXXXXXXX
TRTRR3 [R/W]
00000000 00000000
10061CH
RFWTR3 [R/W]
XXXXXXXX XXXXXXXX
TIER3 [R/W]
00000000 00000000
Block
CAN 2
LEIR3 [R/W]
000-0000
100620H
AMSR3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100624H
AMR03 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100628H
AMR13 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10062CH
to
100648H
GENERAL PURPOSE RAM [R/W]
10064CH
IDR03 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100650H
IDR13 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100654H
IDR23[R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100658H
IDR33 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX-
CAN 3
Remark :
Address range for
CAN 0 to CAN 3
depends on chip
select range.
Mentioned
addresses are
default values,
determined by
boot ROM
contents.
(Continued)
56
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
10065CH
IDR43 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100660H
IDR53 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100664H
IDR63 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100668H
IDR73 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10066CH
IDR83 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100670H
IDR93 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100674H
IDR103 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100678H
IDR113 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
10067CH
IDR123 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXX - - -
100680H
IDR133 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100684H
IDR143 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
100688H
IDR153 [R/W]
XXXXXXXX XXXXXXXX XXXXX - - - XXXXXXXX
+3
10068CH
DLCR032 [R/W]
- - - - - - - - - - - - XXXX
DLCR13 [R/W]
- - - - - - - - - - - - XXXX
100690H
DLCR232 [R/W]
- - - - - - - - - - - - XXXX
DLCR33 [R/W]
- - - - - - - - - - - - XXXX
100694H
DLCR43 [R/W]
- - - - - - - - - - - - XXXX
DLCR53 [R/W]
- - - - - - - - - - - - XXXX
100698H
DLCR63 [R/W]
- - - - - - - - - - - - XXXX
DLCR733 [R/W]
- - - - - - - - - - - - XXXX
10069CH
DLCR83[R/W]
- - - - - - - - - - - - XXXX
DLCR93 [R/W]
- - - - - - - - - - - - XXXX
1006A0H
DLCR103 [R/W]
- - - - - - - - - - - - XXXX
DLCR113 [R/W]
- - - - - - - - - - - - XXXX
1006A4H
DLCR123 [R/W]
- - - - - - - - - - - - XXXX
DLCR133 [R/W]
- - - - - - - - - - - - XXXX
1006A8H
DLCR143 [R/W]
- - - - - - - - - - - - XXXX
DLCR153 [R/W]
- - - - - - - - - - - - XXXX
Block
CAN 3
(Continued)
57
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
1006ACH
DTR03 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006B4H
DTR13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006BCH
DTR23 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006C4H
DTR33 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006CCH
DTR43 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006D4H
DTR53 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006DCH
DTR63 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006E4H
DTR73 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006ECH
DTR83 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006F4H
DTR93 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
1006FCH
DTR103 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100704H
DTR113 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10070CH
DTR123 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100714H
DTR133 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
CAN 3
(Continued)
58
MB91360G Series
(Continued)
Address
Register
+0
+1
+2
Block
+3
10071CH
DTR143 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
100724H
DTR153 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10072CH
CREG3 [R/W]
00000000 00000110

180000H
to
19FFFCH
Sector 0
64 KB
Sector 7
64 KB
1A0000H
to
1BFFFC
Sector 1
64 KB
Sector 8
64 KB
1C0000H
to
1DFFFC
Sector 2
64 KB
Sector 9
64 KB
1E0000H
to
1 EFFFCH
Sector 3
32 KB
Sector 10
32 KB
1F0000H
to
1F3FFCH
Sector 4
8 KB
Sector 11
8 KB
1F4000H
to
1F7FFCH
Sector 5
8 KB
Sector 12
8 KB
1F8000H
to
1FFFFCH
Sector 6
16 KB
Sector 13
16 KB
CAN 3
Flash Memory
512 K on F361GA
- addresses
depending on
settings for ship
select area CS1
Note: The data in reserved areas and areas marked “” is indeterminate. Do not use those areas!
59
MB91360G Series
■ INTERRUPT CAUSES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTER
Interrupt number
Interrupt
Interrupt level *1
Interrupt vector *2
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
RN
Reset
0
00


0x3FC
0x000FFFFC

Mode vector
1
01


0x3F8
0x000FFFF8

System reserved
2
02


0x3F4
0x000FFFF4

System reserved
3
03


0x3F0
0x000FFFF0

System reserved
4
04


0x3EC
0x000FFFEC

System reserved
5
05


0x3E8
0x000FFFE8

6
06


0x3E4
0x000FFFE4

7
07


0x3E0
0x000FFFE0

Co-processor error trap *4
8
08


0x3DC
0x000FFFDC

INTE instruction *4
9
09


0x3D8
0x000FFFD8

Instruction break
exception *4
10
0A


0x3D4
0x000FFFD4

Operand break trap *4
11
0B


0x3D0
0x000FFFD0

Step trace trap *4
12
0C


0x3CC
0x000FFFCC

NMI interrupt (tool) *4
13
0D


0x3C8
0x000FFFC8

Undefined instruction
exception
14
0E


0x3C4
0x000FFFC4

NMI request
15
0F
0x3C0
0x000FFFC0

External Interrupt 0
16
10
ICR00
0x440
0x3BC
0x000FFFBC
4
External Interrupt 1
17
11
ICR01
0x441
0x3B8
0x000FFFB8
5
External Interrupt 2
18
12
ICR02
0x442
0x3B4
0x000FFFB4
8
External Interrupt 3
19
13
ICR03
0x443
0x3B0
0x000FFFB0
9
External Interrupt 4
20
14
ICR04
0x444
0x3AC
0x000FFFAC

External Interrupt 5
21
15
ICR05
0x445
0x3A8
0x000FFFA8

External Interrupt 6
22
16
ICR06
0x446
0x3A4
0x000FFFA4

External Interrupt 7
23
17
ICR07
0x447
0x3A0
0x000FFFA0

Reload Timer 0
24
18
ICR08
0x448
0x39C
0x000FFF9C
6
Reload Timer 1
25
19
ICR09
0x449
0x398
0x000FFF98
7
Reload Timer 2
26
1A
ICR10
0x44A
0x394
0x000FFF94

CAN 0 RX
27
1B
ICR11
0x44B
0x390
0x000FFF90

CAN 0 TX/NS
28
1C
ICR12
0x44C
0x38C
0x000FFF8C

CAN 1 RX
29
1D
ICR13
0x44D
0x388
0x000FFF88

CAN 1 TX/NS
30
1E
ICR14
0x44E
0x384
0x000FFF84

System reserved
Co-processor fault trap
*4
FH fixed
(Continued)
60
MB91360G Series
(Continued)
Interrupt number
Interrupt
Interrupt level *1
Interrupt vector *2
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
RN
CAN 2 RX
31
1F
ICR15
0x44F
0x380
0x000FFF80

CAN 2 TX/NS
32
20
ICR16
0x450
0x37C
0x000FFF7C

33
21
ICR17
0x451
0x378
0x000FFF78

34
22
ICR18
0x452
0x374
0x000FFF74

PPG 0/1
35
23
ICR19
0x453
0x370
0x000FFF70

PPG 2/3
36
24
ICR20
0x454
0x36C
0x000FFF6C

PPG 4/5
37
25
ICR21
0x455
0x368
0x000FFF68

PPG 6/7
38
26
ICR22
0x456
0x364
0x000FFF64

Reload Timer 3
39
27
ICR23
0x457
0x360
0x000FFF60

Reload Timer 4
40
28
ICR24
0x458
0x35C
0x000FFF5C

Reload Timer 5
41
29
ICR25
0x459
0x358
0x000FFF58

ICU 0/1
42
2A
ICR26
0x45A
0x354
0x000FFF54

OCU 0/1
43
2B
ICR27
0x45B
0x350
0x000FFF50

ICU 2/3
44
2C
ICR28
0x45C
0x34C
0x000FFF4C

OCU 2/3
45
2D
ICR29
0x45D
0x348
0x000FFF48

ADC
46
2E
ICR30
0x45E
0x344
0x000FFF44
14
Timebase Overflow
47
2F
ICR31
0x45F
0x340
0x000FFF40

Free Running Counter 0
48
30
ICR32
0x460
0x33C
0x000FFF3C

Free Running Counter 1
CAN 3 RX *5
CAN 3 TX/NS
*5
49
31
ICR33
0x461
0x338
0x000FFF38

SIO 0
*6
50
32
ICR34
0x462
0x334
0x000FFF34
(12)
SIO 1
*6
51
33
ICR35
0x463
0x330
0x000FFF30
(15)
Sound Generator
52
34
ICR36
0x464
0x32C
0x000FFF2C

UART 0 RX
53
35
ICR37
0x465
0x328
0x000FFF28
0
UART 0 TX
54
36
ICR38
0x466
0x324
0x000FFF24
1
UART 1 RX
55
37
ICR39
0x467
0x320
0x000FFF20
2
UART 1 TX
56
38
ICR40
0x468
0x31C
0x000FFF1C
3
UART 2 RX
57
39
ICR41
0x469
0x318
0x000FFF18
10
UART 2 TX
58
3A
ICR42
0x46A
0x314
0x000FFF14
11
I2C
59
3B
ICR43
0x46B
0x310
0x000FFF10
13
Alarm Comparator
60
3C
ICR44
0x46C
0x30C
0x000FFF0C

RTC (Watchtimer) /
Calibration Unit
61
3D
ICR45
0x46D
0x308
0x000FFF08

DMA
62
3E
ICR46
0x46E
0x304
0x000FFF04

(Continued)
61
MB91360G Series
(Continued)
Interrupt number
Interrupt
Interrupt level *1
Interrupt vector *2
RN
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
63
3F
ICR47
0x46F
0x300
0x000FFF00
System reserved *3
64
40


0x2FC
0x000FFEFC

*3
65
41


0x2F8
0x000FFEF8

Security vector
66
42


0x2F4
0x000FFEF4

System reserved
67
43
(ICR51)
0x473
0x2F0
0x000FFEF0

System reserved
68
44
(ICR52)
0x474
0x2EC
0x000FFEEC

System reserved
69
45
(ICR53)
0x475
0x2E8
0x000FFEE8

System reserved
70
46
(ICR54)
0x476
0x2E4
0x000FFEE4

System reserved
71
47
(ICR55)
0x477
0x2E0
0x000FFEE0

System reserved
72
48
(ICR56)
0x478
0x2DC
0x000FFEDC

System reserved
73
49
(ICR57)
0x479
0x2D8
0x000FFED8

System reserved
74
4A
(ICR58)
0x47A
0x2D4
0x000FFED4

System reserved
75
4B
(ICR59)
0x47B
0x2D0
0x000FFED0

System reserved
76
4C
(ICR60)
0x47C
0x2CC
0x000FFECC

System reserved
77
4D
(ICR61)
0x47D
0x2C8
0x000FFEC8

System reserved
78
4E
(ICR62)
0x47E
0x2C4
0x000FFEC4

System reserved
79
4F
(ICR63)
0x47F
0x2C0
0x000FFEC0

Used by the INT
instruction.
80
to
255
50
to
FF

0x2BC
to
0x000
0x000FFEBC
to
0x000FFC00
Delayed interrupt
activation bit
System reserved






*1 : The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is
provided for each interrupt request.
*2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table
base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table
are for the default TBR value (0x000FFC00) . The TBR is initialized to this value by a reset.After execution of
the internal boot ROM TBR is set to 0x00FFC00.
*3 : Used by REALOS
*4 : System reserved
*5 : Only available on MB91FV360GA
*6 : DMA to/from SIO is not yet implemented.
62
MB91360G Series
■ PERIPHERAL RESOURCES
1. INSTRUCTION CACHE
This section describes the instruction cache memory included in FR50 Family members and it operation. This
only applies to MB91FV360GA and MB91F361GA.
(1) General Description
The instruction cache is temporary memory. When an external low-speed memory accesses an instruction code,
the instruction cache stores the single-accessed code to increase the second and subsequent access
speeds.Setting this memory to the RAM mode enables software to directly read and write instruction cache data
RAM and tag RAM.
(2) Main Body Structure
• FR basic instruction length : 2 bytes
• Block arrangement system : 2-way set associative system
• Block
One way consists of 128 blocks.
One block consists of 16 bytes ( = 4 sub-blocks) .
One sub-block consists of 4 bytes ( = 1 bus access unit) .
4 bytes
4 bytes
4 bytes
4 bytes
4 bytes
I3
I2
I1
I0
Way 1
Cache tag
Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0
Block 0
Cache tag
Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0
Block 127
Cache tag
Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0
Block 0
Cache tag
Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0
Block 127
128 blocks
Way 2
128 blocks
Instruction Cache Structure
63
MB91360G Series
Way 1
31
09
Address tag
07
SBV3
08
Reserved
06
SBV2
05
ABV1
04
SBV0
Sub-block valid
LRU
Entry lock
03
TAGV
02
Reserved
01
LRU
00
ETLK
TAG valid
Way 2
31
09
Address tag
07
SBV3
Reserved
06
SBV2
Sub-block valid
05
ABV1
04
SBV0
03
TAGV
TAG valid
Entry lock
Instruction Cache Tag
64
08
02
Reserved
01
00
ETLK
MB91360G Series
(3) Control Register Structure
IRBS (32 bits)
Address : 00000300H
Address : 00000302H
Initial value
00000000B
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
1
Initial value
00000001B
R
R
R
R
R
R
R
R
ICR26
Initial value
0010 - - - -B
15
14
13
12
11
10
9
8
IRBS
IRBS
IRBS
IRBS




R/W
R/W
R/W
R/W




7
6
5
4
3
2
1
0
















Initial value
--------B
IRBS [bits 15 to 12] These bits are used to set the base address of cache RAM at access in the RAM mode.
Align cache RAM in units of 4 K bytes. These bits are initialized by INIT. The initial value is the 00012000H
address.
ISIZE (8 bits)
00000307H
Initial value
7
6
5
4
3
2
1
0






SIZE1
SIZE0






R/W
R/W
- - - - - - 11B
The ICHCR (I-CacHe Control Register) controls the instruction cache operations.
Writing to the ICHCR does not affect caching of instructions fetched within three subsequent cycles.
ICHCR (8 bits)
Initial value
000003E7H
7
6
5
4
3
2
1
0
RAM

GBLK
ALFL
EOLK
ELKR
FLSH
ENAB
R/W

R/W
R/W
R/W
R/W
R/W
R/W
0 - 000000B
65
MB91360G Series
2. BOOT ROM
The Boot ROM is a fixed start-up routine which is located at FF000 (Reset entry) and will therefore be executed
after every RST or INIT. The purpose of this ROM is to configure the device after a reset and to provide a simple
serial bootloader for programming the embedded Flash memories.
The Boot ROM contains three logical parts :
(1) Chip Initializations
Immediately after each reset, the following settings will be made :
CS0 : 200000…2FFFFF, 32 Bit Bus, 1 wait-state (default external access)
CS1 : 180000…1FFFFF, 32 Bit Bus, 1 wait-state (Flash Area only on F361GA)
CS7 : 100000…10FFFF, 16 Bit Bus, 1 wait-state (CAN)
In addition, the Table-Base Register will be initialized to 1FFC00 (F361GA only) and the synchronous reset (see
TBCR) will be enabled.
(2) Check for Bootcondition
After the chip initialization, the “Security-Vector” will be checked (Vector #66) . The purpose of this feature is to
disable the bootstraploader due to security reasons.
The RSRR (reset cause register) will be read and saved. If no power-on reset (external INIT input, RSRR =
0x80) is indicated, a branch to the user application will be initiated (Branch to 1F4000) .
If INIT was detected and the “Security-Vector” check okay, the following conditions must be met in order to start
the Bootstraploader :
Within a certain time, the start-up character “V” must be received via UART0 (9600, 8N1) . The time-out is set
to 200 ms.
(3) Bootstraploader
If the Bootcondition was met, an acknowledge character “F” will be transmitted via UART0 to indicate that the
Bootloader is ready to accept commands. 4 different commands are possible :
Receive and write to a specified memory block
Dump the contents of a specified memory block
Initiate a “CALL” to a certain location
Re-dump a calculated checksum for verification
(4) Configuration Register (Mode Register F362MD)
This register is used to control which pins of the external bus interface are active, where the pins for the external
DMA channel are located and which I2C module is used.
address
000001FEH
access
Initial value
66
bit 15

bit 14
bit 13
ASYMCLKT HIZ_D_A
R/W
0
R/W
0
bit 12
bit 11
bit 10
bit 9
HIZ_ECLK HIZ_D_23_16 HIZ_D_15_0 DMASWP
R/W
0
R/W
0
R/W
0
R/W
0
bit 8
IICSEL
R/W
0
MB91360G Series
3. CLOCK MODULATOR
An important property of MCUs and other electronic devices is their electromagnetic compatibility - EMC. Besides
a low susceptibility against external interferences, a low radiated emission is desired to avoid interference of
adjacent devices.
Particularly the system clock and derived signals such as data- and address busses contribute significantly to
the radiated emission. The purpose of the clock modulator is to spread the energy of these signals over a wide
range of frequencies and thus reducing the amplitudes of the fundamental and harmonic frequencies.
With the use of an advanced frequency modulation algorithm, the Fujitsu built in clock modulator can achieve
an attenuation of up to 20-25 dB compared to non modulated clock operation. Since the modulator is highly
configurable, it can be optimally adjusted to the actual application in order to achieve minimal electromagnetic
interference.
By default, the modulator is disabled and the MCU is running with unmodulated clock.
If you plan to use this feature, please contact Fujitsu.
67
MB91360G Series
4. I/O PORTS
There are 3 types of I/O port register structure; port data register (PDR7 to PDR5) , data direction register (DDR7
to DDR5) , and portfunction registers (PFR7 to PRF5) , where bits PDR7 to PDR5, bits DDR7 to DDR5, and
bits PFR7 to PRF5 correspond respectively. Each bit on the register corresponds to an external pin. The PFR
settings define whether a pin is used as a functional I/O (e.g. UART output) or as general purpose pin.
• For input (DDR = “0”) setting;
PDR reading operation : reads level of corresponding external pin.
PDR writing operation : writes set value to PDR.
• For output (DDR = “1”) setting;
PDR reading operation : reads PDR value.
PDR writing operation : outputs PDR value to corresponding external pin.
68
MB91360G Series
(1) Register configuration
Port Data Register
bit 7
bit 0 Initial value Access
Address : 00000007H
PDR7
111XXXXXB
R/W
00000008H
PDR8
XXXXXXXXB
R/W
00000009H
PDR9
XXXXXXX1B
R/W
0000000BH
PDRB
XXXXXXXXB
R/W
00000010H
PDRG
XXXXXXXXB
R/W
00000011H
PDRH
XXXXXXXXB
R/W
00000012H
PDRI
X - - - X - - -B
R/W
00000013H
PDRJ
XXXXXXXXB
R/W
00000014H
PDRK
XXXXXXXXB
R/W
00000015H
PDRL
XXXXXXXXB
R/W
00000016H
PDRM
- - - - XXXXB
R/W
00000017H
PDRN
- -XXXXXXB
R/W
00000018H
PDRO
XXXXXXXXB
R/W
00000019H
PDRP
XXXXXXXXB
R/W
0000001AH
PDRQ
--XXXXXXB
R/W
0000001BH
PDRR
XXXXXXXXB
R/W
0000001CH
PDRS
XXXXXXXXB
R/W
69
MB91360G Series
Data directon Register
bit 7
70
bit 0 Initial value Access
Address : 00000607H
DDR7
00000000B
R/W
00000608H
DDR8
00000000B
R/W
00000609H
DDR9
00000000B
R/W
0000060BH
DDRB
00000000B
R/W
00000400H
DDRG
00000000B
R/W
00000401H
DDRH
00000000B
R/W
00000402H
DDRI
- - - - 0 - - -B
R/W
00000403H
DDRJ
00000000B
R/W
00000404H
DDRK
00000000B
R/W
00000405H
DDRL
00000000B
R/W
00000406H
DDRM
- - - - 0000B
R/W
00000407H
DDRN
- - 000000B
R/W
00000408H
DDRO
00000000B
R/W
00000409H
DDRP
00000000B
R/W
0000040AH
DDRQ
- - 000000B
R/W
0000040BH
DDRR
00000000B
R/W
0000040CH
DDRS
00000000B
R/W
MB91360G Series
Port function registers (PFR)
PFR7
7
6
5
4
3
2
1
0
Initial value Access
Address : 00000617H
P77
P76
P75
P74
P73
P72
P71
P70
PFR8
7
6
5
4
3
2
1
0
Initial value Access
Address : 00000618H
P87
P86
P85
P84
P83
P82


111110 - -B
PFR9
7
6
5
4
3
2
1
0
Initial value Access
Address : 00000619H
P97
P96
P95
P94
P93
P92
P91
P90
PFRB
7
6
5
4
3
2
1
0
Address : 0000061BH
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PFR27
7
6
5
4
3
2
1
0
Address : 00000627H
P277
P276
P275
P274
P273
P272
P271
P270
PFRG
7
6
5
4
3
2
1
0
Address : 00000410H
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PFRH
7
6
5
4
3
2
1
0
Address : 00000411H
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PFRI
7
6
5
4
3
2
1
0
Initial value Access
Address : 00000412H




PI3



- - - - 0 - - -B
PFRJ
7
6
5
4
3
2
1
0
Initial value Access
Address : 00000413H
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PFRK
7
6
5
4
3
2
1
0
Address : 00000414H
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
PFRL
7
6
5
4
3
2
1
0
Address : 00000415H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
PFRM
7
6
5
4
3
2
1
0
Address : 00000416H




PM3
PM2
PM1
PM0
PFRN
7
6
5
4
3
2
1
0
Address : 00000417H


PN5
PN4
PN3
PN2
PN1
PN0
00001111B
11110101B
R/W
R/W
R/W
Initial value Access
00000000B
R/W
Initial value Access
1111 - 00 -B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
R/W
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
- - - - 0000B
R/W
Initial value Access
- - 000000B
R/W
(Continued)
71
MB91360G Series
(Continued)
72
PFRO
7
6
5
4
3
2
1
0
Address : 00000418H
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
PFRP
7
6
5
4
3
2
1
0
Address : 00000419H
PP7
PP6
PP5
PP4
PP3
PP2
PP1
PP0
PFRQ
7
6
5
4
3
2
1
0
Address : 0000041AH


PQ5
PQ4
PQ3
PQ2
PQ1
PQ0
PFRR
7
6
5
4
3
2
1
0
Address : 0000041BH
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
PFRS
7
6
5
4
3
2
1
0
Address : 0000041CH
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
- - 000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
MB91360G Series
5. DMA CONTROLLER (DMAC)
The DMAC module is used to implement direct memory access (DMA) transfer in FR50 series devices.
In a DMA transfer controlled by this module, various types of data can be transferred at high speed without
involving the CPU, thus increasing system performance.
(1) Hardware Configuration
The following are the main components of the DMAC module :
• Five independent DMA channels
• 5-channel independent access control circuit
• 32-bit address registers (Reload can be specified : Two registers for each channel.)
• 16-bit transfer count registers (Reload can be specified : One register for each channel.)
• 4-bit block count registers (One register for each channel)
• External transfer request input pins DREQ0, DREQ1, and DREQ2 (only channels 0, 1, and 2)
• External transfer request acceptance output pins DACK0, DACK1, and DACK2 (only channels 0, 1, and 2)
• DMA termination output pins DEOP0, DEOP1, and DEOP2 (only channels 0, 1, and 2)
• Two-cycle transfer
(2) Main Functions
The following are the main functions of data transfer performed by the module :
• Independent data transfer in multiple channels is enabled (5 channels) .
a : Priority (channel 0 > channel 1 > channel 2 > channel 3 > channel 4)
b : Priority can be alternated between channel 0 and channel 1.
c : DMAC start cause
• External-only pin input (edge detection/level detection channels 0 to 2 only)
• Internal peripheral request (interrupt request is shared, including external interrupts)
• Software request (register write)
d : Transfer mode
• Demand transfer, burst transfer, step transfer, block transfer
• Addressing mode 32-bit full address specification (increase, decrease, fixed)
(An address increment/decrement size of −255 to +255 can be specified.)
• Data types of byte, halfword, and word lengths
• Single-shot/reload selectable
73
MB91360G Series
(3) Registers Configuration
Channel 0 control/status register A
DMACA0 0000200 H
Channel 0 control/status register B
DMACB0 0000204 H
Channel 1 control/status register A
DMACA1 0000208 H
Channel 1 control/status register B
DMACB1 000020CH
Channel 2 control/status register A
DMACA2 0000210 H
Channel 2 control/status register B
DMACB2 0000214 H
Channel 3 control/status register A
DMACA3 0000218 H
Channel 3 control/status register B
DMACB3 000021CH
Channel 4 control/status register A
DMACA4 0000220 H
Channel 4 control/status register B
DMACB4 0000224 H
Overall control register
D M A C R 0000240 H
Channel 0 transfer source address register
DMASA0 0001000 H
Channel 0 transfer destination address register DMADA0 0001004H
Channel 1 transfer source address register
DMASA1 0001008 H
Channel 1 transfer destination address register DMADA1 000100CH
Channel 2 transfer source address register
DMASA2 0001010 H
Channel 2 transfer destination address register DMADA2 0001014H
Channel 3 transfer source address register
DMASA3 0001018 H
Channel 3 transfer destination address register DMADA3 000101CH
Channel 4 transfer source address register
DMASA4 0001020 H
Channel 4 transfer destination address register DMADA4 0001028H
74
MB91360G Series
(4) Block Diagram
Counter
DMA trnasfer request
to bus controller
Selector
Write
back
Buffer
DTC 2-step register DTCR
DMA start
cause selection
circuit and
request
acceptance
control
Peripheral start request/stop
input
External pin start request/stop input
Counter
DSS [3:0]
Read/Write
control
Selector
DDNO
Status
transition
circuit
Clear peripheral interrupt
Selector
MCLREQ
TYPE, MOD, WS
DDNO register
DSAD 2-step register
SDAM, SASZ [7:0] SADR
DDAD 2-step register
DADM, DASZ [7:0] DADR
Write-back
Selector
Counter buffer
Counter buffer
Access
Address
IRQ [4:0]
ERIR, EDIR
DMA control
Address counter
To
bus
controller
Bus control section
BLK register
To transfer controller
Bus control section
Read
Write
Priority circuit
Selector
X-bus
Buffer
Write-back
DMAC 5-channel block diagram
75
MB91360G Series
6. UART
The UART is a serial I/O port for performing asynchronous (stop-start synchronization) communications.
The MB91360G series contains three UART channels.
(1)
•
•
•
•
•
•
•
•
76
Features
Full-duplex, double buffering
Supports asynchronous (stop-start synchronization) communications
Supports multi-processor mode
Fully programmable baud rate
The baud rate can be set using an internal timer. (See the U-TIMER section.)
Supports flexible baud rate setting using an external clock
Error detection function (parity, framing, overrun)
Non return to zero (NRZ) transfer signal
Supports DMA transfer activation using an interrupt
MB91360G Series
(2) Register Configuration
Register structure
8 7
15
Access
0
SCR
SMR
R/W
SSR
SIDR (R)/SODR (W)
R/W
ULS
8 bits
8 bits
Serial input register (SIDR)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Serial output register (SODR)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Serial status register (SSR)
7
6
5
4
3
2
1
0
PE
ORE
FRE
RDRF
TDRE

RIE
TIE
Serial mode register (SMR)
7
6
5
4
3
2
1
0
MD1
MD0


CS0

SCKE

Serial control register (SCR)
7
6
5
4
3
2
1
0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
UART level select register (ULS)
SMR
SCR
Address
Bits
0000 0063H
0000 006FH
0000 007BH
Address
Bits
0000 0062H
0000 006EH
0000 007AH
7
6
5
4
3
2
1
0




NSDO
NSDI
UTDBL
UDBL
7
6
5
4
3
2
1
0
MD1
MD2
R/W
R/W
7
6
5
4
3
2
1
0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Initial value
00000100B
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
← Access
Reserved Reserved
CS0
Reserved Reserved Reserved
Initial value
00 - - 0 - 00B
← Access
W
77
MB91360G Series
(3) Block Diagram
Control signals
Reception interrupt
(to CPU)
SCK (Clock)
From U-TIMER
Transmission
interrupt (to CPU)
Transmitting clock
Clock
selection
circuit
SI
(Reception data)
Receiving clock
Reception control
circuit
Transmission
control circuit
Start bit detecter
Transmission
start circuit
Received bit
counter
Transmission
bit counter
Received parity
bit counter
Transmission
parity counter
SO
(Transmission data)
Transmission
Shifter
Reception
Shifter
Reception status
detecton circuit
Reception
completed
Start of
transmission
SIDR
SODR
Reception error
occurrence
signal for DMA (to DMAC)
R - BUS
MD1
MD0
SMR
register
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
78
MB91360G Series
7. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-timer (U-TIMER) is a 16-bit timer used to generate the baud rate for the UART. The operating frequency
of the chip and the U-TIMER reload value can be combined to set a user-defined baud rate.
The MB91360G series contains three U-TIMER channels. The intervaltimers can count for a maximum of 216 × φ.
(1) Block Diagram
15
0
UTIMR (reload register)
Load
15
0
UTIM (U-timer)
Clock
φ
(Peripheral clock)
Underflow
control
f.f.
To UART
79
MB91360G Series
(2) Register Configuration
Register structure
8 7
15
0
Access
UTIM
R
UTIMR
W
DRCL
UTIMC
R/W
R : Read,
W : Write
UTIM Address Bits
0-ch 00000068H
1-ch 00000074H
2-ch 00000080H
15
14
2
1
0
b15
b14
b2
b1
b0
15
14
2
1
0
b15
b14
b2
b1
b0
2
1
0
UTST
UTCR
Initial value Access
0
R
UTIMR Reload Register
UTIMR Address Bits
0-ch 00000068H
1-ch 00000074H
2-ch 00000080H
Initial value Access
0
W
UTIMC U Timer Control Register
UTIMC Address
0-ch 0000006BH
1-ch 00000077H
2-ch 00000083H
80
7
6
5
4
UCC1



3
UNDR Reserved
Initial value Access
0---0001
R/W
MB91360G Series
8. PWM TIMER
The PWM (Pulse Width Modulation) timer can output high-precision pulse waves at an arbitrary cycle and pulse
width (duty ratio) .
The MB91360G series contains eight PWM timer channels. Each of the channels consists of a 16-bit downcounter, cycle setting register, duty setting register, and pin controller.
The control status register for each channel is used to indicate the operation status of the PWM timer. General
control registers 1 and 2 are common registers shared by four channels, serving for input and software triggering.
(1) Features
• The count clock for the 16-bit down-counter can be selected from among the following four types :
Internal clocks : φ, φ/4, φ/16, φ/64 (φ : Machine clock for peripherals)
• The counter can be initialized to “FFFFH” by a reset or underflow.
The 16-bit down-counter causes an underflow when it changes from “0000H” to “FFFFH”.
• Each channel has PWM outputs.
• Eight channels : Eight output pins
• Registers
• Cycle setting register : Data reload register with buffer
• Data transfer from the buffer is performed either when an activation trigger is detected or when the downcounter causes an underflow (cycle match) . The output is inverted at a cycle match.
• Duty setting register : Compare register with buffer.
• The value set in this register is compared to the counter value. The output is inverted when the values match
(duty match) .
• Pin control
• A duty match causes a reset to “1” (given priority) .
• An underflow causes a reset to “0”.
• The output value fix mode enables output of all “L” or all “H”.
• The polarity can also be specified.
• Interrupt requests can be generated by selecting the following interrupt sources :
• Activation of the PWM timer (software trigger or trigger input)
• Occurrence of an underflow (cycle match)
• Occurrence of a duty match
• Occurrence of an underflow (cycle match) or duty match
• You can set simultaneous activation of two or more channels using software or another interval timer. You can
also set restarting the PWM timer during operation.
81
MB91360G Series
(2) Register Configuration for Channels 1 to 3
Address
Bits
87
15
GCN10
00000118 H
0000011AH
0 Access
PDBL0
GCN20
Register name
R/W
General control register 10
R/W
Disable/General control register 20
PWM timer ch 0
00000120 H
PTMR
R
ch0 timer register
00000122 H
PCSR
W
ch0 cycle setting register
00000124 H
PDUT
W
ch0 duty setting register
R/W
ch0 control status registers
00000126 H
PCNL
PCNH
PWM timer ch 1
00000128 H
PTMR
R
ch1 timer register
0000012AH
PCSR
W
ch1 cycle setting register
0000012CH
PDUT
W
ch1 duty setting register
R/W
ch1 control status registers
0000012EH
PCNH
PCNL
PWM timer ch 2
00000130 H
PTMR
R
ch2 timer register
00000132 H
PCSR
W
ch2 cycle setting register
00000134 H
PDUT
W
ch2 duty setting register
R/W
ch2 control status registers
00000136 H
PCNL
PCNH
PWM timer ch 3
00000138 H
PTMR
R
ch3 timer register
0000013AH
PCSR
W
ch3 cycle setting register
0000013CH
PDUT
W
ch3 duty setting register
R/W
ch3 control status registers
0000013EH
82
PCNH
PCNL
MB91360G Series
(3) PWM Timer Registers for Channels 4 to 7
Address
Bits
87
15
GCN11
0000011CH
0000011EH
0 Access
PDBL1
GCN21
Register name
R/W
General control register 11
R/W
Disable/General control register 21
PWM timer ch 4
00000140 H
PTMR
R
ch4 timer register
00000142 H
PCSR
W
ch4 cycle setting register
00000144 H
PDUT
W
ch4 duty setting register
R/W
ch4 control status registers
00000146 H
PCNL
PCNH
PWM timer ch 5
00000148 H
PTMR
R
ch5 timer register
0000014AH
PCSR
W
ch5 cycle setting register
0000014CH
PDUT
W
ch5 duty setting register
R/W
ch5 control status registers
0000014EH
PCNH
PCNL
PWM timer ch 6
00000150 H
PTMR
R
ch6 timer register
00000152 H
PCSR
W
ch6 cycle setting register
00000154 H
PDUT
W
ch6 duty setting register
R/W
ch6 control status registers
00000156 H
PCNL
PCNH
PWM timer ch 7
00000158 H
PTMR
R
ch7 timer register
0000015AH
PCSR
W
ch7 cycle setting register
0000015CH
PDUT
W
ch7 duty setting register
R/W
ch7 control status registers
0000015EH
PCNH
PCNL
83
MB91360G Series
(4) Configuration Diagram of the Entire PWM Timer
16-bit reload timer
Output pins
OCPA0 (PWM0)
TRG input
PWM timer ch0
ch0
ch1
General control
register 10
(source selection)
General control
register 20
Disable
register 0
16-bit reload timer
ch2
ch3
General control
register 11
(source selection)
General control
register 21
Disable
register 1
TRG input
PWM timer ch1
OCPA1 (PWM1)
TRG input
PWM timer ch2
OCPA2 (PWM2)
TRG input
PWM timer ch3
OCPA3 (PWM3)
TRG input
PWM timer ch4
OCPA4 (PWM4)
TRG input
PWM timer ch5
OCPA5 (PWM5)
TRG input
PWM timer ch6
OCPA6 (PWM6)
TRG input
PWM timer ch7
OCPA7 (PWM7)
(5) Configuration Diagram of PWM Timer 1 ch
Cycle setting register
Duty setting register
PCSR
PDUT
Prescalar
φ/1
φ/4
φ / 16
φ / 64
cmp
Load
Clock
16-bit down-counter
Start
Underflow
PPG mask
S
Peripheral clock (φ)
Q
PWM output
R
Inverted bit
Enable
TRG input
(Internal trigger input)
Edge
detection
Software trigger
84
Interrupt
selection
IRQ
(Interrupt request signal)
MB91360G Series
9. 16-BIT RELOAD TIMER
Each 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, a prescaler for generating
the internal count clock, and a control register.
The 16-bit reload timer can also activate DMA transfer using interrupts.
The MB91360G series contains six 16-bit reload timer channels.
(1) 16 bit Reloard Timer Register Configuration
Control status register (TMCSR)
15
14
13
12
11
10
9
8




CSL1
CSL0


7
6
5
4
3
2
1
0



RELD
INTE
UF
CNTE
TRG
16-bit timer register (TMR)
15
0
15
0
16-bit reload register (TMRLR)
85
MB91360G Series
(2) Block diagram
16
16-bit reload register
8
Reload
RELD
16-bit down-counter

UF
16
R-BUS

GATE
OUT
CTL.
INTE
UF
IRQ
CSL1
CNTE
Clock selector
CSL0
TRG
2
φ
φ
φ
21 23 25
Internal clock
86
Clear
prescalar
PWM (Reload timer 0-ch to 3-ch)*
A/D (Reaload timer 4-ch)*
* Internally connected
MB91360G Series
10. BIT SEARCH MODULE
The bit search module searches for a “0”, “1”, or change-point in the data written to the input register and returns
the position of the detected bit.
This section describes the data register for detecting zeros (BSD0) , data register for detecting ones (BSD1) ,
data register for detecting change-points (BSDC) , and detection result register (BSRR) .
a : Data register for detecting zeros (BSD0)
Address
31
Register structure
0
0000 03F0H
Initial value
Access
Indeterminate
W
Initial value
Access
Indeterminate
R/W
Initial value
Access
Indeterminate
W
Initial value
Access
Indeterminate
R
b : Date register for detecting ones (BSD1)
Address
31
Register structure
0
0000 03F4H
c : Data register for detecting change points (BSDC)
Address
31
Register structure
0
0000 03F8H
d : Detection Result Register (BSRR)
Address
0000 03FCH
31
Register structure
0
87
MB91360G Series
• Block Diagram of the Bit Search Module
Input latch
D-BUS
Address
decoder
Detection
mode
One-detect data conversion
Bit search circuit
Search result
88
MB91360G Series
11. 10-BIT A/D CONVERTER (Successive Approximation Conversion Type)
This section provides an overview of the A/D converter, describes the register structure and functions, and
describes the operation of the A/D converter.
A/D Converter converts analog input voltage into digital values, and provides the following features.
• Conversion time : minimum 178 cycles (32 MHz : 5.6 µs, 24 MHz : 7.4 µs, 16 MHz : 11.2 µs) per channel
• RC type successive approximation conversion with sample & hold circuit
• 10-bit resolution
• Program selection analog input from 16 channels
• Single conversion mode : conversion of one selected channel
• Scan conversion mode : continuous conversion of multiple channels, programmable for up to 16 channels
• Single conversion mode : Convert the specified channel once only.
• Continuous mode : Repeatedly convert the specified channels.
• Stop mode : Convert one channel then temporarily halt until the next activation.
(Enables synchronization of the conversion start timing.)
A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that
is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to
memory.
• Startup may be by software, external trigger (falling edge) or timer (rising edge)
89
MB91360G Series
8 7
15
0
ADMD
ADCH
ADCS
ADCD
ADBL
8 bit
8 bit
Channel setting register (ADCH)
bit
7
6
5
4
3
2
1
0
ANS3
ANS2
ANS1
ANS0
ANE3
ANE2
ANE1
ANE0
bit
15
14
13
12
11
10
9
8
Address : 00009CH




MOD1
MOD0
STS1
STS0
7
6
5
4
3
2
1
0
BUSY
INT
INTE
PAUS


STRT
Reserved
Address : 00009DH
Mode register (ADMD)
Control status register (ADCS)
bit
Address : 00009FH
Data register (ADCD)
bit
7
6
5
4
3
2
1
0
Address : 0000A1H
D7
D6
D5
D4
D3
D2
D1
D0
bit
15
14
13
12
11
10
9
8
Address : 0000A0H






D9
D8
bit
15
14
13
12
11
10
9
8
Address : 0000A3H







DBL
Disable register (ADBL)
90
MB91360G Series
• Block Diagram
AVCC
AVRH/AVRL
MP
AVSS
D/A Converter
Input circuit
Sequential
comparison register
Data bus
Comparator
Sample-and-hold circuit
Decoder
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
ANA
ANB
ANC
AND
ANE
ANF
A/D data register
ADCD
A/D channel setting register
A/D mode register
Trigger activation
A/D control status register
ADCH
ADMD
ADCS
ATG
Timer activation
Output of 16-bit reload timer 4
(internal connection)
Machine clock (φ)
Operating clock
Prescaler
91
MB91360G Series
12. INTERRUPT CONTROLLER
An interrupt controller controls interrupt acceptance and arbitration processing.
Hardware configuration
This module consists of the following :
• ICR register
• Interrupt priority evaluation circuit
• Interrupt level and interrupt number (vector) generator
• Hold request cancel request generator
Major functions
This module has the following major functions :
• Detecting an NMI request or interrupt request
• Priority evaluation (using the level or number)
• Transferring the level of the interrupt cause in the evaluation result (to the CPU)
• Transferring the number of the interrupt cause in the evaluation result (to the CPU)
• Instructing recovery from stop mode due to an NMI or interrupt level other than 11111 (to the CPU)
• Generating a hold request cancel request for the bus master
92
MB91360G Series
(1) Register Configuration
bit 7
6
5
4
3
2
1
0
Address : 00000440H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR00
Address : 00000441H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
Address : 00000442H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
Address : 00000443H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
Address : 00000444H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
Address : 00000445H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
Address : 00000446H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
Address : 00000447H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
Address : 00000448H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
Address : 00000449H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
Address : 0000044AH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
Address : 0000044BH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
Address : 0000044CH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
Address : 0000044DH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
Address : 0000044EH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
Address : 0000044FH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
Address : 00000450H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
Address : 00000451H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
Address : 00000452H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
Address : 00000453H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
Address : 00000454H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
Address : 00000455H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
Address : 00000456H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
Address : 00000457H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
Address : 00000458H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
Address : 00000459H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
Address : 0000045AH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
Address : 0000045BH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
Address : 0000045CH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
Address : 0000045DH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
Address : 0000045EH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
Address : 0000045FH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
R
R/W
R/W
R/W
R/W
(Continued)
93
MB91360G Series
(Continued)
bit 7
6
5
4
3
2
1
0
Address : 00000460H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR32
Address : 00000461H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
Address : 00000462H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
Address : 00000463H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
Address : 00000464H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
Address : 00000465H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR37
Address : 00000466H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
Address : 00000467H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
Address : 00000468H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
Address : 00000469H



ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
Address : 0000046AH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
Address : 0000046BH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
Address : 0000046CH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
Address : 0000046DH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
Address : 0000046EH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
Address : 0000046FH



ICR4
ICR3
ICR2
ICR1
ICR0
ICR47
R
R/W
R/W
R/W
R/W
LVL4
LVL3
LVL2
LVL1
LVL0
R
R/W
R/W
R/W
R/W
Address : 00000045H
MHALTI
R/W
94


HRCL
MB91360G Series
(2) Block Diagram
UNMI
WAKEUP (1 if LEVEL = 11111)
Priority evaluation
NMIRQ
(NMI request)
LEVEL4 to 0
5
NMI
processing
LEVEL evaluation
R100
ICR00
VECTOR
evaluation
R147
6
LEVEL
and
VECTOR
generation
HLDREQ
withdrawal
request
MHALT1
VCT5 to 0
ICR47
(DLYIRQ)
R-BUS
95
MB91360G Series
13. EXTERNAL INTERRUPT/NMI CONTROL BLOCK
The external interrupt/NMI controller controls external interrupt requests input from the NMI and INT0 to INT7
pins.
Detection of “H” levels, “L” levels, rising edges, or falling edges can be selected (except for the NMI) .
The external interrupt/NMI controller can also be used for DMA requests.
This section lists the registers of the controller and provides its block diagram.
(1) Register configuration of the External Interrupt NMI Controller
External interruption permission register (ENIR)
Bit
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
External interruption factors register (EIRR)
Bit
Request level setting register (ELVR)
Bit
Bit
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
(2) Block diagram
R bus
8
Enable interrupt request register
9
Interrupt request
Gate
8
Request F/F
External interrupt request register
8
External level register
96
Edge detect
circuit
9
INT0 to 7
NMI
MB91360G Series
14. DELAYED INTERRUPT
Delayed Interrupt Control Register (DICR)
The delayed interrupt control register (DICR) is a delayed interrupt generator register and is used to generate
the task switching interrupt.
Structure of the DICR
Address
00000044H
Bits
7
6
5
4
3
2
1
0







DLYI
Initial value
-------0
R/W
← Access
97
MB91360G Series
15. CLOCK GENERATION
The MB91V360 generates internal operating clocks as follows :
• Base clock generation : Device scales clock source input by 2 (X clock) or oscillates base clock with PLL to
generate basic clock (PLL clock)
• Generation of each internal clock : Device scales base clock to generate clocks supplied to each block
Generation and control of each clock are explained below.
Some devices allow the operation of the RTC module based on a separate 32 kHz subclock. See the section
about subclock operation for more details.
(1) Register Configuration
RSRR : Reset Source Register, Watchdog Timer Control Register
bit
address : 00000480H
access
Initial Value (INIT)
Initial Value (INIT)
Initial Value (RST)
After Boot ROM **
15
14
13
12
11
10
9
8
INIT
HSTB
WDOG
ERST
SRST

WT1
WT0
R
1
*
X
0
R
0
*
X
0
R
0
*
X
0
R
0
X
*
0
R
0
X
*
0




0
R/W
0
0
0
0
R/W
0
0
0
0
* : varies with reset factor
x : not initialized
** : After execution of the program in the internal boot ROM the reset source is visible
STCR : Standby Control Register
bit
address : 00000481H
access
Initial Value (INIT)
Initial Value (HST) *
Initial Value (INIT)
Initial Value (RST)
7
6
5
4
3
2
STOP
SLEEP
HIZ
SRST
OS1
OS0
R/W
0
0
0
0
R/W
0
0
0
0
R/W
1
1
1
X
R/W
1
1
1
1
R/W
0
1
X
X
R/W
0
1
X
X
1
0
OSCD2 OSCD1
R/W
1
1
1
X
R/W
1
1
1
X
* : Valid only when this initialization is performed simultaneously with initialization by INIT : others same as INIT.
(Continued)
98
MB91360G Series
TBCR : Time-based counter control register
bit
address : 00000482H
Initial Value (INIT)
Initial Value (RST)
15
14
13
12
11
10
TBIF
TBIE
TBC2
TBC1
TBC0

0
0
R/W
0
0
R/W
X
X
R/W
X
X
R/W
X
X
R/W
X
X
R/W
9
8
SYNCR SYNCS
0
X
R/W
0
X
R/W
CTBR : Time-based counter clear register
bit
address : 00000483H
Initial Value (INIT)
Initial Value (RST)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
W
X
X
W
X
X
W
X
X
W
X
X
W
X
X
W
X
X
W
X
X
W
14
13
12
11
10
9
8
CLKR : Clock source control register
bit
address : 00000484H
15
PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1
R/W
0
X
Initial Value (INIT)
Initial Value (RST)
R/W
0
X
R/W
0
X
R/W
0
X
CLKS0
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
WPR Watchdog reset generation postponement register
bit
7
6
5
4
3
2
1
0
address : 00000485H
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value (INIT)
Initial Value (RST)
R/W
X
X
R/W
X
X
R/W
X
X
R/W
X
X
R/W
X
X
R/W
X
X
R/W
X
X
R/W
X
X
DIVR0 : Base clock division setting register 0
bit
7
6
5
4
3
2
1
0
address : 00000486H
B3
B2
B1
B0
P3
P2
P1
P0
Initial Value (INIT)
Initial Value (RST)
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
R/W
1
X
R/W
1
X
DIVR1 : Base clock division setting register 1
bit
7
6
5
4
3
2
1
0
address : 00000487H
T3
T2
T1
T0
S3
S2
S1
S0
Initial Value (INIT)
Initial Value (RST)
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
(Continued)
99
MB91360G Series
(Continued)
CMCR : Clock Control for CAN Modules
address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
initial
0164H
PRE7
PRE6
PRE5
PRE4
PRE3
PRE2
PRE1
PRE0
11111111
address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
initial
0165H
PRES







00000000
Subclock RTC32 (CLKR2)
This register is used to control the RTC32 mode bit for use in subclock system.
address
000046H
access
initial value
100
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8







RTC32
R/W
0
R/W
0
R/W
0
MB91360G Series
(2) Block Diagram
R
[Clock generation block]
DIVR0 and DIVR1
registers
B
U
S
CPU clock division
Ext. bus clock division
Stop control
Resource clock division
CPU clock
CLKB
Resource clock
CLKP
Ext. bus clock
CLKT
CLKR register
SELCLK
X0
X1
Oscillator
circuit
4 MHz
PLL1
1
MONCLK
Clock for CAN
CANCLK
Clock
mod
1/2
Clock for RTC
0
X0A
X1A
Oscillator
circuit
32 kHz
[Stop/sleep control block]
STCR register
internal Interrrupt
Stop state
State
transition
control
circuit
internal Reset
Sleep state
Reset
occurrence F/F
Reset
occurrence F/F
HST
Internal reset (RST)
Internal reset (INIT)
[Reset source circuit]
RST
INIT
RSRR register
WPR register
Watchdog F/F
Timer-base counter
CTBR register
TBCR register
Overflow detect. F/F
Time-base timer
interrupt request
Interrupt enable
[Watchdog control block]
101
MB91360G Series
16. BUS INTERFACE
The external bus interface controls the interfaces with the external memory and external I/Os.
• Up to 32-bit (4 GB) address output.
• Up to eight independent banks provided by chip-select function
The banks can be set in 64-KB (minimum) at any position in the logic address space.
Can be set to no area
• 32/16/8 bit bus width setup can be performed for each chip-select area.
• Programmable automatic memory wait (up to 7 cycles) insertion
Note : Chip Select Areas CS7 and CS1 are used for the internal CAN modules and Flash module (F361GA only)
respectively. The necessary register settings are done by an internal boot routine. Take care not to overwrite
register bits related to those CS areas.
If the CAN macros and the flash memory which are connected internally to the external bus (also called
User Logic Bus) are used, a certain number of data, address and control ports of the external bus interface
cannot be configured as general purpose IO ports.
(1) Register Configuration
Area select Registers (ASR0 to ASR7)
bit 7
bit 0
R/W
00000640H
ASR0
00000000B
W
00000644H
ASR1
0000XXXXB
W
00000648H
ASR2
0000XXXXB
W
0000064CH
ASR3
0000XXXXB
W
0000650H
ASR4
0000XXXXB
W
00000654H
ASR5
0000XXXXB
W
00000658H
ASR6
0000XXXXB
W
0000065CH
ASR7
00000000B
W
After execution of the code internal boot ROM ASR0 is set to “0x20”, ASR1 to “0x1C”, and ASR7 to “0x10”
(F361GA only)
(Continued)
102
MB91360G Series
(Continued)
Area Mask Register (AMR0 to AMR7)
AMR0 00000642H
AM R0
FFFFFFFFH
W
AMR1 00000646H
AMR1
0000XXXXH
W
AMR2 0000064AH
AMR2
0000XXXXH
W
AMR3 0000064EH
AMR3
0000XXXXH
W
AMR4
AMR4
0000XXXXH
W
AMR5 00000656H
AMR5
0000XXXXH
W
AMR6 0000065AH
AMR6
0000XXXXH
W
AMR7 0000065CH
AMR7
00000000H
W
0000652H
Area Mode Registers (AMD0 to AMD7)
00000660H

RDYE
BW1
BW0
WTC2
WTC1
WTC0
00000111B
R/W
CHE5
CHE4
CHE3
CHE2
CHE1
CHE0
11111111B
R/W
CSE4
CSE3
CSE2
CSE1
CSE0
00000001B
R/W

CHE (CacHe Enable register)
00000670H
CHE7
CHE6
CSE (Chip Select Enable register)
00000668H
CSE7
CSE6
CSE5
103
MB91360G Series
(2) Block Diagram
ADDRESS BUS DATA BUS
A-OUT
32
EXTERNAL
DATA BUS
32
write bus
switch
read buffer
switch
MUX
DATA BLOCK
ADDRESS BLOCK
+1 or +2
EXTERNAL
ADDRESS BUS
address buffer
ASR
CS0 to CS7
ASZ
comparator
External pin control section
RD
WR0, WR1
WR2, WR3
All block control
resisters
&
control
104
BRQ
BGRNT
RDY
CLK
MB91360G Series
17. CAN CONTROLLER
This section provides an overview of the CAN Interface, describes the register structure and functions, and
describes the operation of the CAN Interface.
The CAN controller is a module built into a MB91360G series. The CAN (Controller Area Network) is the standard
protocol for serial communication between automobile controllers and is widely used in industrial applications.
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Supports full-bit comparison, full-bit mask and partial bit mask filtering.
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbits/s to 1 Mbits/s (when input clock is at 16 MHz)
The following sections only describe CAN 0. For the addresses of the registers of the other CAN channels see
the IO-Map.
105
MB91360G Series
(1) List of Control Registers
List of Control Registers (1)
Address
CAN0
100000H
100001H
100002H
100003H
100004H
100005H
100006H
100007H
100008H
100009H
10000AH
10000BH
10000CH
10000DH
10000EH
10000FH
100010H
100011H
100012H
100013H
100014H
100015H
100016H
100017H
100018H
100019H
106
Register
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR0
R/W
00000000 00000000
Transmit request register
TREQR0
R/W
00000000 00000000
Transmit cancel register
TCANR0
W
00000000 00000000
Transmit complete register
TCR0
R/W
00000000 00000000
Receive complete register
RCR0
R/W
00000000 00000000
Remote request receiving register
RRTRR0
R/W
00000000 00000000
Receive overrun register
ROVRR0
R/W
00000000 00000000
Receive interrupt enable register
RIER0
R/W
00000000 00000000
Control status register
CSR0
R/W, R
00 - - - 000 0 - - - - 0 - 1
Last event indicator register
LEIR0
R/W
- - - - - - - - 000 - 0000
Receive/transmit error counter
RTEC0
R
00000000 00000000
Bit timing register
BTR0
R/W
-1111111 11111111
IDE register
IDER0
R/W
XXXXXXXX XXXXXXXX
MB91360G Series
List of Control Registers (2)
Address
CAN0
10001AH
10001BH
10001CH
10001DH
10001EH
10001FH
Register
Abbreviation
Access
Initial Value
Transmit RTR register
TRTRR0
R/W
00000000 00000000
Remote frame receive waiting register
RFWTR0
R/W
XXXXXXXX XXXXXXXX
Transmit interrupt enable register
TIER0
R/W
00000000 00000000
100020H
100021H
100022H
XXXXXXXX XXXXXXXX
Acceptance mask select register
AMSR0
R/W
XXXXXXXX XXXXXXXX
100023H
100024H
100025H
100026H
XXXXXXXX XXXXXXXX
Acceptance mask register 0
AMR00
R/W
XXXXX - - - XXXXXXXX
100027H
100028H
100029H
10002AH
10002BH
XXXXXXXX XXXXXXXX
Acceptance mask register 1
AMR10
R/W
XXXXX - - - XXXXXXXX
107
MB91360G Series
(2) Message Buffers
List of Message Buffers (ID Registers) (1)
Address
CAN0
10002CH
to
10004BH
Register
Abbreviation
Access
Initial Value
General-purpose RAM

R/W
XXXXXXXX
to
XXXXXXXX
10004CH
10004DH
10004EH
XXXXXXXX XXXXXXXX
ID register 0
IDR00
R/W
XXXXX - - - XXXXXXXX
10004FH
100050H
100051H
100052H
XXXXXXXX XXXXXXXX
ID register 1
IDR10
R/W
XXXXX - - - XXXXXXXX
100053H
100054H
100055H
100056H
XXXXXXXX XXXXXXXX
ID register 2
IDR20
R/W
XXXXX - - - XXXXXXXX
100057H
100058H
100059H
10005AH
XXXXXXXX XXXXXXXX
ID register 3
IDR30
R/W
XXXXX - - - XXXXXXXX
10005BH
10005CH
10005DH
10005EH
XXXXXXXX XXXXXXXX
ID register 4
IDR40
R/W
XXXXX - - - XXXXXXXX
10005FH
100060H
100061H
100062H
XXXXXXXX XXXXXXXX
ID register 5
IDR50
R/W
XXXXX - - - XXXXXXXX
100063H
100064H
100065H
100066H
100067H
108
XXXXXXXX XXXXXXXX
ID register 6
IDR60
R/W
XXXXX - - - XXXXXXXX
MB91360G Series
List of Message Buffers (ID Registers) (2)
Address
CAN0
Register
Abbreviation
Access
100068H
100069H
10006AH
XXXXXXXX XXXXXXXX
ID register 7
IDR70
R/W
XXXXX - - - XXXXXXXX
10006BH
10006CH
10006DH
10006EH
XXXXXXXX XXXXXXXX
ID register 8
IDR80
R/W
XXXXX - - - XXXXXXXX
10006FH
100070H
100071H
100072H
XXXXXXXX XXXXXXXX
ID register 9
IDR90
R/W
XXXXX - - - XXXXXXXX
100073H
100074H
100075H
100076H
XXXXXXXX XXXXXXXX
ID register 10
IDR10
R/W
XXXXX - - - XXXXXXXX
100077H
100078H
100079H
10007AH
XXXXXXXX XXXXXXXX
ID register 11
IDR11
R/W
XXXXX - - - XXXXXXXX
10007BH
10007CH
10007DH
10007EH
XXXXXXXX XXXXXXXX
ID register 12
IDR12
R/W
XXXXX - - - XXXXXXXX
10007FH
100080H
100081H
100082H
XXXXXXXX XXXXXXXX
ID register 13
IDR13
R/W
XXXXX - - - XXXXXXXX
100083H
100084H
100085H
100086H
100087H
Initial Value
XXXXXXXX XXXXXXXX
ID register 14
IDR14
R/W
XXXXX - - - XXXXXXXX
109
MB91360G Series
List of Message Buffers (ID Registers) (3)
Address
CAN0
Register
Abbreviation
Access
100088H
100089H
10008AH
Initial Value
XXXXXXXX XXXXXXXX
ID register 15
IDR15
R/W
XXXXX - - - XXXXXXXX
10008BH
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
CAN0
10008CH
10008DH
10008EH
10008FH
100090H
100091H
100092H
100093H
100094H
100095H
100096H
100097H
100098H
100099H
10009AH
10009BH
10009CH
10009DH
10009EH
10009FH
1000A0H
1000A1H
110
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR00
R/W
- - - - XXXX
DLC register 1
DLCR10
R/W
- - - - XXXX
DLC register 2
DLCR20
R/W
- - - - XXXX
DLC register 3
DLCR30
R/W
- - - - XXXX
DLC register 4
DLCR40
R/W
- - - - XXXX
DLC register 5
DLCR50
R/W
- - - - XXXX
DLC register 6
DLCR60
R/W
- - - - XXXX
DLC register 7
DLCR70
R/W
- - - - XXXX
DLC register 8
DLCR80
R/W
- - - - XXXX
DLC register 9
DLCR90
R/W
- - - - XXXX
DLC register 10
DLCR100
R/W
- - - - XXXX
MB91360G Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
Register
Abbreviation
Access
Initial Value
DLC register 11
DLCR110
R/W
- - - - XXXX
DLC register 12
DLCR120
R/W
- - - - XXXX
DLC register 13
DLCR130
R/W
- - - - XXXX
DLC register 14
DLCR140
R/W
- - - - XXXX
DLC register 15
DLCR150
R/W
- - - - XXXX
1000ACH
to
1000B3H
Data register 0 (8 bytes)
DTR00
R/W
XXXXXXXX
to
XXXXXXXX
1000B4H
to
1000BBH
Data register 1 (8 bytes)
DTR10
R/W
XXXXXXXX
to
XXXXXXXX
1000BCH
to
1000C3H
Data register 2 (8 bytes)
DTR20
R/W
XXXXXXXX
to
XXXXXXXX
1000C4H
to
1000CBH
Data register 3 (8 bytes)
DTR30
R/W
XXXXXXXX
to
XXXXXXXX
1000CCH
to
1000D3H
Data register 4 (8 bytes)
DTR40
R/W
XXXXXXXX
to
XXXXXXXX
1000D4H
to
1000DBH
Data register 5 (8 bytes)
DTR50
R/W
XXXXXXXX
to
XXXXXXXX
1000DCH
to
1000E3H
Data register 6 (8 bytes)
DTR60
R/W
XXXXXXXX
to
XXXXXXXX
1000E4H
to
1000EBH
Data register 7 (8 bytes)
DTR70
R/W
XXXXXXXX
to
XXXXXXXX
1000ECH
to
1000F3H
Data register 8 (8 bytes)
DTR80
R/W
XXXXXXXX
to
XXXXXXXX
1000F4H
to
1000FBH
Data register 9 (8 bytes)
DTR90
R/W
XXXXXXXX
to
XXXXXXXX
CAN0
1000A2H
1000A3H
1000A4H
1000A5H
1000A6H
1000A7H
1000A8H
1000A9H
1000AAH
1000ABH
111
MB91360G Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
Register
Abbreviation
Access
Initial Value
1000FCH
to
100103H
Data register 10 (8 bytes)
DTR100
R/W
XXXXXXXX
to
XXXXXXXX
100104H
to
10010BH
Data register 11 (8 bytes)
DTR110
R/W
XXXXXXXX
to
XXXXXXXX
10010CH
to
100113H
Data register 12 (8 bytes)
DTR120
R/W
XXXXXXXX
to
XXXXXXXX
100114H
to
10011BH
Data register 13 (8 bytes)
DTR130
R/W
XXXXXXXX
to
XXXXXXXX
10011CH
to
100123H
Data register 14 (8 bytes)
DTR140
R/W
XXXXXXXX
to
XXXXXXXX
100124H
to
10012BH
Data register 15 (8 bytes)
DTR150
R/W
XXXXXXXX
to
XXXXXXXX
CAN0
Configuration Register (CREG)
Address
Register
Abbreviation
Access
Initial Value
Configuration register
CREG0
R/W
00000000
00000110
CAN0
10012CH
10012DH
112
MB91360G Series
(3) Block Diagram
CREG
CANCLK
Clock
Configuration
CLKT
External Bus
(User Logic Bus)
PSC
PR
PH
RSJ
TOE
TS
RS
CSR HALT
NIE
NT
NS1,0
Prescaler 1 to 64
frequency division
Clock for CAN transmit/receive operation
Clock for External Bus Access
TQ (Operating clock)
Bit timing generation
SYNC, TSEG1, TSEG2
BTR
Node status change
interrupt generation
Bus
state
machine
Node status
change interrupt
Error
control
RTEC
Transmitting/
receiving
sequencer
BVALR
TREQR
TBFx,
clear
Transmitting
buffer x decision
TBFX
TBFX
TRTRR
TCR
TBFx, set, clear
TIER
Transmission complete
interrupt generator
RCR
RBFx, set
Reception complete
interrupt generation
RIER
RBFx, TBFx, set, clear
Transmission
complete
interrupt
IDR0 to 15,
DLCR0 to 15,
DTR0 to 15,
RAM
Receiving buffer x
decision
RBFX
RAM address
generation
ACK
CRCER
CRC generator/
error check
Receive
shift register
ARBLOST
Acceptance
filter
TX
generation generation
RBFx, set IDSEL
0
1
Output
driver
Stuffing
CRC
TDLC
RDLC
Reception
completed
interrupt
AMSR
AMR1
ARBLOST
Transmission
shift register
RFWTR
AMR0
Overload
frame
generation
IDSEL
BITER, STFER,
CRCER, FRMER,
ACKER
TCANR
ROVRR
Error
frame
generation
Data
Acceptance
counter filter control
TDLC RDLC
RRTRR
IDLE, INT, SUSPND,
transmit, receive,
ERR, OVRLD
BITER
ACKER
FRMER
STFER
Destuffing/
stuffing
error check
Arbitration
check
Bit error
check
Acknowledgment
error check
PH1
Form error
check
Input
latch
RX
RBFX, TBFX, RDLC, TDLC, IDSEL
LEIR
113
MB91360G Series
18. D/A CONVERTER
This section provides an overview of the D/A converter, describes the register structure and functions, and
describes the operarton of D/A converter.This block is an R-2R format D/A converter, having ten-bit resolution.
The D/A converter has two channels.Output control can be performed independently for the two channels using
the D/A control register.
(1) Block Diagram
R-Bus
DA DA DA DA DA DA DA DA DA DA
19 18 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA DA DA
09 08 07 06 05 04 03 02 01 00
DVR
DVR
DA19
DA09
2R
DA18
2R
DA17
R
R
DA11
114
R
2R
R
2R
R
DA07
DA01
2R
DA10
2R
DA08
R
DA00
2R 2R
2R 2R
DAE1
Standby control
DAE0
Standby control
DA output ch1
DA output ch0
MB91360G Series
(2) Registers
D/A control register (DACR)
bit
Address : 0000A5H
7
6
5
4
3
2
1
0





MODE
DAE1
DAE0
D/A converter data register (ch 0) (DADR0)
bit
15
14
13
12
11
10
9
8
Address : 0000A6H






DA09
DA08
bit
7
6
5
4
3
2
1
0
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
Address : 0000A7H
D/A converter data register (ch 1) (DADR1)
bit
15
14
13
12
11
10
9
8
Address : 0000A8H






DA19
DA18
bit
7
6
5
4
3
2
1
0
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
bit
7
6
5
4
3
2
1
0
Address : 0000ABH







DBL
Address : 0000A9H
D/A clock control (DDBL)
115
MB91360G Series
19. 100 kHz I2C INTERFACE
This section describes the functions and operation of the MB91360G series basic I2C interface. This interface
allows operation up to 100 kHz and 8-bit-addressing.
The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C bus.
(1) I2C Interface Features
The MB91360G series microcontroller includes a built-in one-channel I2C interface. The I2C interface has the
following features.
• Master/slave sending and receiving functions
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transfer direction detection function
• Repeated start condition generation and detection function
• Bus error detection function
116
MB91360G Series
(2) I2C Interface Registers
a : Bus Status Register (IBSR)
Address : 000095H
Read/write
Default value
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Bit no.
b : Bus Control Register (IBCR)
Address : 000094H
Read/write
Default value
15
14
13
12
11
10
9
8
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0


EN
CS4
CS3
CS2
CS1
CS0
()
()
()
()
(R/W)
(0)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Bit no.
c : Clock control register (ICCR)
Address : 000097H
Read/write
Default value
Bit no.
d : Address Register (IADR)
Address : 000096H
Read/write
Default value
15
14
13
12
11
10
9
8

A6
A5
A4
A3
A2
A1
A0
()
()
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Bit no.
e : Data Register (IDAR)
Address : 000099H
Read/write
Default value
Bit no.
f : Clock Disable Register (IDBL)
Address : 00009BH
Read/write
Default value
7
6
5
4
3
2
1
0







DBL
()
()
()
()
()
()
()
()
()
()
()
()
()
()
(R/W)
(0)
Bit no.
117
MB91360G Series
(3) I2C Interface Block Diagram
ICCR
I2C enable
EN
5
ICCR
CS4
CS3
Clock divider 1
6
7
8
Clock signal for division
Clock selector 1
Clock divider 2
2 4 8 16 32 64 128
CS2
CS1
CS0
256
RSC
LRB
Shift clock generator
Clock selector 2
Shift clock edge
conversion timing
IBSR
BB
Sync
Bus busy
Repeat start
Last Bit
Start-stop condition
deector
Error
Send/receive
TRX
First Byte
FBT
AL
Arbitration lost detectior
IBCR
SCL
BER
BEIE
Interrupt request
R-bus
INTE
INT
IBCR
SCC
MSS
ACK
GCAA
End
Start
Master
ACK enable
Start-stop condition
detector
GC-ACK enable
IDAR
IBSR
AAS
GCA
Slave
Global call
Slave address
comparator
IADR
118
SDA
MB91360G Series
20. 400 kHz I2C INTERFACE
This section describes the functions and operation of the fast I2C interface.
The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C bus.
(1)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Master/slave transmitting and receiving functions
Arbitration function
Clock synchronization function
General call addressing support
Transfer direction detection function
Repeated start condition generation and detection function
Bus error detection function
7 bit addressing as master and slave
10 bit addressing as master and slave
Possibility to give the interface a seven and a ten bit slave address
Acknowledging upon slave address reception can be disabled (Master-only operation)
Address masking to give interface several slave addresses (in 7 and 10 bit mode)
Up to 400 KBit transfer rate
Possibility to use built-in noise filters for SDA and SCL
Can receive data at 400 KBit if R-Bus-Clock is higher than 6 MHz regardless of prescaler setting
Can generate MCU interrupts on transmission and bus error events
Supports being slowed down by a slave on bit and byte level
The I2C interface does not support SCL clock stretching on bit level since it can receive the full 400 KBit datarate
if the R-Bus-Clock (CLKP) is higher than 6 MHz regardless of the prescaler setting. However, clock stretching
on byte level is performed since SCL is pulled low during an interrupt (INT = “1” in IBCR register) .
119
MB91360G Series
(2) Block Diagram
IDBL
DBL
ICCR
5
CS4
CS3
CS2
CS1
CS0
R-Bus Clock (CLKP)
FB59 Module Clock Supply
Clock disable
Clock Divider 1
2 3 4 5
32
5
Clock Selector
Sync
Clock Divider 2 (by 12)
SCL Duty Cycle Generator
Shift Clock Generator
IBSR
BB
RSC
LRB
TRX
Bus busy
Repeat start
Bus Observer
Last Bit
Send/receive
Bus Error
ADT
Address Data
AL
Arbitration Loss Detector
ICCR
NSF
IBCR
BER
BEIE
MCU
IRQ
Interrupt Request
INTE
SCL
R-bus
INT
SDA
IBCR
SCC
MSS
ACK
GCAA
Start
Start-Stop Condition
Generator
Master
ACK enable
ACK Generator
GC-ACK enable
8
IDAR
IBSR
AAS
GCA
8
Slave
General call
ISMK
ENSB
Slave Address
Comparator
enable 7 bit mode
ITMK
ENTB
RAL
enable 10 bit mode
received ad. length
10
ITBA
10
10
120
enable
SCL
Noise
Filter
SDA
10
ITMK
7
ISBA
7
ISMK
MB91360G Series
(3) I2C Interface Registers
a : Bus Control Register (IBCR2)
Address : 000184H
Read/write
Default value
15
14
13
12
11
10
9
8
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
(R/W)
(0)
(R/W)
(0)
(W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
b : Bus Status Register (IBSR2)
Address : 000185H
Read/write
Default value
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Bit no.
c : Ten Bit slave Address register (ITBAH, ITBAL)
Ten Bit Address high byte
Address : 000186H
Read/write
Default value
15
14
13
12
11
10
9
8






TA9
TA8
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
Ten Bit Address low byte
Address : 000187H
Read/write
Default value
7
6
5
4
3
2
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
d : Ten bit slave address Mask register (ITMKH, ITMKL)
Ten Bit Address Mask high byte
Address : 000188H
Read/write
Default value
15
14
13
12
11
10
9
8
ENTB
RAL




TM9
TM8
(R/W)
(0)
(R)
(0)
()
(1)
()
(1)
()
(1)
()
(1)
(R/W)
(1)
(R/W)
(1)
Bit no.
Ten Bit Address Mask low byte
Address : 000189H
Read/write
Default value
7
6
5
4
3
2
1
0
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
Bit no.
e : Seven Bit slave Address register (ISBA)
Address : 00018BH
Read/write
Default value
7
6
5
4
3
2
1
0

SA6
SA5
SA4
SA3
SA2
SA1
SA0
()
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
(Continued)
121
MB91360G Series
(Continued)
f : Seven bit slave address Mask register (ISMK)
Address : 00018AH
Read/write
Default value
15
14
13
12
11
10
9
8
ENSB
SM6
SM5
SM4
SM3
SM2
SM1
SM0
(R/W)
(0)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
15
14
13
12
11
10
9
8








()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8

NSF
EN
CS4
CS3
CS2
CS1
CS0
()
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
7
6
5
4
3
2
1
0







DBL
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
()
(0)
(R/W)
(0)
Bit no.
g : Data Register (IDARH, IDAR2)
Data register high byte
Address : 00018CH
Read/write
Default value
Bit no.
Data register
Address : 00018DH
Read/write
Default value
Bit no.
h : Clock control register (ICCR2)
Address : 00018EH
Read/write
Default value
Bit no.
i : Clock Disable Register (IDBL2)
Address : 00018FH
Read/write
Default value
122
Bit no.
MB91360G Series
21. 16-BIT I/O TIMER
The MB91360G Series contains two 16-bit free-running timer modules, two output compare modules, and two
input capture modules and supports four input channels and four output channels. The following sections only
describes the 16-bit free-running timer, Output Compare 0/1 and Input Capture 0/1.
The remaining modules have the identical functions and the register addresses should be found in the I/O map.
(1) Function Overview
a : 16-bit free-running timer
The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The values output from
this timer counter are used as the base timer for input capture and output compare.
• Four counter clocks are available.
Internal clock : φ/4, φ/16, φ/32, φ/64
• An interrupt can be generated upon a counter overflow or a match with compare register 0.
• The counter value can be initialized to “0000H” upon a reset, software clear, or match with compare register 0.
b : Output compare (2 channels per one module)
The output compare module consists of two 16-bit compare registers, compare output latch, and control register.
When the 16-bit free-running timer value matches the compare register value, the output level is reversed and
an interrupt is issued.
• The two compare registers can be used independently.
Output pins and interrupt flags corresponding to compare registers
• Output pins can be controlled based on pairs of the two compare registers.
Output pins can be reversed by using the two compare registers.
• Initial values for output pins can be set.
• Interrupts can be generated upon a compare match.
c : Input capture (2 channels per one module)
The input capture module consists of two 16-bit capture registers and control registers corresponding to two
independent external input pins. The 16-bit free-running timer value can be stored in the capture register and
an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin.
• The detection edge of an external input signal can be specified.
Rising, falling, or both edges
• Two input channels can operate independently.
• An interrupt can be issued upon a valid edge of an external input signal.
123
MB91360G Series
(2) Registers
a : 16-bit free-running timer
15
0
Timer data register
TCDT
0000C8 H
0000CBH
Timer status register
TCCS
b : 16-bit output compare
15
0
0000BCH
0000BE H
Compare register
OCCP0/1
0000B8 H
Control status register
OCS0
OCS1
c : 16-bit input capture
15
0
0000B0 H
0000B2 H
0000ACH
Capture register
IPC0/1
IOTDBL0
Disable/Control status register
ICS0/1
(3) Block Diagram
To each block
Control logic
Interrupt
16-bit free-run timer
16-bit timer
Clear
Bus
Output compare 0
Compare register 0
TQ
OUT0
Compare register 1
TQ
OUT1
Output compare 1
Input caputure 0
Capture register 0
Edge selection
IN0
Capture register 1
Edge selection
IN1
Input caputure 1
124
MB91360G Series
22. ALARM COMPARATOR
This section provides an overview of the Alarm Comparator (Also called Under/Overvoltage Detection) , describes the register structure and functions, and describes the operation of the Alarm Comparator.
(1) Block Diagram
Alarm comparator - analog part
Alarm comparator - digital part
AVDD
FR51
OUT1
B0DX
D Q
ALARM
CK
RB [15:0]
STOP
STOP
WRCR
PMWR
RDCR
RSLEEP
RST
CLKP
ACSR
PD
OUT2
RB [15:0]
D Q
DEC
RSLEEP
RST
CLKP
CK
REG
CDBLE
CLKP
CDBLE
IRQ_AC
Interrupt
logic
F-MODULE
IRQ_AC
B-MODULE
UMQA02
(2) Registers
Alarm Comparator Clock Disable Register (ACCDBL)
Address
00000180H
Bits
7
6
5
4
3
2
1
0







CDBLE
R/W
Initial value
- - - - - - - 0B
← Access
Alarm Comparator Status Disable Register (ACSR)
Address
00000181H
Bits
7

6
5
OV_EN UV-EN
R/W
R/W
4
3
2
1
0
OUT2
OUT1
IRQ
IEN
PD
R
R
R/W
R/W
R/W
Initial value
-11xxx00B
← Access
125
MB91360G Series
23. POWER DOWN RESET
This section provides an overview of the Power Down Reset, describes the register structure and functions, and
describes the operation of the Power Down Reset Module.
The power down reset module performs a system reset when VCC goes below a threshold voltage. The reset
signal is be disabled and enabled by setting the power down reset control register PDRCR. For low power
applications the digital and the analog part of the power down reset control circuit can be disabled.
(1) Block Diagram
input stage
PDCOMP
IN
OUT
EN
PDRST
RST
9-bit LFSR
READY
counter
CLR
S
Q
WR
R
RB [1]
(RD bit)
(2) Register
PDRCR
access
initial value (INIT)
initial value (RST)
126
7
6
5
4
3
2
1
0





CDSBLE
PD
EN


X


X


X


X


X
R/W
0
X
R/W
0
X
R/W
0
X
MB91360G Series
24. SERIAL I/O INTERFACE (SIO)
This section provides an overview of the Serial I/O Interface (SIO) , describes the register structure and functions,
and describes the operation of the SIO.
(1) Block Diagram
This block is a serial I/O interface that allows data transfer using clock synchronization. The interface consists
of a single eight-bit channel. Data can be transferred from the LSB or MSB.
MB91360G series contains two Serial I/O units SIO0 and SIO1. This section only describes SIO0. Please see
the IO-Map for the register addresses of SIO1.
The serial I/O interface operates in two modes :
• Internal shift clock mode : Data is transferred in synchronization with the internal clock.
• External shift clock mode : Data is transferred in synchronization with the clock supplied via the external pin
(SCK) . By manipulating the general-purpose port sharing the external pin (SCK) ,
data can also be transferred by a CPU instruc tion in this mode.
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first)
Transfer direction selection
SIN3
Read
Write
SDR (Serial data register)
SOT3
SCK3
Control circuit
Shift clock counter
Internal clock
2
SMD2
1
SMD1
0
SMD0
SIE
SIR
BUSY
STOP
STRT
MODE
BDS

SCOE
Interrupt
request
Internal data bus
127
MB91360G Series
(2) Registers
Serial mode control status register (SMCS)
Address : 000084H
Address : 000085H
15
14
13
12
11
10
9
8
SMD2
SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
7
6
5
4
3
2
1
0




MODE
BDS

SCOE
SIO edge selection/clock disable register (SES)
Address : 000086H
15
14
13
12
11
10
9
8






DBL
NEG
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Serial data register (SDR)
Address : 000087H
128
MB91360G Series
25. SOUND GENERATOR
This section provides an overview of the Sound Generator, describes the register structure and functions, and
describe the operation of the Sound Generator.
The Sound Generator consists of the Sound Control register, Frequency Data register, Amplitude Data register,
Decrement Grade register, Tone Count register, Sound Disable register, PWM pulse generator, Frequency
counter, Decrement counter and Tone Pulse counter.
(1) Registers
Sound Control register (SGCR)
Address : 0000EFH
Read/write
Default value
Address : 0000EEH
Read/write
Default value
7
6
5
4
3
2
1
0
S1
S0
TONE


INTE
INT
ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
()
()
()
()
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
TST





BUSY
DEC
(R/W)
(0)
()
()
()
()
()
()
()
()
()
()
(R)
(0)
(R/W)
(0)
Bit no.
Bit no.
Frequency Data register (SGFR)
Address : 0000F1H
Read/write
Default value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
Amplitude Data register (SGAR)
Address : 0000F0H
Read/write
Default value
Bit no.
Decrement Grade register (SGDR)
Address : 0000F3H
Read/write
Default value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Bit no.
Tone Count register (SGTR)
Address : 0000F2H
Read/write
Default value
Bit no.
Sound Disable register (SGDBL)
Address : 0000EDH
Read/write
Default value
7
6
5
4
3
2
1
0







DBL
()
()
()
()
()
()
()
()
()
()
()
()
()
()
(R/W)
(0)
Bit no.
129
MB91360G Series
(2) Block Diagram
Clock input
Prescaler
S1
S0
8-bit PWM
pulse generator CO
EN
PWM
CI
Frequency
counter
Toggle
flip-flop
CO
EN
Reload
Amplitude data
register
Reload
Tone count
register
1/d
DEC
CI
CO
EN
SGA
Decrement grade
register
Tone pulse
counter
Q
Decrement
Grade register
DEC
Decrement
counter
D
EN
Mix
SGO
TONE
CI
CO
EN
INTE
INT
ST
IRQ
130
MB91360G Series
26. STEPPER MOTOR CONTROLLER
This section provides an overview of the Stepper Motor Control Module, describe the register structure and
functions, and described the operation of the Stepper Motor Control Module.
The Stepping Motor Controller consists of two PWM Pulse Generators, four motor drivers, Selector Logic and
the Zero Rotor Position Detector. The four motor drivers have high output drive capabilities and they can be
directly connected to the four ends of two motor coils. The combination of the PWM Pulse Generators and
Selector Logic is designed to control the rotation of the motor. A Synchronization mechanism assures the
synchronous operations of the two PWMs. The Zero Rotor Position Detector helps CPU obtain feed back
information of the rotor movements. The following sections describe the Stepping Motor Controller 0 only. The
other controllers have the same functions. The register addresses are found in the I/O map.
Note : The Rotor Zero Position Detection capability is protected by a patent from Mannesmann VDO and may only
be used with VDO’s prior approval.
(1) Block Diagram
Machine clock
Prescaler
CK
PWM1P0
PWM1 pulse generator
EN
P1
Selector
PWM
PWM1M0
P0
PWM1 compare register
PWM1 selector register
CK
PWM2P0
PWM2 pulse generator
CE
EN
Selector
PWM
PWM2M0
Load
PWM2 compare register
BS
PWM2 select register
Comparator
Debounce logic
8-bit counter
Zero Detect 0
register
+
−
PWM2M0
1/9 AVCC
reference
voltage
Power down
Zero Rotor Position Detector
131
MB91360G Series
(2) Registers
PWM Control 0 register (PWC0)
Address : 0000D1H
Read/write
Default value
7
6
5
4
3
2
1
0


P1
P0
CE


TST
()
()
()
()
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
()
()
()
()
(R/W)
(0)
Bit no.
Zero Detect 0 register (ZPD0)
Address : 0000D0H
Read/write
Default value
15
14
13
12
11
10
9
8
S1
S0
TS
T2
T1
T0
PD
RS
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(0)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Bit no.
PWM1 Compare 0 register (PWC10)
Address : 0000D9H
Read/write
Default value
Bit no.
PWM2 Compare 0 register (PWC20)
Address : 0000D8H
Read/write
Default value
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0


P2
P1
P0
M2
M1
M0
()
()
()
()
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
PWM1 Select register (PWS10)
Address : 0000DBH
Read/write
Default value
Bit no.
PWM2 Select register (PWS20)
Address : 0000DAH
Read/write
Default value
15
14
13
12
11
10
9
8

BS
P2
P1
P0
M2
M1
M0
()
()
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
PWM Clock Disable register (SMDBL0)
Address : 0000E8H
Read/write
Default value
132
7
6
5
4
3
2
1
0







DBL
()
()
()
()
()
()
()
()
()
()
()
()
()
()
(R/W)
(0)
Bit no.
MB91360G Series
27. REAL TIME CLOCK
This section provides an overview of the Real Time Clock (also called Watchtimer) , describes the register
structure and functions, and describes the operation of RTC module.The Real Time Clock (Watch Timer) consists
of the Timer Control register, Sub-second register, Second/Minute/Hour registers, 1/2 clock divider, 21bit
prescaler and Second/Minute/Hour counters. The Real Time Clock operates as the real-world timer and provides
the real-world time information.
(1) Block Diagram
Oscillation
clock
21 bit prescaler
CO
1/2 Clock
Divider
WOT
EN
Sub second
register
UPDT
ST
Second counter
CI
EN
LOAD
CO
Minute counter
6 bits
6 bits
Hour counter
CO
CO
5 bits
Second/Minute/Hour register
INTE0 INT0
INTE1 INT1
INTE2 INT2
INT3
INT3
IRQ
133
MB91360G Series
(2) Registers
Timer disable register (WTDBL)
Address : 0000F5H
Read/write
Default value
7
6
5
4
3
2
1
0







DBL
()
()
()
()
()
()
()
()
()
()
()
()
()
()
(R/W)
(0)
Bit no.
Timer control register (WTCR)
Address : 0000F7H
Read/write
Default value
Address : 0000F6H
Read/write
Default value
7
6
5
4
3
2
1
0
TST2
TST1
TST0

RUN
UPDT

ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
()
()
(R)
(0)
(R/W)
(0)
()
()
(R/W)
(0)
15
14
13
12
11
10
9
8
INTE3
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0



D20
D19
D18
D17
D16
()
()
()
()
()
()
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8


S5
S4
S3
S2
S1
S0
()
()
()
()
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Bit no.
Bit no.
Sub-second register (WTBR)
Address : 0000FBH
Read/write
Default value
Address : 0000FAH
Read/write
Default value
Address : 0000F9H
Read/write
Default value
Bit no.
Bit no.
Bit no.
Second register (WTSR)
Address : 0000FEH
Read/write
Default value
Bit no.
(Continued)
134
MB91360G Series
(Continued)
Minute register (WTMR)
Address : 0000FDH
Read/write
Default value
7
6
5
4
3
2
1
0


M5
M4
M3
M2
M1
M0
()
()
()
()
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8



H4
H3
H2
H1
H0
()
()
()
()
()
()
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Bit no.
Hour register (WTHR)
Address : 0000FCH
Read/write
Default value
Bit no.
135
MB91360G Series
28. SUBCLOCK
The Subclock System provides various power saving modes. The key of the concept is to supply the 32 kHz
clock signal only to the Real Time Clock RTC) Module, while the rest of the MCU is provided with 4 MHz clock
signal in order to achieve lower power supply current in the RTC32K mode.
This behavior can be altered by the configuration input, SELCLK pin to switch the RTC module to operate with
the 4 MHz clock. The following sections describe the operation with SELCLK connected to “0” and SELCLK
connected to “1” respectively.
Note : On MB91F361GA and MB91F362GA SELCLK should always be connected to “1”, subclock operation is not
implemented on those devices.
(1) Operation of Subclock (SELCLK = 0)
The next table summarizes the operation states of the components related to the Subclock System.To simplify
this table SLEEP modes are not listed but the operation is the same as for RUN modes except that the CPU is
stopped.
Operation of components
Mode
Power dissipation
CPU &
4 M Osc.
32 K Osc.
RTC
PLL
Peripheral
RUN
High
Run
Run
Run
Run
Stop/Run
RTC4M32K
Medium Low
Run
Run
Run
Stop
Stop
RTC32K
Low
Stop
Run
Run
Stop
Stop
STOP
Lowest
Stop
Stop
Stop
Stop
Stop
The following table summarizes those operation modes and necessary software settings.
Software Setting
Mode
STOP
PLL1EN
PLL2EN
OSCD1
OSCD2
RTC32
RUN
0
0 or 1
1
Don’t Care
Don’t Care
Don’t Care
RTC4M32K
1
Don’t Care
1
0
0
Don’t Care
RTC32K
1
Don’t Care
1
1
0
1
STOP
1
Don’t Care
Don’t Care
1
1
Don’t Care
It is recommended that PLL2EN is set to “1” after the initialization to start the 32 kHz oscillation and this bit
should be kept at “1” during the operation. Otherwise the 32 kHz oscillator does not start. Also bits 9 and 10 of
the CLKR register (address 0046H) should always be set to “0” during operation.
136
MB91360G Series
(2) 4 MHz Real Time Clock Configuration (SELCLK = 1)
When the SELCLK pad is connected logic level 1, the 32 kHz oscillation is disabled regardless of the software
setting. In this configuration, the Real Time Clock Module is supplied with the 4 MHz oscillation clock signal.
The following table summaries the modes available in this configuration.
Operation of components
Mode
Power dissipation
CPU &
4 M Osc.
32 K Osc.
RTC
Peripheral
PLL
RUN
High
Run
Stop
Run
Run
Stop/Run
RTC4M
Medium Low
Run
Stop
Run
Stop
Stop
STOP
Lowest
Stop
Stop
Stop
Stop
Stop
Mode
Software Setting
STOP
PLL1EN
PLL2EN
OSCD1
OSCD2
RTC32
RUN
0
0 or 1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
RTC4M
1
Don’t Care
Don’t Care
0
Don’t Care
Don’t Care
STOP
1
Don’t Care
Don’t Care
1
Don’t Care
Don’t Care
(3) Use of Real Time Clock Module
There is some additional consideration needed to operate the RTC module to achieve the desired functionality.
Because the RTC module is directly connected to the 32 kHz oscillation clock, the oscillation stabilization time
has to be taken care of by the software.This can be achieved by using another timer (e.g the Time Base Timer)
to trigger the software to start the RTC module (Setting of ST bit to “1”) .
It is also important to stop the RTC module before entering the STOP mode. Otherwise, the reactivation from
STOP mode results in unpredictable operation of the RTC module.
After the reactivation, the oscillation stabilization time has to be measured again by the software, then the RTC
module can be restarted.
137
MB91360G Series
29. 32 kHz CLOCK CALIBRATION UNIT
The 32 kHz Clock Calibration Module provides possibilities to calibrate the 32 kHz oscillation clock with respect
to the 4 MHz oscillation clock.
(1) Description
This hardware allows the software to measure time generated by the 32 kHz clock with the 4 MHz clock.
By utilizing this hardware in conjunction with software processing, the accuracy of the 32 kHz clock can come
closer to that of the 4 MHz clock. The measurement result from the 32 kHz Clock Calibration Module can be
processed by the software and the setting required for the Real Time Clock Module can be obtained.
This module consists of two timers, one operating with the 32 kHz clock and the other operating with the 4 MHz
clock. The 32 kHz timer triggers the 4 MHz timer and resulting 4 MHz timer value is stored in a register. The
value stored in this register can be used for the subsequent software processing to calculate the desired Real
Time Clock module’s setting.
(2) Block Diagram
UC18CLK
CLK4G = OSC4 | ∼ STRT | (READY & −RUNS) ;
gete
OSC4
STRT
READY
RUNS
OSC32
gete
STRT
gete
CLKP
RSLEEPB
gete
CLKPG
CLK32G
CLKPG2 CUTD
32 kHz UC18TRD
TIMER
counter (16 bit)
STRTS
RSLEEPB
STRT
SLKPG2 = CLKP
| (∼STRT & RSLEEPB) ;
&
anync
RUN RST
STRT
set
/reset
RB
INT
reset
UC18BUS
138
UC18TRR
&
READY
RUNSS1
RUNSS
sync
4 ≥ CLKP
set
READYPULSE
CUCR (3 bit)
INT_I
RDB
WRB
RSTB
UC18IO
CUTR
reset
INTEN
set
/reset
RBB
RSLEEPB
RMWB
RB
RSLEEP
RMW
RD
WR
sync RUNS
32 ≥ 4
4 MHz
TIMER
CUTR (24 bit)
STRT
STRT
INT
RUN
READY
sync
CLKP ≥ 32
async
STRT RST
RST
CLK4G
&
INT_INT
CUTR (24 bit)
CUTD (16 bit)
CUTD
CU18RBI
FC18
MB91360G Series
(3) Timing
32 kHz
STRT (CLKP)
STRTS (32 kHz)
RUN (32 kHz)
RUNS (4 MHz)
32 kHz counter (16 bit)
4 MHz counter (24 bit)
CUTD CUTD-1
old CUTR
0
2
1
0
CUTD
new CUTR
READY (32 kHz)
READYPULSE (CLKP)
INT (CLKP)
139
MB91360G Series
(4) Clocks
The module operates with 3 different clocks : The 4 MHz clock OSC4, the 32 kHz clock OSC32 and the Rbus
clock CLKP. Synchronization circuits adapt the different domains.
All 3 clocks are gated. The 32 kHz and the 4 MHz clock are switched off if STRT is 0. CLKPG is gated by RSLEEP
and CLKPG2 by RSLEEP and STRT for the 2 bits, which are set/reset by hardware.
The clock frequencies have to fulfill the following requirements :
1.) Clock ratio
TOSC32 > 2 × TOSC4 + 3 × TCLKP
TOSC4 < 1 / 2 × TOSC32 − 3 / 2 × TCLKP
TCLKP < 1 / 3 × TOSC32 − 2 / 3 × TOSC4
2.) The input frequencies must not exceed the values given in next table.
Maximum operation frequencies
CLKP
maximum
32 MHz
OSC32
31.25 ns
4 MHz
250 ns
OSC4
13 MHz
76.9 ns
Examples of valid clock ratios which fulfill requirements 1 and 2
OSC32
140
OSC4
CLKP
maximum operation speed
4 MHz
250 ns
13 MHz
76.9 ns
32 MHz
31.25 ns
standard TDIR mode
500 kHz
2000 ns
4 MHz
250 ns
4 MHz
250 ns
normal operation
32 kHz
31.25 us
4 MHz
250 ns
> 2 MHz
500 ns
MB91360G Series
(5) Register Description
a : Calibration Unit Control Register (CUCR)
Control Register low byte (CUCRL)
Address : 000191H
Read/write
Default value
7
6
5
4
3
2
1
0



STRT


INT
INTEN
(R)
(0)
(R)
(0)
(R)
(0)
(R/W)
(0)
(R)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
b : 32 kHz Timer Data Register (CUTD)
32 kHz Timer Data Register high byte (CUTDH)
Address : 000192H
Read/write
Default value
15
14
13
12
11
10
9
8
TDD15
TDD14
TDD13
TDD12
TDD11
TDD10
TDD9
TDD8
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
32 kHz Timer Data Register low byte (CUTDL)
Address : 000193H
Read/write
Default value
7
6
5
4
3
2
1
0
TDD7
TDD6
TDD5
TDD4
TDD3
TDD2
TDD1
TDD0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit no.
c : 4 MHz Timer Data Register (CUTR)
4 MHz Timer Data Register1 high byte (CUTR1H)
Address : 000194H
Read/write
Default value
15
14
13
12
11
10
9
8








(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Bit no.
4 MHz Timer Data Register1 low byte (CUTR1L)
Address : 000195H
Read/write
Default value
7
6
5
4
3
2
1
0
TDR23
TDR22
TDR21
TDR20
TD19
TDR18
TDR17
TDR16
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Bit no.
4 MHz Timer Data Register2 high byte (CUTR2H)
Address : 000196H
Read/write
Default value
15
14
13
12
11
10
9
8
TDR15
TDR14
TDR13
TDR12
TDR11
TDR10
TDR9
TDR8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Bit no.
4 MHz Timer Data Register2 low byte (CUTR2L)
Address : 000197H
Read/write
Default value
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TD3
TDR2
TDR1
TDR0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Bit no.
141
MB91360G Series
30. FLASH MEMORY
MB91360G series devices feature 512 K of embedded flash memory. On MB91F361GA it is connected to the
external bus, on the other devices to the F-bus.
(1) Out Line of Flash Memory
The Flash Memory consists of a flash memory unit derived from the MBM29LV400C and a flash memory interface
circuit.
Flash Memory :
• 512 Kword × 8 bit/256 Kword × 16 bit/128 Kword × 32 bit
(64 Kbyte×3 + 32 Kbyte + 8 Kbyte×2 + 16 Kbyte) sectors
• Uses automatic program algorithm (Embedded Algorithm)
• Erase pause/restart function
• Detects completion of writing/erasing using data polling or toggle bit functions
• Detects completion of writing/erasing by RY/BY pin
• Compatible with JEDEC standard commands
• Performs minimum of 10,000 write/erase operations
• Sector erase function (any combination of sectors)
• Sector protect function
• Temporary sector protect cancellation function
• Allows flash memory interface circuit to write to/erase flash memory both under control of external pin by writer
and under control of internal bus by CPU.
Embedded Algorithm is a registered trademark of Advanced Micro Devices, Inc.
142
MB91360G Series
(2) Block diagrams of Flash Memory
a : Block diagram of Flash Memory
Figure shows the block diagram of the flash memory unit, which has almost the same configuration as the
MBM29FLV400C.
DQ0 to DQ15
RY/BY
buffer
RY/BY
I/O buffer
Erase circuit
WE
BYTE
RESET
Control
circuit
Write circuit
Chip enable/
output enable
circuit
CE
OE
STB
Y decoder
Data latch
Y gate
STB
Low VCC
detection circuit
Write/erase
pulse timer
address
latch X decoder
cell matrix
A0 to A17
A-1
b : Entire block diagram of Flash Memory
Figure shows the entire block diagram of the Flash Memory with the flash memory interface circuit.
Flash memorry
interface circuit
Ext.Bus
I/F
BYTE
BYTE
CE
CE
OE
OE
WE
WE
A0 to A18
User
Logic
bus
4 Mbit flash memory
DQ0 to DQ15
RY/BY
A0 to A17
A-1
DQ0 to DQ15
RY/BY
RESET
External reset signal
RY/BY
write enable signal
143
MB91360G Series
c : Sector configuration
i) write, byte read, half word read
8 bit × 2
Flash Memory mode
Other modes F361GA
Other modes
other devices
7FFFFH
1FFFFF
FFFFF
Sector 13
16 KB
7C000H
1FC000
FC000
Sector 12
8 KB
7A000H
1FA000
FA000
Sector 11
8 KB
78000H
1F8000
F8000
Sector 10
32 KB
70000H
1F0000
F0000
Sector 9
64 KB
60000H
1E0000
E0000
Sector 8
64 KB
50000H
1D0000
D0000
Sector 7
64 KB
40000H
1C0000
C0000
Sector 6
16 KB
3C000H
1BC000
BC000
Sector 5
8 KB
3A000H
1BA000
BA000
Sector4
8 KB
38000H
1B8000
B8000
Sector 3
32 KB
30000H
1B0000
B0000
Sector 2
64 KB
20000H
1A0000
A0000
Sector 1
64 KB
10000H
190000
90000
Sector 0
64 KB
00000H
180000
80000
ii) long word read
144
MSB
LSB
8 bit × 2
8 bit × 2
Flash Memo- Other modes Other modes
ry mode
F361GA
other devices
7FFFF
1FFFFFH
FFFFF
Sector 13
16 KB
Sector 6
16 KB
78000H
1F8000H
F8000
Sector 12
8 KB
Sector 5
8 KB
74000H
1F4000H
F4000
Sector 11
8 KB
Sector 4
8 KB
70000H
1F0000H
F0000
Sector 10
32 KB
Sector 3
32 KB
60000H
1E0000H
E0000
Sector 9
64 KB
Sector 2
64 KB
40000H
1C0000H
C0000
Sector 8
64 KB
Sector 1
64 KB
20000H
1A0000H
A0000
Sector 7
64 KB
Sector 0
64 KB
00000H
180000H
80000
MB91360G Series
(3) Write/Erase Modes
The flash memory can be accessed in two different ways; the flash memory mode allowing write/erase directly
from the external pins, and the other modes allowing write/erase from the CPU via the internal bus. These modes
are selected by the external mode pins.
a : Flash Memory mode
The CPU stops when the mode pins are set to 111 while the INIT signal is asserted. The flash memory interface
circuit is directly connected to the external bus interface, allowing direct control by the external pins. This mode
makes the MCU seem like a standard flash memory at the external pins, and write/erase can be performed
using a flash memory programmer.
In the flash memory mode all the operations supported by the flash memory automatic algorithm can be used.
b : Other modes
The flash memory is located in the CS1 area of the CPU memory space and like ordinary mask ROM can be
read-accessed and program-accessed from the CPU through the flash memory interface circuit. After execution
of the internal Boot ROM the area for CS1 is set from 180000 to FFFFF (F361GA only) .
Writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface
circuit. Therefore, this mode allows rewriting even when the MCU is soldered on the target board.
The sector protect operations can not be performed in these modes.
c : Control signals of flash memory
Next table lists the flash memory control signals in the flash memory mode.
There is almost a one-to-one correspondence between the flash memory control signals and the external pins
of the MBM29LV400C. The VID (12 V) pins required by the sector protect operations are MD0, MD1 and MD2
instead of A9, RESET and OE for the MBM29LV400C.
In the flash memory mode, the width of the external data bus can be 8 or 16 bit.
145
MB91360G Series
Flash Control Signals
MB91F361GA/MB91F362GA
Normal function
Flash Memory mode
1 to 8
D24 to D31
D24 to D31
DQ8 to DQ15
9
A0
A0
A-1
10 to 24
A1 to A15
A1 to A15
A0 to A14
27 to 30
A16 to A18
A16 to A18
A15 to A17
32
CS4
CS4
WE
33
CS5
CS5
BYTE
35
RDY
RDY
OE
36
BGRNT
BGRNT
CE
37
BRQ
BRQ
RY/BY
111
MD0
VDA9
A9 (VID)
112
MD1
VDRS
RESET (VID)
113
MD2
VDOE
OE (VID)
115
INIT
INIT
RESET
201 to 208
D16 to D23
D16 to D23
DQ0 to DQ7
A19, A20 should be pulled up, INIT must be low during power on for at least 500 ns.
146
MBM29LV400C
Pin number
MB91360G Series
MB91FV360GA
MBM29LV400C
Pin number
Normal function
Flash Memory mode
202
A0
A0
A-1
310
A1
A1
A0
201
A2
A2
A1
357
A3
A3
A2
257
A4
A4
A3
144
A5
A5
A4
309
A6
A6
A5
256
A7
A7
A6
200
A8
A8
A7
356
A9
A9
A8
308
A10
A10
A9
92
A11
A11
A10
44
A12
A12
A11
255
A13
A13
A12
143
A14
A14
A13
199
A15
A15
A14
307
A16
A16
A15
91
A17
A17
A16
142
A18
A18
A17
140
CS4
CS4
WE
196
CS5
CS5
BYTE
89
CS6
TMOD

305
RDY
RDY
OE
139
BGRNT
BGRNT
CE
88
BRQ
BRQ
RY/BY
293
MD0
VDA9
A9 (VID)
31
MD1
VDRS
RESET (VID)
239
MD2
VDOE
OE (VID)
30
INIT
INIT
RESET
46
D16
D16
DQ0
95
D17
D17
DQ1
1
D18
D18
DQ2
148
D19
D19
DQ3
205
D20
D20
DQ4
(Continued)
147
MB91360G Series
(Continued)
MB91FV360GA
148
MBM29LV400C
Pin number
Normal function
Flash Memory mode
45
D21
D21
DQ5
94
D22
D22
DQ6
260
D23
D23
DQ7
312
D24
D24
DQ8
204
D25
D25
DQ9
147
D26
D26
DQ10
93
D27
D27
DQ11
259
D28
D28
DQ12
203
D29
D29
DQ13
146
D30
D30
DQ14
258
D31
D31
DQ15
MB91360G Series
(4) Flash Control Status Register (FMCS)
Flash Memory Macros used in devices :
Normal Flash Macro used in : MB91F361GA, MB91F362GA
Fast Flash Macro used in : MB91FV360GA
address
FV360GA, F362GA : 00007000H
F361GA : 00100180H
access
initial value
value after
Boot ROM
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FACCEN


RDYEG*
RDY
RDYI
WE
LPM
R/W
1
0
R/W
1
1
R/W
1
1
R
0
0
R
X
X
R/W
0
0
R/W
0
0
R/W
0
0
* : It is not allowed to use RDYEG.
149
MB91360G Series
(5) Read/Write Access
In the flash memory mode, read/write access to the flash memory must be under control of the external pins.
However, with the CPU access, there are no special timing constraints on read/write access because the flash
memory is controlled by the flash memory interface circuit.
In this section, “write access” does not directly mean “program flash memory”. It implies “activation of the flash
commands”.
a : Read/write access in flash memory mode
Next table gives the setting of pins for read/write access in the Flash Memory mode. There is no special problem
with control of these pins if connected to a flash memory writer. However, in other cases, timing specifications
must be met.
Setting Conditions of Pins for Read/Write Access in Flash Memory Mode
Operations
BGRNTX (CE)
RDY (OE)
CS4X (WE)
A0 to A18
D16 to D31
INIT
Read
L
L
H
Read address
DOUT
H
Write
L
H
L
Write address
DIN
H
Output disable
L
H
H
x
High-Z
H
Standby
H
x
x
x
High-Z
H
Hardware reset
x
x
x
x
High-Z
L
b : Read/write access with CPU on F361GA
The access timing to the flash memory unit is controlled by the flash memory interface circuit. Depending on
the setting for CLKT the read operation can be completed in two or more cycles of CLKT.
External Bus clear
Wait cycles
32 MHz
1
24 MHz
1
≤ 16 MHz
0
c : Read access with CPU on other devices
Flash Wait Control Register (FMWT) *
address
00007004H
access
initial value
value after Boot ROM
Normal Flash Macro
value after Boot ROM
Fast Flash Macro
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0


FAC1
FAC0
EQINH
WTC2
WTC1
WTC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
0
1
1
* : FMWT register is not available on MB91F361GA (Flash on external bus)
150
MB91360G Series
Normal Flash Macro : Recommended settings
Without applying clock modulation
CLKB unmodulated
core clock frequency
[MHz]
FAC1
FAC0
EQINH
WTC2
WTC1
WTC0
FACC low
cycles/wait
cycles
FMWT
64
0
1
0
0
1
1
1/3
13H
48
0
1
0
0
1
1
1/3
13H
40
0
1
0
0
1
0
1/2
12H
32
0
0
0
0
1
0
0.5 / 2
02H
24
0
0
0
0
0
1
0.5 / 1
01H
16
0
0
0
0
0
1
0.5 / 1
01H
FACC low
cycles/wait
cycles
FMWT
When applying clock modulation
CLKB core clock
frequency
[MHz]
Peak Max.
frequency
FAC1
48
64
0
1
0
0
1
1
1/3
13H
32
48
0
1
0
0
1
1
1/3
13H
24
40
0
1
0
0
1
0
1/2
12H
24
32
0
0
0
0
1
0
0.5 / 2
02H
16
24
0
0
0
0
0
1
0.5 / 1
01H
FAC0 EQINH WTC2 WTC1 WTC0
Example for flash memory read access with 1 cycle for the low time of FACC and 3 wait cycles
1 cycle
FACC = "L"
3 wait cycles
core
clock
CLKB
FA
A1
A2
A3
F-bus
wait
FWAITR
FACC
F-bus
address
tFP
FD
FACC
for flash
tFACC
D1
F-bus
data
The minimum value for tFP is 15 ns, for tFACC it is 40 ns.
151
MB91360G Series
Fast Flash Macro : Recommended settings
Without applying clock modulation
CLKB unmodulated
core clock frequency
[MHz]
FAC1
FAC0
EQINH
WTC2
WTC1
WTC0
ATDIN high
cycles/wait
cycles
FMWT
64
0
1
0
0
1
1
1/3
13H
48
0
0
0
0
1
0
0.5 / 2
02H
40
0
0
0
0
1
0
0.5 / 2
02H
32
0
0
1
0
0
1
0.5 / 1
09H
24
0
0
0
0
0
1
0.5 / 1
01H
16
0
0
0
0
0
1
0.5 / 1
01H
When applying clock modulation
CLKB core clock
Peak Max.
frequency
frequency
[MHz]
FAC1
FAC0
EQINH
WTC2
WTC1
WTC0
ATDIN high
cycles/wait
cycles
FMWT
48
64
0
1
0
0
1
1
1/3
13H
32
48
0
0
0
0
1
0
0.5 / 2
02H
24
40
0
0
0
0
1
0
0.5 / 2
12H
24
32
0
0
1
0
0
1
0.5 / 1
09H
16
24
0
0
0
0
0
1
0.5 / 1
01H
Example for flash memory read access with 1 cycle for the high time of ATDIN and 3 wait cycles
1 cycle
ATDIN ="H"
3 wait cycles
core
clock
CLKB
FA
A1
F-bus
A3 address
A2
F-bus
wait
FWAITR
ATDIN
EQIN
ATDIN
for flash
tWATD
EQIN
for flash
tWEQ
FD
D1
tACC
tRC
The minimum value for tWATD is 10 ns, the minimum value for tWEQ is 20 ns.
The minimum value for tRC is 40 ns.
The maximum value for tACC is tWATD + tWEQ + 5 ns.
152
F-bus
data
MB91360G Series
d : Write access with CPU on other devices
Recommended settings for WTC2 to WTC0 for write access to the flash memory, FACCEN of FMCS should be
set to 1 for writing, so FAC1, FAC0, EQINH register settings then have no meaning for the write operation
Without applying clock modulation
CLKB unmodulated
core clock frequency
[MHz]
WTC2
WTC1
64
WTC0
Wait cycles
FMWT
setting not allowed for writing
48
1
0
0
4
X4H
40
1
0
0
4
X4H
32
0
1
0
2
X2H
24
0
1
0
2
X2H
16
0
0
1
1
X1H
When applying clock modulation
CLKB core clock
frequency [MHz]
Peak Max.
frequency
48
64
32
48
1
0
0
4
X4H
24
40
1
0
0
4
X4H
24
32
0
1
0
2
X2H
16
24
0
1
0
2
X2H
WTC2
WTC1
WTC0
Wait cycles
FMWT
setting not allowed for writing
153
MB91360G Series
(6) Automatic Write/Erase
Irrespective of the Flash Memory mode or other modes, writing to/erasing the flash memory unit is performed
by starting the flash memory automatic algorithm.
To start the automatic algorithm, various sequences of write accesses are executed in 1 to 6 cycles. They are
called Flash commands.
a : Flash Commands
There are four commands for starting the automatic algorithm of the Flash Memory unit; Read/Reset, Write,
Chip Erase, and Sector Erase. There are also Erase Suspend and Erase Resume commands for the sector
erase operation.
Next tables give the command sequence lists in the flash memory and other modes.
b : Command sequence
Command Sequence List (CPU access)
Second
Fourth Read/
Third Write
Fifth Write
Sixth Write
Write First Write
Write Cycle
Write Cycle
Cycle
of
Bus
Cycle
of
Bus
Cycle
of
Bus
Cycle
of Bus
Command Cycle
of Bus
of Bus
Sequence
of
AdAdAdAdAdAdBus
Data
Data
Data
Data
Data
Data
dress
dress
dress
dress
dress
dress
Read/
Reset*1
1
*2xxxx
Read/
Reset*1
4
*25554 xxAA *2aaa8
xx55 *25554 xxF0
Write
4
*25554 xxAA *2aaa8
xx55 *25554 xxA0
Chip Erase
6
*25554 xxAA *2aaa8
xx55 *25554 xx80 *25554 xxAA *2aaa8 xx55 *25554 xx10
Sector
Erase
6
*25554 xxAA *2aaa8
xx55 *25554 xx80 *25554 xxAA *2aaa8 xx55
xxF0










RA
RD








PA
PD
(even) (word)
SA
(even)
Sector Erase
Suspend
Input of address *2xxxx or data (xxB0H) suspends sector erasing.
Sector Erase
Resume
Input of address *2xxxx or data (xx30H) suspends and resumes sector erasing.
xx30
Addresses in the table are the values in the CPU memory space. All addresses and data are hexadecimal values,
where x is any value and *2 may be 08 to 0F on F362GA/FV360GA, 18 to 1F on F361GA.
*1 : Read/Reset command reset Flash memory to read mode.
154
MB91360G Series
Command Sequence List (Flash Memory Mode)
Second
Fourth Read/
Third Write
Fifth Write
Sixth Write
Write First Write
Write Cycle
Write Cycle
Cycle
of
Bus
Cycle
of
Bus
Cycle
of
Bus
Cycle
of Bus
Command Cycle
of Bus
of Bus
Sequence
of
AdAdAdAdAdAdBus
Data
Data
Data
Data
Data
Data
dress
dress
dress
dress
dress
dress
Read/
Reset*
1
*xxxx
F0










Read/
Reset*
4
*aaaa
AA
*5554
55
*aaaa
F0
RA
RD




Write
4
*aaaa
AA
*5554
55
*aaaa
A0
PA
PD
(even) (word)




Chip Erase
6
*aaaa
AA
*5554
55
*aaaa
80
*aaaa
AA
*5554
55
*aaaa
10
Sector
Erase
6
*aaaa
AA
*5554
55
*aaaa
80
*aaaa
AA
*5554
55
SA
(even)
30
Sector Erase
Suspend
Input of address *xxxx or data (B0H) suspends sector erasing.
Sector Erase
Resume
Input of address *xxxx or data (30H) suspends and resumes sector erasing.
Addresses in the table are values for writer addresses. All addresses and data are hexadecimal values, where x
is any value and * may be 0 to 7.
RA : Read address
PA : Write address. Only even addresses can be specified.
SA : Sector address (See next table) . Only even addresses can be specified.
RD : Read data
PD : Write data. Only word data can be specified.
155
MB91360G Series
Sector Address for half word mode
156
Sector
A18
A17
A16
A15
A14
A13
Address range
SA13
1
1
1
1
1

7C000H to 7FFFFH
SA12
1
1
1
1
0
1
7A000H to 7BFFFH
SA11
1
1
1
1
0
0
78000H to 79FFF
SA10
1
1
1
0


70000H to 77FFFH
SA9
1
1
0



60000H to 6FFFFH
SA8
1
0
1



50000H to 5FFFFH
SA7
1
0
0



40000H to 4FFFFH
SA6
0
1
1
1
1

3C000H to 3FFFFH
SA5
0
1
1
1
0
1
3A000H to 3BFFFH
SA4
0
1
1
1
0
0
38000H to 39FFFH
SA3
0
1
1
0


30000H to 37FFFH
SA2
0
1
0



20000H to 2FFFFH
SA1
0
0
1



10000H to 1FFFFH
SA0
0
0
0



00000H to 0FFFFH
MB91360G Series
(7) Connection to Flash Memory
The Flash Memory mode of the MB91F361GA is intended mainly for external connection to a flash memory
writer. As indicated in Table Flash Control Signals, there is a slight difference between the external pins of the
MB91F361GA and the MBM29LV400C (4 Mbit flash memory) . Connection to an MBM29LV400C writer requires
the socket adapter.
Socket adapter
flash writer
MB91F361GA
A9
A10
2.2 kΩ
RESET
INIT
2.2 kΩ
OE
RDY
2.2 kΩ
MD0
2.2 kΩ
MD1
2.2 kΩ
MD2
2.2 kΩ
157
MB91360G Series
(8) Notes to Use of Flash Memory
Notes on the Flash Memory in MB91360G series devices are given below.
a : Input of hardware reset (INIT)
To input a hardware reset when the automatic algorithm is not started, where reading is in progress, a minimum
of 500 ns should be taken at a low-level width. In this case, a maximum of 500 ns is required until data can be
read from the flash memory after a hardware reset has been activated.
Similarly, to input a hardware reset when the automatic algorithm is activated, where writing/erasing is in
progress, a minimum of 50 ns should be taken in a low-level width. In this case, 20 µs are required until data
can be read after the executing operation has been terminated to initialize the flash memory.
A hardware reset during writing undefined data being written. A hardware reset during erasing may make the
sector being erased unusable.
b : Canceling software reset, watchdog timer reset, and hardware standby
When writing/erasing the flash memory with the CPU access and if reset conditions occur while the automatic
algorithm is active, the CPU may run away. This occurs because these reset conditions cause the automatic
algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from
entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset
conditions should be inhibited during writing/erasing the Flash Memory.
c : Program access to Flash Memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory
access mode of the CPU set to the internal ROM mode, writing/erasing should be started after switching the
program area to another area such as RAM.
In this case, when sectors containing interrupt vectors are erased, interrupt processing cannot be executed.
For the same reason, all interrupt sources should be disabled while the automatic algorithm is operating.
d : Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed and many
cause erroneous writing/erasing. When the acceptance of a hold request is enabled, ensure that the WE bit of
the control status register (FMCS) is 0.
e : Applying VID
Applying VID required for the sector protect operation should always be started and terminated when the supply
voltage is on.
158
MB91360G Series
(9) Timing Diagrams in Flash Mode
Each timing diagram for the external pins of the MB91F361 in the Flash Memory mode is shown below.
a : Data read by read access
tRC
A18 to A0
Address stable
tAC
120 ns
30 ns
BGRNT (CE)
RDY (OE)
tOE
50 ns
120 ns (TOGGLE)
0 ms (Read)
tDF
tOEH
CS4 (WE)
tOH
0
tCE
120 ns
High-Z
High-Z
Output defined
D31 to D16
b : Write Data polling Read (WE control)
Third bus cycle
A18 to A0
Data Polling
7AAAAH
PA
tWC
tAS
PA
tRC
tAH
BGRNT (CE)
tGHEL
RDY (OE)
tWP
tWHWH1
CS4 (WE)
tOE
tWPH
tCS
tDF
tDH
A0H
D31 to D16
PD
D23
DOUT
tDS
tOH
VDD (= 5.0 V)
tCE
PA : Write address
PD : Write data
D23 : Reverse output of write data
DOUT : Output of write data
Note : The last two bus cycle sequences out of the four are described.
159
MB91360G Series
c : Write Data polling Read (CE control)
Third bus cycle
Data Polling
7AAAAH
A18 to A0
PA
tWC
tAS
PA
tAH
tWH
BGRNT (CE)
tGHEL
RDY (OE)
tCP
tWHWH1
CS4 (WE)
tCPH
tWS
tDH
A0H
D31 to D16
PD
DOUT
D23
tDS
VDD (= 5.0 V)
PA : Write address
PD : Write data
D23 : Reverse output of write data
DOUT : Output of write data
Note : The last two bus cycle sequences out of the four are described.
d : Chip erase/sector erase command sequence
tAS
7AAAAH
A18 to A0
tAH
75554H
7AAAAH
7AAAAH
75554H
SA*
BGRNT (CE)
tGHWL
RDY (OE)
tWP
CS4 (WE)
tWPH
tCS
D31 to D16
tDH
AAH
tDS
55H
80H
AAH
55H
10H/30H
VDD
tVCS
Note : SA is the sector address at sector erasing. 7AAAAH (or 6AAAAH) is the address at chip erasing.
160
MB91360G Series
e : Data polling
tCH
BGRNT (CE)
tOE
tDF
RDY (OE)
tOEH
CS4 (WE)
tCE
tOH
*
D23
D23 =
Valid data
D23
High-Z
tWHWH1 or tWHWH2
D31 - D16 = Invalid
D31 to D16
D31 - D16 =
Valid data
tEOE
* : DQ7 is valid data (The device terminates automatic operation) .
f : Toggle bit
BGRNT (CE)
tOEH
RDY (OE)
tOES
CS4 (WE)
Data
(D31 to D16)
D22 = Toggle
D22 = Toggle
*
*
D22 = Stop
toggling
D31 to D16
= Valid
tOE
* : DQ6 stops toggling (The device terminates automatic operation) .
g : RY/BY timing during writing/erasing
BGRNT (CE)
Rising edge of last write pulse
RDY (OE)
Writing or erasing
CS4 (WE)
tBUSY
161
MB91360G Series
h : INIT and RY/BY timing
BGRNT (CE)
CS4 (OE)
tRP
BRQ (RY/BY)
tREADY
i : Enable sector protect/verify sector protect
A18 to A13
SAx
A7, A2,
and A1
(A7, A2, A1) = (0, 1, 0)
MD0 (A9(VID))
12 V
5V
MD2 (OE(VID))
12 V
5V
SAy
tVLHT
tVLHT
CS4 (WE)
tWPP
RDY (OE)
tOESP
D31 to D16
tCSP
01H
tOE
SAx : First sector address
SAy : Next sector address
162
MB91360G Series
j : Temporary sector protect cancellation
MD1
(RESET (VID))
12 V
5V
5V
BGRNT (CE)
CS4 (WE)
tVLHT
Write/erase command sequence
BRQ (RY/BY)
Sector protect cancellation
163
MB91360G Series
(10) AC Characteristics in Flash Memory Mode
The AC specifications for the external pins of the MB91F361 in the Flash Memory mode are shown below. They
apply to the case where the user performs read/write access in the Flash Memory mode. They are not needed
for access in the normal mode and for use of a flash memory writer.
The values are subject to change without prior notice.
a : Read access
AC Characteristics for Read Access
(Under recommended conditions)
Symbol
Test
Conditions
Min.
Typ.
Max.
Read cycle time
tRC

120


ns
Address access time
tACC
CE = VIL
OE = VIL


120
ns
CE to data output
tCE
OE = VIL


120
ns
OE to data output
tOE



50
ns
CE to output floating
tDF



30
ns
OE to output floating
tDF



30
ns
Previous cycle data output hold time
tOH

0


ns
tReady



20
µs
Parameter
INITI pin to return to read mode
164
Value
Unit
MB91360G Series
b : Write [write/erase command] access (WE control)
AC Characteristics for Write Access (WE Control)
(Under recommended conditions)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Write cycle time
tWC
120


ns
Address setup time
tAS
0


ns
Address hold time
tAH
50


ns
Data setup time
tDS
50


ns
Data hold time
tDH
0


ns
Output enable setup time
tOES
0


ns
0


ns
10


ns
tGHWL
0


ns
CE setup time
tCS
0


ns
CE hold time
tCH
0


ns
Write pulse width
tWP
50


ns
Write pulse width High level
tWPH
20


ns
Write continuation time
tWHWH1

16

µs
Sector erase continuation time*1
tWHWH2

1.5
30
s
tVCS
50


µs
tVLHL
4


µs
tWPP
100


µs
tOESP
4


µs
tCSP
4


µs
tRP
500


ns
tBUSY
50


ns
Output enable hold time
Read
Toggle and data polling
Read recovery time before write
VCC setup time
Voltage transition time*
2
Write pulse width*2
OE setup time for validating WE*2
CE setup time for validating WE*
2
INIT pulse width
RY/BY delay until write/erase is enabled
tOEH
*1 : The internal preprogramming time before erasing is not included.
*2 : Applies only to sector protection
165
MB91360G Series
c : Write [write/erase command] access (CE control)
AC Characteristics for Write Access (CE Control)
(Under recommended conditions)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Write cycle time
tWC
120


ns
Address setup time
tAS
0


ns
Address hold time
tAH
50


ns
Data setup time
tDS
50


ns
Data hold time
tDH
0


ns
Output enable setup time
tOES
0


ns
0


ns
10


ns
tGHWL
0


ns
WE setup time
tWS
0


ns
WE hold time
tWH
0


ns
CE pulse width
tCP
50


ns
CE pulse width High level
tCPH
20


ns
Write continuation time
tWHWH1

16

µs
Sector erase continuation time*
tWHWH2

1.5
30
s
VCC setup time
tVCS
50


µs
INIT pulse width
tRP
500


ns
tBUSY
50


ns
Output enable hold time
Read
Toggle and data polling
Read recovery time before write
RY/BY delay until write/erase is enabled
tOEH
* : The internal preprogramming time before erasing is not included.
166
Value
MB91360G Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Rating
Symbol
Unit
Condition
Min.
Max.
VDD-VSS
−0.3
6.0
V
HVDD-HVSS
−0.3
6.5
V
Storage temperature
Tstg
−55
+125
°C
Power consumption
PTOT

*1
mW
Digital input voltage
VIDIG
−0.3*2
5.8
V
VSS = 0 V, VDD = 5 V
Analog input voltage
VIA
−0.3
5.8
V
VSSA = 0 V, VDDA = 5 V
Analog supply voltage
VDDA-VSSA
−0.3
5.8
V
VSSA = 0 V
Analog reference voltage
VREFH/L-VSSA
−0.3
5.8
V
VSSA = 0 V
II/ODC
−2
2
mA
Digital supply voltage
Stepper motor control supply voltage
Static DC current into digital I/O
TA = +25°C
ΣII/ODC < ISRUN
*1 : The value differs in each kind of the product.
*2 : Making full use of the allowed static DC correct into digital I/O will lead to lower values for VIDIG Min.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
Parameter
Operating temperature
Digital supply
Supply voltage
Stepper motor
(Internal voltage
control supply
regulator)
Analog supply
RAM data retention voltage
Symbol
Value
Min.
TA
−40
VDD - VSS
4.25*
HVDD - HVSS
Typ.
Max.
Unit
Condition
+85
°C
5
5.25
V
VDDCORE = 3.3 V
4.75
5
5.25
V
HVSS = 0 V
VDDA - VSSA
4.9
5
5.1
V
VSSA = 0 V
VDD - VSS
3.0


V
*: This is only valid if the integrated power-down reset circuit is switched-off, else a reset can be triggered at voltages
less or equal than 4.5 V (see “■ PERIPHERAL RESOURCES 23. POWER DOWN RESET”) .
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
167
MB91360G Series
3. DC Characteristics
Current
consumption
Min.
Typ.
Max.
Run mode
Isrun


*1
RTC mode
IsRTC

0.5

1.25
500
mA fclk = 4 MHz at TA = 25 °C
µA fclk = 32 kHz at TA = 25 °C
Stop mode
Isstop

10
200
µA fclk = 0 at TA = 25 °C
VOHH
HVDD − 500

HVDD − 125 mV Iol = ±30 mA, TC = 25 °C
VOHL
HVSS + 125

HVSS + 500 mV Iol = ±30 mA, TC = 25 °C
VOHH
HVDD − 500

HVDD − 125 mV Iol = ±27 mA, TC = 85 °C
VOHL
HVSS + 125

HVSS + 500 mV Iol = ±27 mA, TC = 85 °C
VOHH
HVDD − 500

HVDD − 125 mV Iol = ±30 mA, TC = −40 °C
VOHL
HVSS + 125

HVSS + 500 mV Iol = ±30 mA, TC = −40 °C
VTHcomp
HVDD / 9
− 70
HVDD / 9
HVDD / 9
+ 70
mV


40

ns
Cload = 0 pF
/ VDDA + 5%
V
(external 4 : 1 divider)
/ VDDA + 5%
V
H-port output voltage
Stepper
motor
control
SMC comparator
threshold voltage
Slew rate
OverThreshold voltage
voltage
UnderAlarm comvoltage
parator
Switching hysteresis
/ VDDA − 5%
4 5
4 5
/ VDDA − 5%
2 5
2 5
VTAH
4 5
VTAL
2 5
/ VDDA
/ VDDA
Unit
Condition
mA TA = 25 °C
V TAHYS
12.5
25
50
mV
Alarm sense time
tAS


10
µs
Input resistance
Rin
5


MΩ at VTAH, VTAL
VTPOR
3.5
4.0
4.5
V
20
50
80
mV
tRS


10
µs
VOH
VDD − 0.5

VDD
V
Iload = 4mA
VOL
VSS

VSS + 0.4
V
Iload = −4mA
Threshold voltage
Power
down Reset
Value
Symbol
Parameter
Switching hysteresis
Reset sense time
Digital out- Output “H” voltage
puts
Output “L” voltage
VTPORHYS
*1 : See “4. Run Mode Current/Power Consumption”.
(Continued)
168
MB91360G Series
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
VIH
0.65 × VDD

VDD
V
VIL
VSS

0.25 × VDD
V
High voltage
range
VIH
0.8 × VDD

VDD
V
Low voltage
range
VIL
VSS

0.2 × VDD
V
High voltage
range
VIH
0.8 × VDD

VDD
V
Low voltage
range
VIL
VSS

0.5 × VDD
0.6 × VDD
V
V
hysteresis
voltage


0.5

V
VIH
0.65 × VDD

VDD
V
VIL
VSS

0.25 × VDD
V
High voltage
range
VIH
0.65 × VDD

VDD
V
Low voltage
range
VIL
VSS

0.25 × VDD
V
CMOS 3 V Input capaci(Type : P, W) tance
CIN


16
pF
Input leakage
current
IIL
−1

+1
µA TA = 25 °C
Rup1
Rup2

50
10

kΩ Types : E, U
kΩ Type : S
(Continued)
High voltage
CMOS
range
(Type : Q, S,
Low voltage
Y, T)
range
CMOS
SchmittTrigger
(Types : E,
F, U)
Digital
Inputs*2
Value
CMOS
Automotive
SchmittTrigger
(Types : A,
B, K1, M1, J)
High voltage
CMOS 3/5 V range
(Type : L, N,
Low voltage
O)
range
Pull up
resistor
VDDmin = 4.25 V
VDDmin = 4.75 V
*2 : valid for bidirectional tristate I/O PAD cell
169
MB91360G Series
(Continued)
Parameter
Value
Min.
Typ.
Max.
Unit
Condition
Reference voltage input
VREFH
VREFL
VREFL + 3
VSSA

VDDA
VREFH − 3
V
V
Input voltage range
Vimax
Vimin
VREFL


VREFH

V
V
Input resistance
RI


3.6
kΩ
Input capacitance
CI


30
pF
Input leakage current
IIL
−5

5
µA
TA = 25 °C
Impedance of external
output driving the ADC
input



4.0
kΩ
at sampling time of
1.6 µs
Output voltage
Vout
VSSA

VDDA
V
Output impedance
Rout

2.9

kΩ
Output capacitance
Cout


20
pF
VoutHIGH
VoutLOW
VDD − 0.5
VSS

VDD
VSS + 0.4
V
V
Iout
4


mA
Output voltage
VoutHIGH
VoutLOW
VDD − 0.5
VSS

VDD
VSS + 0.4
V
V
Output current
Iout
4


mA
VoutHIGH
VoutLOW
VDD − 0.8



VSS + 0.8
V
V
Output voltage
VoutHIGH
VoutLOW

VSS

VDD
VSS + 0.4
V
V
Output current
Iout
3


mA IoutLOW = 3 mA
Lock-up time PLL1
(4 MHz →16 MHz to 64 MHz)


0.1
1
ms
ESD Protection
(Human body model MIL883-B
compliant)
Vsurge
2


kV
ADC
inputs
DAC
analog
outputs
Output voltage
Sound
generator
Output current
PPG
LED
I2C Bus
Interface
(Open
Drain
Output)
170
Symbol
Output voltage
external voltage
follower required
IoutHIGH = 14 mA
IoutLOW = 24 mA
Rdischarge = 1.5 kΩ
Cdischarge = 100 pF
MB91360G Series
4. Run Mode Current/Power Consumption
The power dissipation during normal operation is determined by the total power dissipation of the internal logic
PC, the dissipation from analog modules PA and the power dissipation PIO of the I/O buffers. Among the I/O buffers
the dissipation caused by the stepper motor drivers PSMC should be taken into special consideration.
So the overall power consumption PD will be calculated as a sum of Pc + PA + PSMC + PIO .
(1) Logic Power Consumption
The following formula can be used to calculate the maximum core current consumption when the PLL is used
depending on the frequency settings for the internal clocks :
ICC = 3.45 [mA/MHz] × CLKB [MHz] + 2.52 [mA/MHz] × CLKP[MHz] + 0.72 [mA/MHz] × CLKT [MHz] + 35.5 mA.
If clock modulation is used the following value must be added to this result : 0.24 [mA/MHz] × CLKB [MHz].
This results in the following values (higher clock settings are not allowed) :
Clock frequencies [MHz]
Maximum Core
Logic Power
Current
Consumption
CLKB
CLKP
CLKT
Consumption [mA]
PC at 5.25 V [mW]
Remarks
64
16
16
308
1.70
no clock modulation possible
48
24
24
290
1.52
48
16
16
264
1.40
32
32
32
257
1.35
32
16
16
205
1.08
24
24
24
202
1.06
24
12
12
163
0.86
16
16
16
146
0.77
2
2
2
40
0.21
no PLL, no clock modulation
0.125
0.125
0.125
30
0.16
no PLL, no clock modulation
In addition to this power consumption of the MCU core logic the following contributions to the overall power consumption have to be considered :
(2) Analog Power Consumption
Module
Maximum Current Consumption
DAC
1 mA / channel
ADC
7 mA
Power down reset
0.5 mA
Remarks
Alarm Comparator
0.5 mA
To calculate the analog power consumption PA, the current contributions of the active modules have to be multiplied by the maximum analog supply voltage of 5.1 V.
171
MB91360G Series
(3) I/O and SMC Power Consumption
SMC drivers :
The average current consumption per SMC channel is 38.2 mA, for four channels this results in 152.8 mA.
At 2 × 0.5 V this results in 153 mW power consumption PSMC for four channels of stepper motor drivers.
Other I/O Buffers :
The power dissipation (PIO) (at 5.25 V) of the I/O buffers is represented as the sum of the dynamic power
dissipation (PAC) and the static power consumption (PDC) .
PIO = PAC × 1.1 + PDC
The following table lists values for PAC :
Buffer Type
Normal Input
Bidirectional Input
4 mA Bidirectional Output
4 mA Output
Power Consumption
Unit
12.4
194 + 25 CL
µW/MHz
@ 5.0 V
8 mA Bidirectional Output
353 + 25 CL
8 mA Output
PAC = PIB × In × f × operating rate + POB × On × f × operating rate
PIB :
POB :
In :
On :
f:
Power Consumption of Input Buffers and Bidirectional Inputs
Power Consumption of Output Buffers and Bidirectional Outputs
Total number of input buffers and bidirectional buffer inputs
Total number of output buffers and bidirectional buffer outputs
System frequency
Operating rate : 1.0 if all buffers are switched simultaneously at system frequency
PDC is the caused by off chip loads which are drawing static currents.
PDC = VO × IO × DCN
VO :
Output voltage drop - usually 0.4 V
IO :
Output current - usually 4 mA
DCN :
Number of output buffers and bidirectional buffers driving off chip loads causing static currents.
172
MB91360G Series
5. Clock Settings
Clock domain
Core
Clock name
CLKB
Max. frequency
setting
Remark
64 MHz
under normal operating conditions (see “4. Run Mode
Current/Power Consumption”) *
32 MHz
for supply voltage between 4.25 and 3.5 V
Resource bus
CLKP
32 MHz
Ext. Bus
CLKT
32 MHz
Clock for CAN
CANCLK
32 MHz
* : F361GA : If the maximum frequency of 64 MHz is set for CLKB, it is not allowed to have an odd division factor
for CLKT.
F362GA : If the maximum frequency of 64 MHz is set for CLKB and an odd division factor for CLKT (3, 5, 7, 9,
11, 13, 15) has been selected, then the option to create an asymmetrical CLKT must be used (set bit 14 of the
F362MD register to “1”) .
173
MB91360G Series
6. Converter Characteristics
• A/D Converter
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Resolution



10
Bit
Conversion error



±5.0
LSB
Non-linearity



±2.5
LSB
Differential Non-linearity



±1.9
LSB
Zero Reading voltage
V0T
AVRL − 3.5
AVRL + 0.5
AVRL + 4.5
LSB
Full scale reading voltage
VFST
AVRH − 5.5
AVRH − 1.5
AVRH + 2.5
LSB
[email protected]

3.0
7.0
mA
IR

1.6
2.6
mA
Input current
Reference voltage current
Remark
overall error
• D/A Converter
Parameter
174
Symbol
Value
Min.
Typ.
Max.
Unit
Resolution



10
Bit
Differential linearity error

−0.9

+0.9
Bit
Remark
MB91360G Series
7. A/D Converter Glossary
• Resolution
The smallest change in analog voltage detected by A/D converter.
• Linearity error
A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000
0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”) .
• Differential linearity error
A deviation of a step voltage for changing the LSB of output code from ideal input voltage.
• Total error
A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error
3FF
1.5 LSB’
3FE
Actual conversion
characteristic
3FD
Digital output
{1 LSB’ × (N − 1) + 0.5 LSB’}
004
VNT
(measured value)
003
Actual conversion
002
Ideal characteristic
001
0.5 LSB’
AVRL
AVRH
Analog input
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
[LSB]
1 LSB’
VOT ’ (Ideal value) = AVRL + 0.5 LSB’ [V]
Total error of digital output N
=
VFST ’ (Ideal value) = AVRH − 1.5 LSB’ [V]
VNT : A voltage for causing transition of digital output from (N − 1) to N
(Continued)
175
MB91360G Series
(Continued)
Linearity error
3FF
Differential linearity error
Ideal characteristic
Actual conversion characteristic
N+1
3FE
{1 LSB × (N − 1) + VOT}
Actual conversion
characteristic
VFST
(measured value)
004
VNT
(measured value)
003
Actual conversion
characteristic
Digital output
Digital output
3FD
N
N−1
V(N + 1)T
(measured value)
002
VNT
(measured value)
Ideal characteristic
N−2
001
Actual conversion
characteristic
VOT (measured value)
AVRL
AVRH
AVRL
Analog input
Analog input
=
Linearity error of digital output N
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
1022
1 LSB’ (ideal value) =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N + 1) T − VNT
1 LSB
[LSB]
−1 [LSB]
[V]
AVRH − AVRL
1022
[V]
VOT : A voltage for causing transition of digital output from (000) H to (001) H
VFST : A voltage for causing transition of digital output from (3FE) H to (3FF) H
VNT : A voltage for causing transition of digital output from (N − 1) H to N
176
AVRH
MB91360G Series
8. Notes on Using A/D Converter
Output impedance of external circuit of analog input under following conditions;
Output impedance of external circuit < 4 kΩ.
If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate
sampling.
• Analog input Equivalent Circuit
Analog input pin
Comparator
RO
C0
RON : 3.6 KΩ
C0 : 30 pF
• Error
As the absolute value of AVRH decreases, relative error increases.
177
MB91360G Series
9. The Time for Power Supply
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Power supply raising slope
∆V/∆t


0.05
V/µs
Power supply raising slope
tR
80


µs
4.2 V
VDD
∆V
0.2 V
∆t
10. AC Characteristics
• Measurement conditions
Parameter
Symbol
Value
Unit
“H” level input voltage
VIH
“L” level input voltage
VIL
“H” level output voltage
VOH
0.5 × VDD
V
“L” level output voltage
VOL
0.5 × VDD
V
“H” level input voltage
VIH
3.0
V
“L” level input voltage
VIL
0
V
“H” level output voltage
VOH
0.5 × VDD
V
“L” level output voltage
VOL
0.5 × VDD
V
according to I/O spec
Load conditions
Output pin
C = 50 pF
178
Conditions
V
V
VDD = 4.25 to 5.25 V,
TA = −40 to +85 °C
VDD = 3.0 to 3.6 V,
TA = −40 to +85 °C
MB91360G Series
• External bus clock
(VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C)
Signal
Symbol
Pin name
CLK cycle
tCYC
CLK rise → CLK fall
CLK fall → CLK rise
Value
Unit
Min.
Max.
CLK
tCPT

ns
tCHCL
CLK
tCYC / 2 − 10
tCYC / 2 + 10
ns
tCLCH
CLK
tCYC / 2 − 10
tCYC / 2 + 10
ns
Note : This is only valid for operation without clock modulator
tCYC
tCHCL
tCLCH
VOH
CLK
VOH
VOL
The values for tCHCL and tCLCH are heavily dependent on the load connected to the CLK pin. The following diagrams
show this dependency for the worst case situation. The first diagram shows the situation for even division ratios
between CLKB and CLKT, the second diagram shows this for odd division ratios between CLKB and CLKT
(ASYMCLKT bit is not set) .
It has to note that when the combination of CLK frequency and load at CLK pin is such that rise or fall times are
longer than tCYC / 2 the duty ratio can get worse.
179
MB91360G Series
Even CLKB/CLKT division ratios :
deviation of tCHCL from tCYC / 2 versus load
14,0
12,0
10,0
5V
6,0
3.3 V
ns
8,0
4,0
2,0
0,0
0
20
40
60
80
100
120
pF
Odd CLKB/CLKT division ratios :
deviation of tCHCL from tCYC / 2 versus load
14,0
12,0
10,0
5V
6,0
3.3 V
ns
8,0
4,0
2,0
0,0
0
20
40
60
pF
180
80
100
120
MB91360G Series
• External bus interface
Signal
(VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C)
Symbol
Pin name
CS6 to CS0 delay time
tCHCSL
CS6 to CS0 delay time
tCHCSH
CLK
CS6 to CS0
Address delay time
tCHAV
Data delay time
tCHDV
RD delay time
tCLRL
RD delay time
tCLRH
WR3 to WR0 delay time
tCLWL
WR3 to WR0 delay time
tCLWH
Effective address ⇒
Effect data input time
tAVDV
RD (fall) →
Effect data input time
tRLDV
Data set up →
RD (rise) time
tDSRH
RD (rise) → Data hold time
tRHDX
AS delay time
tCHASL
AS delay time
tCHASH
Value
Unit
Min.
Max.

15
ns

15
ns
CLK
A20 to A0

20
ns
CLK
D31 to D0

16
ns

15
ns

15
ns

15
ns

15
ns

3 / 2 × tCYC − 30
ns

tCYC − 20
ns
25

ns
0

ns
AS

15
ns
AS

15
ns
CLK
RD
CLK
WR3 to WR0
A20 to A0
D31 to D0
RD
D31 to D0
181
MB91360G Series
tCYC
CLK
VOH
VOH
VOL
tCHASH
tCHASL
AS
VOH
VOL
VOH
VOL
tCHCSH
tCHCSL
CS0 - CS6
VOH
VOL
tCHAV
VOH
VOL
A23 - A00
tCLRL
tCLRH
RD
VOH
VOL
tRLDV
tRHDX
tDSRH
tAVDV
VOH
VOL
D31 - D00
tCLWL
WR3 - WR0
VOL
tCHDV
D31 - D00
182
VOH
VOL
VOH
VOL
tCLWH
VOH
MB91360G Series
• RDY
(VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C)
Signal
Symbol
Pin name
RDY setup
tRDYS
RDY hold
tRDYH
Value
Unit
Min.
Max.
CLK
RDY
16

ns
CLK
RDY
0

ns
tCYC
CLK
VOH
VOL
VOH
tRDYS tRDYH
RDY
case 1
RDY
case 2
VIL
VIH
VOL
tRDYS tRDYH
VIH
VIL
183
MB91360G Series
• BGRNT
(VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C)
Signal
Symbol
Pin name
BGRNT
tCHBGL
BGRNT
tCHBGH
CLK
BGRNT
Bus access enabled
BGRNT falling
tXHAL
Bus access disabled
BGRNT rising
tHAHV
Value
Max.

10
ns

10
ns
tcyc − 15
tcyc + 15
ns
tcyc − 15
tcyc + 15
ns
BGRNT
tCYC
CLK
VOH
VOH
VOH
BRQ
tCHBGH
tCHBGL
VOH
BGRNT
tXHAL
Other
Ports
184
Unit
Min.
tHAHV
High-Z
MB91360G Series
• DMA
(VDD = 4.25 V to 5.25 V, TA = −40 °C to +85 °C)
Signal
Symbol
Pin name
DREQ
tDRWH
DSTP
DACK
Unit
Min.
Max.
DREQ0
5tCYC

ns
tDSWH
DSTP0*
5tCYC

ns
tCLDL
CLK
DACK0

20

20

20

20
tCLDH
tCLEL
DEOP
Value
CLK
DEOP0
tCLEH
ns
ns
tCYC
CLK
tCLDL
tCLDH
DACK0
tCLEL
tCLEH
DEOP0
tDSWH
DSTP0
DREQ0
tDRWH
* : DSTP and DEOP share a pin. The pin is possible to change DSTP and DEOP functions using a port function
register.
185
MB91360G Series
■ PACKAGE THERMAL RESISTANCE INFORMATION
Thermal Resistance [ °C/W]
Package
Theta-ja
1 m/s
3 m/s
FPT-208P-M04
16
13
11
2.5
PGA-401C-A02
16
8.5
5.5

■ ORDERING INFORMATION
Part number
186
Theta-jc
0 m/s
Package
MB91FV360GACR
401-pin Ceramic PGA
(PGA-401C-A02)
MB91F361GAPFVS
208-pin Plastic QFP
(FPT-208P-M04)
MB91F362GAPFVS
208-pin Plastic QFP
(FPT-208P-M04)
Remarks
MB91360G Series
■ PACKAGE DIMENSIONS
401-pin ceramic PGA
(PGA-401C-A02)
48.26 ± 0.55 SQ
(1.900 ± .022)
2.54 (.100) TYP
0.40 ± 0.10
DIA
(.016 ± .004)
1.00 (.039) DIA TYP
(4 PLCS)
45.72 (1.800)
REF
INDEX AREA
1.02 (.040) C TYP
(4 PLCS)
1.20 ± 0.25
(.047 ± .010)
EXTRA INDEX PIN
3.40 ± 0.40
(.134 ± .016)
5.27 (.207)
MAX
C
1994 FUJITSU LIMITED R401002SC-2-2
Dimensions in mm (inches).
187
MB91360G Series
208-pin plastic QFP
(FPT-208P-M04)
Note : Pins width and pins thickness include plating thickness.
30.60±0.20(1.205±.008)SQ
28.00±0.10(1.102±.004)SQ
+0.03
0.17 –0.08
156
+.001
.007 –.003
105
157
104
0.08(.003)
Details of "A" part
+0.20
3.75 –0.30
+.008
.148 –.012
(Mounting height)
+0.10
0.40 –0.15
+.004
INDEX
0°~8°
208
LEAD No.
53
1
52
0.50(.020)
C
2000 FUJITSU LIMITED F208020S-c-2-3
0.22±0.05
(.009±.002)
0.08(.003)
"A"
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
.016 –.006
(Stand off)
0.25(.010)
M
Dimensions in mm (inches).
Note : The design may be modified changed without notice, contact to Fujitsu sales division when using the device.
188
MB91360G Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3353
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmal.fujitsu.com/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0107
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, and
manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use,
and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks
or dangers that, unless extremely high safety is secured, could have
a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.