HITACHI HM5225645F

HM5225645F-B60
HM5225325F-B60
256M LVTTL interface SDRAM
100 MHz
1-Mword × 64-bit × 4-bank/2-Mword × 32-bit × 4-bank
PC/100 SDRAM
ADE-203-1014C (Z)
Rev. 1.0
Oct. 1, 1999
Description
The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word × 64-bit × 4-bank. The Hitachi
HM5225325F is a 256-Mbit SDRAM organized as 2097152-word × 32-bit × 4-bank. All inputs and outputs
are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
•
•
•
•
•
•
•
•
•
•
•
Single chip wide bit solution (× 64/× 32)
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Extremely small foot print: 1.27 mm pitch
 Package: BGA (BP-108)
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 4/8/full page
2 variations of burst sequence
 Sequential (BL = 4/8/full page)
 Interleave (BL = 4/8)
Programmable CAS latency: 2/3
Byte control by DQMB
HM5225645F-B60, HM5225325F-B60
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
 Auto refresh
 Self refresh
• Full page burst length capability
 Sequential burst
 Burst stop capability
Ordering Information
Type No.
Frequency
CAS latency
Package
HM5225645FBP-B60*
100 MHz
3
14 mm × 22 mm 108 bump BGA (BP-108)
HM5225325FBP-B60*
100 MHz
3
Note: 66 MHz operation at CAS latency = 2.
2
HM5225645F-B60, HM5225325F-B60
Pin Arrangement (HM5225645F)
108-bump BGA
1
2
3
4
5
6
7
8
9
A
DQ63
DQ62
DQ49
DQ48
VSS
DQ47
DQ46
DQ33
DQ32
B
DQ61
DQ60
DQ51
DQ50
VCC
DQ45
DQ44
DQ35
DQ34
C
DQ59
DQ58
DQ53
DQ52
VCC
DQ43
DQ42
DQ37
DQ36
D
DQ57
DQ56
DQ55
DQ54
VSS
DQ41
DQ40
DQ39
DQ38
E
DQ
MB7
DQ
MB6
DQ
MB5
DQ
MB4
F
CKE
VCC
RAS
WE
G
A12
VCC
A10
A13
H
A7
A5
VCC
A1
J
A4
VSS
A2
A3
K
A8
A6
VSS
A0
L
A11
VSS
A9
CS
M Open
CLK
VCC
CAS
N
DQ
MB0
DQ
MB1
DQ
MB2
DQ
MB3
P
DQ6
DQ7
DQ8
DQ9
VSS
DQ22
DQ23
DQ24
DQ25
R
DQ4
DQ5
DQ10
DQ11
VCC
DQ20
DQ21
DQ26
DQ27
T
DQ2
DQ3
DQ12
DQ13
VCC
DQ18
DQ19
DQ28
DQ29
U
DQ0
DQ1
DQ14
DQ15
VSS
DQ16
DQ17
DQ30
DQ31
(Top view)
3
HM5225645F-B60, HM5225325F-B60
Pin Description (HM5225645F)
Pin name
Function
A0 to A13
Address input
Row address
A0 to A11
Column address
A0 to A7
Bank select address A12/A13 (BS)
DQ0 to DQ63
Data-input/output
CS
Chip select
RAS
Row address strobe command
CAS
Column address strobe command
WE
Write enable
DQMB0 to DQMB7
Byte data mask* 1
CLK
Clock input
CKE
Clock enable
VCC
Power supply
VSS
Ground
Open
Open* 2
Note:
4
1. DQMB0: DQ0 to DQ7
DQMB1: DQ8 to DQ15
DQMB2: DQ16 to DQ23
DQMB3: DQ24 to DQ31
DQMB4: DQ32 to DQ39
DQMB5: DQ40 to DQ47
DQMB6: DQ48 to DQ55
DQMB7: DQ56 to DQ63
2. Don’t connect. Internally connected with die.
HM5225645F-B60, HM5225325F-B60
Pin Arrangement (HM5225325F)
108-bump BGA
1
2
3
4
5
6
7
8
9
A
DQ31
NC
NC
DQ24
VSS
DQ23
NC
NC
DQ16
B
DQ30
NC
NC
DQ25
VCC
DQ22
NC
NC
DQ17
C
DQ29
NC
NC
DQ26
VCC
DQ21
NC
NC
DQ18
D
DQ28
NC
NC
DQ27
VSS
DQ20
NC
NC
DQ19
E
DQ
MB3
NC
DQ
MB2
NC
F
CKE
VCC
RAS
WE
G
A12
VCC
A10
A13
H
A7
A5
VCC
A1
J
A4
VSS
A2
A3
K
A8
A6
VSS
A0
L
A11
VSS
A9
CS
M Open
CLK
VCC
CAS
N
NC
DQ
MB0
NC
DQ
MB1
P
DQ3
NC
NC
DQ4
VSS
DQ11
NC
NC
DQ12
R
DQ2
NC
NC
DQ5
VCC
DQ10
NC
NC
DQ13
T
DQ1
NC
NC
DQ6
VCC
DQ9
NC
NC
DQ14
U
DQ0
NC
NC
DQ7
VSS
DQ8
NC
NC
DQ15
(Top view)
5
HM5225645F-B60, HM5225325F-B60
Pin Description (HM5225325F)
Pin name
Function
A0 to A13
Address input
Row address
A0 to A11
Column address
A0 to A8
Bank select address A12/A13 (BS)
DQ0 to DQ31
Data-input/output
CS
Chip select
RAS
Row address strobe command
CAS
Column address strobe command
WE
Write enable
DQMB0 to DQMB3
Byte data mask* 1
CLK
Clock input
CKE
Clock enable
VCC
Power supply
VSS
Ground
Open
Open* 2
NC
No connection*3
Note:
6
1. DQMB0: DQ0 to DQ7
DQMB1: DQ8 to DQ15
DQMB2: DQ16 to DQ23
DQMB3: DQ24 to DQ31
2. Don’t connect. Internally connected with die.
3. Not internally connected with die.
HM5225645F-B60, HM5225325F-B60
Block Diagram (HM5225645F)
A0 to A13
CS
RAS
CAS
WE
CLK
CKE
14
64-Mbit SDRAM
4M × 16
2
8
16
64-Mbit SDRAM
4M × 16
2
16
64-Mbit SDRAM
4M × 16
2
16
64-Mbit SDRAM
4M × 16
2
16
DQMB 0 to
DQMB 7
64
DQ 0 to DQ 63
Block Diagram (HM5225325F)
A0 to A13
CS
RAS
CAS
WE
CLK
CKE
14
64-Mbit SDRAM
8M × 8
4
DQMB 0 to
DQMB 3
32
DQ 0 to DQ 31
1
8
64-Mbit SDRAM
8M × 8
1
8
64-Mbit SDRAM
8M × 8
1
8
64-Mbit SDRAM
8M × 8
1
8
7
HM5225645F-B60, HM5225325F-B60
Power-up Sequence and Initialization Sequence
Initialization sequence
Power up sequence
100 µs
VCC
200 µs
0V
CKE, DQMB
Low
CLK
Low
CS, DQ
Low
Power stabilize
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to V SS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Operating temperature
Topr
0 to +70 (Tj max = 110)
°C
Storage temperature
Tstg
–55 to +125
°C
Note:
1. Respect to V SS
DC Operating Conditions (Tcase = 0 to +70°C [Tj max = 110°C])
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC
3.0
3.6
V
1, 2
VSS
0
0
V
3
Input high voltage
VIH
2.0
VCC + 0.3
V
1, 4
Input low voltage
VIL
–0.3
0.8
V
1, 5
Notes: 1.
2.
3.
4.
5.
8
All voltage referred to VSS
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS .
HM5225645F-B60, HM5225325F-B60
DC Characteristics
(Tcase = 0 to 70°C [Tj max = 110°C]), VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5225645F)
HM5225645F
-B60
Parameter
Symbol
Min
Max
Unit
Test conditions
Notes
Operating current
(CAS latency = 2)
—
200
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CAS latency = 3)
I CC1
—
220
mA
Standby current in power down
I CC2P
—
12
mA
CKE = VIL,
t CK = 12 ns
6
Standby current in power down
(input signal stable)
I CC2PS
—
8
mA
CKE = VIL, t CK = ∞
7
Standby current in non power
down
I CC2N
—
64
mA
CKE, CS = VIH,
t CK = 12 ns
4
Standby current in non power
down (input signal stable)
I CC2NS
—
36
mA
CKE = VIH, t CK = ∞
9
Active standby current in power
down
I CC3P
—
16
mA
CKE = VIL,
t CK = 12 ns
1, 2, 6
Active standby current in power
down (input signal stable)
I CC3PS
—
12
mA
CKE = VIL, t CK = ∞
2, 7
Active standby current in non
power down
I CC3N
—
80
mA
CKE, CS = VIH,
t CK = 12 ns
1, 2, 4
Active standby current in non
power down (input signal stable)
I CC3NS
—
60
mA
CKE = VIH, t CK = ∞
2, 9
I CC4
—
220
mA
t CK = min, BL = 4
1, 2, 5
I CC4
—
270
mA
Refresh current
I CC5
—
380
mA
t RC = min
3
Self refresh current
I CC6
—
4
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
Self refresh current (L-version)
I CC6
—
1.6
mA
Input leakage current
I LI
–4
4
µA
0 ≤ Vin ≤ VCC
Output leakage current
I LO
–6
6
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
V
I OH = –4 mA
Output low voltage
VOL
—
0.4
V
I OL = 4 mA
Burst operating current
(CAS latency = 2)
(CAS latency = 3)
9
HM5225645F-B60, HM5225325F-B60
DC Characteristics
(Tcase = 0 to 70°C [Tj max = 110°C]), VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5225325F)
HM5225325F
-B60
Parameter
Symbol
Min
Max
Unit
Test conditions
Notes
Operating current
(CAS latency = 2)
—
180
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CAS latency = 3)
I CC1
—
200
mA
Standby current in power down
I CC2P
—
12
mA
CKE = VIL,
t CK = 12 ns
6
Standby current in power down
(input signal stable)
I CC2PS
—
8
mA
CKE = VIL, t CK = ∞
7
Standby current in non power
down
I CC2N
—
64
mA
CKE, CS = VIH,
t CK = 12 ns
4
Standby current in non power
down (input signal stable)
I CC2NS
—
36
mA
CKE = VIH, t CK = ∞
9
Active standby current in power
down
I CC3P
—
16
mA
CKE = VIL,
t CK = 12 ns
1, 2, 6
Active standby current in power
down (input signal stable)
I CC3PS
—
12
mA
CKE = VIL, t CK = ∞
2, 7
Active standby current in non
power down
I CC3N
—
80
mA
CKE, CS = VIH,
t CK = 12 ns
1, 2, 4
Active standby current in non
power down (input signal stable)
I CC3NS
—
60
mA
CKE = VIH, t CK = ∞
2, 9
I CC4
—
200
mA
t CK = min, BL = 4
1, 2, 5
I CC4
—
250
mA
Refresh current
I CC5
—
380
mA
t RC = min
3
Self refresh current
I CC6
—
4
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
Self refresh current (L-version)
I CC6
—
1.6
mA
Input leakage current
I LI
–4
4
µA
0 ≤ Vin ≤ VCC
Output leakage current
I LO
–6
6
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
V
I OH = –4 mA
Output low voltage
VOL
—
0.4
V
I OL = 4 mA
Burst operating current
(CAS latency = 2)
(CAS latency = 3)
10
HM5225645F-B60, HM5225325F-B60
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are V IH or VIL fixed.
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Min
Max
Unit
Notes
Input capacitance (CLK)
CI1
10
14
pF
1, 2, 4
Input capacitance
(Input except DQM)
CI2
10
14
pF
1, 2, 4
Input capacitance (DQM)
CI3
2.5
5
pF
1, 2, 4
Output capacitance (DQ)
CO
3
5
pF
1, 2, 3, 4
Notes: 1.
2.
3.
4.
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Dout.
This parameter is sampled and not 100% tested.
11
HM5225645F-B60, HM5225325F-B60
AC Characteristics
(Tcase = 0 to 70°C [Tj max = 110°C]), VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HM5225645F/HM5225325F
-B60
Parameter
HITACHI
Symbol
PC/100
Symbol
Min
Max
Unit
Notes
System clock cycle time
(CAS latency = 2)
t CK
Tclk
15
—
ns
1
(CAS latency = 3)
t CK
Tclk
10
—
ns
CLK high pulse width
t CKH
Tch
3
—
ns
1
CLK low pulse width
t CKL
Tcl
3
—
ns
1
Access time from CLK
(CAS latency = 2)
t AC
Tac
—
8
ns
1, 2
(CAS latency = 3)
t AC
Tac
—
6
ns
Data-out hold time
t OH
Toh
3
—
ns
1, 2
CLK to Data-out low impedance
t LZ
2
—
ns
1, 2, 3
CLK to Data-out high impedance
(CAS latency = 2, 3)
t HZ
—
6
ns
1, 4
Input setup time
t AS , t CS, t DS, Tsi
t CES
2
—
ns
1, 5, 6
CKE setup time for power down
exit
t CESP
2
—
ns
1
Input hold time
t AH, t CH, t DH, Thi
t CEH
1
—
ns
1, 5
Tpde
Ref/Active to Ref/Active command t RC
period
Trc
70
—
ns
1
Active to Precharge command
period
t RAS
Tras
50
120000
ns
1
Active command to column
command (same bank)
t RCD
Trcd
20
—
ns
1
Precharge to active command
period
t RP
Trp
20
—
ns
1
Write recovery or data-in to
precharge lead time
t DPL
Tdpl
10
—
ns
1
Active (a) to Active (b) command
period
t RRD
Trrd
20
—
ns
1
Transition time (rise and fall)
tT
1
5
ns
Refresh period
t REF
—
64
ms
12
HM5225645F-B60, HM5225325F-B60
Notes: 1.
2.
3.
4.
5.
6.
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is CL = 50 pF.
t LZ (min) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES define CKE setup time to CLK rising edge except power down exit command.
t AS /tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM.
t DS/tDH: Data-in, tCES/tCEH: CKE
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
2.4 V
input
0.4 V
I/O
2.0 V
0.8 V
CL
t
T
tT
13
HM5225645F-B60, HM5225325F-B60
Package Dimensions
HM5225645FBP Series
HM5225325FBP Series (BP-108)
Unit: mm
0.20
Preliminary
-A-
-C-
4×
A
0.35 C
4×C1.2
14.00
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.15 C
1.27
22.00
21.0 ± 0.10
Pin 1 Index
-B-
1.27
2.35 Max
0.60
2.10
13.0 ± 0.10
108× φ0.75
φ0.30 M C A B
φ0.15 M C
Details of the part A
14
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
BP-108
—
—
1.2 g
HM5225645F-B60, HM5225325F-B60
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
: http:semiconductor.hitachi.com/
Europe
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan)
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
15
HM5225645F-B60, HM5225325F-B60
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
0.0
Feb. 1, 1999
Initial issue
S. Hatano
S. Hatano
0.1
Feb. 19, 1999 Pin arrangement
Correct pin No. to JEDEC standard
S. Hatano
S. Hatano
S. Hatano
S. Hatano
Package dimenssion
Correct illustration and indexes
0.2
Apr. 1, 1999
1.0
Oct. 1, 1999
Ordering information
Correct error of type No.
Programmable CAS latency: 3 to 2/3
Ordering information
Addition of note
Pin description
Addition of note 1
DC Characteristics (HM5225645F)
I CC1 max (CL = 2): 280 mA to 200 mA
I CC1 max (CL = 3): 300 mA to 220 mA
I CC4 max (CL = 2): 280 mA to 220 mA
I CC4 max (CL = 3): 360 mA to 270 mA
I CC5 max: 460 mA to 380 mA
DC Characteristics (HM5225325F)
I CC1 max (CL = 2): 260 mA to 180 mA
I CC1 max (CL = 3): 280 mA to 200 mA
I CC4 max (CL = 2): 260 mA to 200 mA
I CC4 max (CL = 3): 320 mA to 250 mA
I CC5 max: 460 mA to 380 mA
Capacitance
CI1 max: 16 pF to 14 pF
CI2 max: 20 pF to 14 pF
CO min: 4 pF to 3 pF
CO max: 6.5 pF to 5 pF
Package dimension
Change tolerance of height
16