MICREL MIC59P60BWM

MIC59P60
Micrel
MIC59P60
8-Bit Serial-Input Protected Latched Driver
General Description
Features
The MIC59P60 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common CLEAR, STROBE, CLOCK, SERIAL DATA INPUT,
and OUTPUT ENABLE functions. Similar to the MIC5842,
additional protection circuitry supplied on this device includes
thermal shutdown, under voltage lockout (UVLO), and overcurrent shutdown.
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The bipolar/CMOS combination provides an extremely lowpower latch with maximum interface flexibility. The MIC59P60
has open-collector outputs capable of sinking 500mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply,
where the negative supply is down to –20V and may be
paralleled for higher load current capability.
3.3 MHz Minimum Data-Input Rate
Output Current Shutdown (500mA Typical)
Under Voltage Lockout
Thermal Shutdown
Output Fault Flag
CMOS, PMOS, NMOS, and TTL Compatible
Internal Pull-Up/Pull-Down Resistors
Low Power CMOS Logic and Latches
High Voltage Current Sink Outputs
Output Transient-Protection Diodes
Single or Split Supply Operation
Ordering Information
Part Number
Using a 5V logic supply, the MIC59P60 will typically operate
at better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compatible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors. By using the serial data
output, drivers may be cascaded for interface applications
requiring additional drive lines.
Temperature Range
Package
MIC59P60BN
–40°C to +85°C
20-Pin Plastic DIP
MIC59P60BV
–40°C to +85°C
20-Pin PLCC
MIC59P60BWM
–40°C to +85°C
20-Pin Wide SOIC
Each of these eight outputs has an independent over current
shutdown of 500 mA. Upon over-current shutdown, the
affected channel will turn OFF and the flag will go low until VDD
is cycled or the ENABLE/RESET pin is pulsed high. Current
pulses less than 2µs will not activate current shutdown.
Temperatures above 165°C will shut down the device and
activate the error flag. The UVLO circuit prevents operation
at low VDD; hysteresis of 0.5V is provided.
Functional Diagram
Pin Configuration
(DIP and SOIC)
SERIAL
DATA IN
4
VSS
CLEAR
2
CLOCK
3
SERIAL DATA IN
4
VSS
5
VDD
6
SERIAL DATA OUT
7
STROBE
8
13 OUTPUT 7
OUTPUT
ENABLE/RESET
9
12 OUTPUT 8
7
SERIAL DATA OUT
20 FLAG
6
VDD
8
STROBE
LATCHES
5
9
OUTPUT
ENABLE/RESET
1
UVLO
ILIMIT
11
K
19
18
17
16
15
14
13
12
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8
SUB
2
10
VEE
19 OUTPUT 1
SUB
8-BIT SERIAL–PARALLEL SHIFT REGISTER
MOS
BIPOLAR
THERMAL
SHUTDOWN
VEE
I LIMIT
20 FLAG
VEE 10
18 OUTPUT 2
SUB
17 OUTPUT 3
LATCHES
3
1
SHIFT REGISTER
CLOCK
THERMAL
SHUTDOWN
CLEAR
16 OUTPUT 4
15 OUTPUT 5
14 OUTPUT 6
UVLO
11 K
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
January 2000
1
MIC59P60
CLEAR
FLAG
OUT 1
PLCC Pin
Configuration
VEE
Micrel
CLOCK
MIC59P60
3
2
1
20
19
Absolute Maximum Ratings VSS = 0; TA = 25°C
SERIAL DATA IN
4
18
OUT 2
VSS
5
17
OUT 3
VDD
6
16
OUT 4
SERIAL DATA OUT
7
15
OUT 5
STROBE
8
14
OUT 6
Typical Inputs
9
10
11
12
13
OE/RESET
VEE
K
OUT 8
OUT 7
MIC59P60BV
V DD
CLOCK
SERIAL
DATA IN
Output Voltage (VCE) .................................................... 80V
Output Voltage (VCE(SUS)) ............................... 50V, Note 1
VDD with Reference to VSS ........................................... 15V
VDD with Reference to VEE ........................................... 25V
Emitter Supply Voltage (VEE) ...................................... –20V
Input Voltage (VIN) ............................... –0.3V to VDD+0.3V
Protected Current ............................................ 1.5A, Note 2
Power Dissipation (PD)
Plastic DIP (N) ......................................................... 2.0W
Derate above TA = +25°C ............................ 20mW/°C
PLCC (V) .................................................................1.4W
Derate above TA = +25°C ............................ 14mW/°C
Wide SOIC (WM) .................................................... 1.2W
Derate above TA = +25°C ............................ 12mW/°C
Operating Temperature (TA)
Plastic DIP (N), PLCC (V), SOIC (WM) .. –40°C to +85°C
Storage Temperature (TS) ....................... –65°C to +150°C
Junction Temperature (TJ) ...................................... +150°C
ESD ......................................................................... Note 3
V DD
Note 1:
Note 2:
STROBE
OUTPUT
ENABLE
Note 3:
For inductive load applications.
Each channel. VEE connection must be designed to minimize
inductance and resistance.
Devices are input-static protected but can be damaged by
extremetly high static charges.
V SS
V SS
K
Typical Output Driver
OUT
N
3K
Pin Description
V
EE
SUB
Pin
Name
1
CLEAR
2,10
VEE
3
CLOCK
4
SERIAL DATA IN
5
VSS
Logic reference (Ground) pin.
6
VDD
Logic Positive Supply voltage.
7
SERIAL DATA OUT
8
STROBE
9
OUTPUT ENABLE/RESET
11
K
12—19
OUTPUT N
20
FLAG
MIC59P60
Description
Sets All Latches OFF (open).
Output Ground (Substrate). Most negative voltage in the system connects
here.
Serial Data Clock. A CLEAR must also be clocked into the latches.
Serial Data Input pin.
Serial Data Output pin. (Flow through).
Output Strobe pin. Loads output latches when High. A STROBE is needed
to CLEAR latches.
When Low, Outputs are active. When High, device is inactive and reset
from a fault condition. An under voltage condition emulates a high OE/
RESET input.
Transient suppression diode's cathode common pin.
Open Collector outputs 8 through 1.
Error Flag. Flag is Low upon Overcurrent Fault or Overtemperature fault.
OUTPUT ENABLE/RESET must be pulled high to reset the flag and fault
condition.
2
January 2000
MIC59P60
Micrel
Electrical Characteristics
VDD = 5V, VSS = VEE = 0V; TA = +25°C; unless noted.
Limits
Characteristic
Symbol
Test Conditions
Output Leakage Current
ICEX
Collector-Emitter
Saturation Voltage
VCE(SAT)
VOUT = 80V
VOUT = 80V, TA = +70°C
IOUT = 100mA
IOUT = 200mA
IOUT = 350mA
Collector-Emitter
Sustaining Voltage
VCE(SUS)
IOUT = 350mA, L = 2mH
Input Voltage
VIN(0)
Min.
Typ.
Max.
Unit
50
µA
1.1
1.3
1.6
V
100
0.9
1.1
1.3
50
V
1.0
VIN(1)
VDD = 12V
VDD = 10V
VDD = 5.0V, Note 4
Input Resistance
RIN
VDD = 12V
VDD = 10V
VDD = 5.0V
Flag Output Current
IOL
Flag Output Leakage
Supply Current
10.5
8.5
3.5
50
50
50
V
V
200
300
600
kΩ
VOL = 0.4V
15
mA
IOH
VOH = 12.0V
50
nA
IDD(ON)
All Drivers ON, VDD = 12V
All Drivers ON, VDD = 10V
All Drivers ON, VDD = 5.0V
6.4
6.0
4.6
10.0
9.0
7.5
mA
IDD (1 OUTPUT) One Driver ON, All others OFF, VDD = 12V
One Driver ON, All others OFF, VDD = 10V
One Driver ON, All others OFF, VDD = 5V
3.1
2.9
2.3
4.5
4.5
3.6
mA
IDD(OFF)
All Drivers OFF, VDD = 12V
All Drivers OFF, VDD = 10V
All Drivers OFF, VDD = 5.0V
2.6
2.4
1.9
4.2
3.6
3.0
mA
Clamp Diode
Leakage Current
IR
VR = 80V
50
µA
Clamp Diode
Forward Voltage
VF
IF = 350mA
2.0
V
Over Current
Shutdown Threshold
ILIM
Start Up Voltage
VSU
Minimum Supply (VDD)
VDD MIN
1.7
500
Note 5
mA
3.5
4.0
4.5
V
3.0
3.5
4.0
V
Thermal Shutdown
165
°C
Thermal Shutdown Hysteresis
10
°C
Note 4: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".
Note 5: Undervoltage lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V
January 2000
3
MIC59P60
MIC59P60
Micrel
CLOCK
A
D
B
DATA IN
E
F
C
STROBE
OUTPUT
ENABLE
G
OUT N
Timing Conditions
(TA = +25°C, Logic Levels are VDD and VSS, VDD = 5V)
A.
B.
C.
D.
E.
F.
G.
Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns
Minimum Data Active Time After Clock Pulse (Data Hold Time) .............................................................................. 75 ns
Minimum Data Pulse Width ..................................................................................................................................... 150 ns
Minimum Clock Pulse Width .................................................................................................................................... 150 ns
Minimum Time Between Clock Activation and Strobe ............................................................................................. 300 ns
Minimum Strobe Pulse Width ................................................................................................................................... 100 ns
Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Holding CLEAR high results in a data
logic "0" being clocked into the shift register, turning off respective channels.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OE/RESET pulse
resets the FLAG and the output after a current shutdown fault. Over-temperature faults are not latched and require no reset
pulse.
MIC59P60 Truth Table
Serial
Data
Input
Shift Register Contents
I2
I3 ……
I8
Serial
Data
Output
H
H
R1
R2 ……
R7
R7
L
L
R1
R2 ……
R7
R7
R1
R2
R3 ……
R8
R8
O
O
O ……
O
L
X
X
X ……
X
X
P1
P2
P3 ……
P8
P8
Clear Clock
Input Input
X
H
I1
Latch Contents
I2
I3
……
Output Contents
Output
I8 Enable I1 I2
I3 …… I8
L
R1 R2
R3
……
R8
H
P1 P2
P3
……
P8
L
P1
P2
P3 ……P8
X
X
……
X
H
H
H
H …… H
Strobe
Input
I1
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
MIC59P60
4
January 2000
MIC59P60
Micrel
IL = 100mA
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0
50
100
TEMPERATURE (°C)
Output Saturation
Voltage vs. Temperature
0.7
0.6
0.5
-50
IL = 350mA
VDD = 12V
IL = 100mA
0
50
100
TEMPERATURE (°C)
January 2000
150
ALL OUTPUTS ON
VDD = 5V
3
2
1
0
–50
150
0.60
7
6
ALL OUTPUTS OFF
0
50
100
TEMPERATURE (°C)
150
Supply Current
vs. Temperature
ALL OUTPUTS ON
VDD = 12V
3
2
ALL OUTPUTS OFF
1
0
–50
0
50
100
TEMPERATURE (°C)
5
0.55
VDD = 5V
0.50
0.45
150
VDD = 12V
0.40
0.35
–50
20
5
4
SHUTDOWN THRESHOLD (A)
VDD = 5V to 12V
4
Current Shutdown
Threshold vs. Temperature
Supply Current
vs. Temperature
CURRENT LIMIT DELAY (µS)
IL = 350mA
0.7
0.6
0.5
–50
5
SUPPLY CURRENT (mA)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
Output Saturation
Voltage vs. Temperature
SUPPLY CURRENT (mA)
SATURATION VOLTAGE (V)
SATURATION VOLTAGE (V)
Typical Characteristic Curves
0
50
100
TEMPERATURE (°C)
150
Current Shutdown
Delay vs. Output Current
18
16
14
12
10
8
6
4
VDD = 12V
2 VDD = 5V
0
0.3 0.4 0.5 0.6 0.7 0.8
OUTPUT CURRENT (A)
0.9
MIC59P60
MIC59P60
Micrel
Maximum Allowable Duty Cycle (Plastic DIP)
VDD = 5.0V
VDD = 12V
Number of Outputs ON
(IOUT = 200mA
Max. Allowable Duty Cycle at Ambient Temperature of
VDD = 5.0V)
25°C
40°C
50°C
60°C
70°C
8
85%
72%
64%
55%
46%
7
97%
82%
73%
63%
53%
6
100%
96%
85%
73%
62%
5
100%
100%
100%
88%
75%
4
100%
100%
100%
100%
93%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
Number of Outputs ON
(IOUT = 200mA
Max. Allowable Duty Cycle at Ambient Temperature of
VDD = 12V)
25°C
40°C
50°C
60°C
70°C
8
80%
68%
60%
52%
44%
7
91%
77%
68%
59%
50%
6
100%
90%
79%
69%
58%
5
100%
100%
95%
82%
69%
4
100%
100%
100%
100%
86%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
Typical Applications
Protected Solenoid Driver with Output Enable
+5V
+48V
10k
FLAG
CLEAR
1
22µ
THERMAL
SHUTDOWN
I LIMIT
+
20
19
2
SUB
SERIAL
DATA IN
4
18
5
ENABLE
0.1µ
6
7
17
LATCHES
3
SHIFT REGISTER
CLOCK
15
14
8
13
9
12
10
UVLO
SUB
MIC59P60
16
6
11
January 2000
MIC59P60
Micrel
Hammer Driver
+5V
FLAG
+28V
10k
CLEAR
1
22µ
THERMAL
SHUTDOWN
+
20
I LIMIT
19
2
SUB
4
18
5
6
7
17
LATCHES
3
SHIFT REGISTER
CLOCK
SERIAL
DATA IN
16
28V
15
14
8
13
9
12
0.1µ
10
SUB
11
UVLO
Protected Negative/Positive PIN Diode Driver Transmit/Receive Switch
FLAG
10k
CLOCK
+5V
+75V
DATA IN
1
STROBE
THERMAL
SHUTDOWN
I LIMIT
20
10k
15
SUB
RFC
1000p
18
4
5
0.1µ
6
7
16
Antenna
10k
25
D2
15
RFC
1000p
14
RFC
+75V
13
8
D1
+75V
17
LATCHES
SHIFT REGISTER
3
+5V
Transmitter
19
2
10k
25
1000p
10
0.01µ
+
–5V
January 2000
Receiver
12
9
100µ
SUB
UVLO
D1
(Latch 1)
Receive
OFF
Transmit ACTIVE
11
Diode
D2
(Latch 5)
ACTIVE
OFF
7
RFC
D3
+75V
0.01µ
D3
(Latch 8)
OFF
ACTIVE
PIN Diodes: UM9651
MIC59P60
MIC59P60
Micrel
Package Information
1.070
MAX
(27.178)
PIN 1
0.030-0.110
RAD
(0.762-2.794)
.250±0.005
(6.350±0.127)
0.060±0.005
(1.524±0.127)
0.290-0.320
(7.336-8.128)
0.020
(0.508)
0.040 TYP
(1.016)
0.130±0.005
(3.302±0.127)
0°-10°
0.020 MIN
(0.508)
0.125
MIN
(3.175)
0.100±0.010
(2.540±0.254)
0.018±0.003
(0.457±0.076)
+0.025
–0.015
+0.635
8.255
–0.381
0.325
(
)
20-Pin Plastic DIP (N)
PIN 1
DIMENSIONS:
INCHES (MM)
0.301 (7.645)
0.297 (7.544)
0.027 (0.686)
0.031 (0.787)
0.094 (2.388)
0.090 (2.286)
0.050 (1.270)
TYP
0.016 (0.046)
TYP
0.509 (12.929)
0.505 (12.827)
0.103 (2.616)
0.099 (2.515)
7°
TYP
0.015
R
(0.381)
0.015
(0.381)
SEATING MIN
PLANE
0.297 (7.544)
0.293 (7.442)
0.330 (8.382)
0.326 (8.280)
0.022 (0.559)
0.018 (0.457)
5°
TYP
10° TYP
0.032 (0.813) TYP
0.408 (10.363)
0.404 (10.262)
20-Pin Wide SOP (WM)
MIC59P60
8
January 2000
MIC59P60
Micrel
TOP VIEW
DETAIL A
0.045
0.045
0.050
0.110
0.080
0.027
0.030 DIA
x 0.015 R DEPTH
0.018
0.351
±0.003
0.390
±0.020
SIDE VIEW
BOTTOM VIEW
0.035 R
±0.015
0.310
±.015
0.300
0.045
0.045
DETAIL A
0.170
0.110
20-Pin PLCC (V)
January 2000
9
MIC59P60
MIC59P60
MIC59P60
Micrel
10
January 2000
MIC59P60
January 2000
Micrel
11
MIC59P60
MIC59P60
Micrel
MICREL INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
USA
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
MIC59P60
12
January 2000