DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP FEATURES ■ ■ ■ ■ DESCRIPTION 365ps propagation delay 2.0GHz toggle frequency Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL52 are differential data, differential clock D flip-flops. These devices are functionally equivalent to the E452 devices, with higher performance capabilities. With propagation delays and output transition times significantly faster than the E452, the EL52 is ideally suited for those applications which require the ultimate in AC performance. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs also allow the EL52 to be used as a negative edge triggered device. The EL52 employs input clamping circuitry so that, under open input conditions (pulled down to VEE), the outputs of the device will remain stable. PIN CONFIGURATION/BLOCK DIAGRAM D SY10EL52 SY100EL52 1 8 VCC 7 Q D D 2 CLK 3 6 Q CLK 4 5 VEE Flip-Flop SOIC TOP VIEW TRUTH TABLE(1) PIN NAMES Pin Function D CLK Q D Data Input L Z L CLK Clock Input H Z H Q Data Output NOTE: 1. Z = LOW-to-HIGH transition. Rev.: F 1 Amendment: /0 Issue Date: August, 1998 SY10EL52 SY100EL52 Micrel DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol TA = 0°C TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit IEE Power Supply 10EL Current 100EL — — 21 21 25 25 17 17 21 21 25 25 17 17 21 21 25 25 17 19 21 24 25 29 mA VEE Power Supply 10EL Voltage 100EL –4.75 –4.20 –5.2 –4.5 –5.5 –5.5 –4.75 –4.20 –5.2 –4.5 –5.5 –5.5 –4.75 –4.20 –5.2 –4.5 –5.5 –5.5 –4.75 –4.20 –5.2 –4.5 –5.5 –5.5 V IIH Input HIGH Current — — 150 — — 150 — — 150 — — 150 µA AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 1.8 2.5 — 2.2 2.8 — 2.2 2.8 — 2.2 2.8 — GHz fMAX Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output CLK 235 335 515 275 365 465 275 365 465 320 410 510 tS Set-up Time 125 0 — 125 0 — 125 0 — 125 0 — ps tH Hold Time 150 50 — 150 50 — 150 50 — 150 50 — ps tPW Minimum Pulse Width 400 — — 400 — — 400 — — 400 — — ps 150 — — 150 — — 150 — — 150 — — mV –0.4 –0.4 –0.6 –0.8 — — — — –1.6 –1.2 (3) (3) –0.4 –0.4 –0.6 –0.8 — — — — –1.6 –1.2 (3) (3) –0.4 –0.4 –0.6 –0.8 — — — — –1.6 –1.2 (3) (3) –0.4 –0.4 –0.6 –0.8 — — — — –1.6 –1.2 (3) (3) 225 350 100 225 350 100 225 350 100 225 350 VPP VCMR tr tf Minimum Input Swing(1) Common Mode D (10EL) D (100EL) CLK (10EL) CLK (100EL) Range(2) ps V Output Rise/Fall Times Q 100 (20% to 80%) ps NOTES: 1. Minimum input swing for which AC parameters are guaranteed. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. 3. The lower end of the CMR range is dependent on VEE and is equal to VEE + 3.0V. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10EL52ZC Z8-1 Commercial SY10EL52ZCTR Z8-1 Commercial SY100EL52ZC Z8-1 Commercial SY100EL52ZCTR Z8-1 Commercial 2 SY10EL52 SY100EL52 Micrel 8 LEAD SOIC .150" WIDE (Z8-1) Rev. 03 3 SY10EL52 SY100EL52 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4