MITSUBISHI 〈DIGITAL ASSP〉 MITSUBISHI 〈DIGITAL ASSP〉 M66007P/FP M66007P/FP 12-BIT INPUT EXPANDER 12-BIT INPUT EXPANDER DESCRIPTION The M66007 is a semiconductor integrated circuit providing the 12-bit parallel input-serial output shift register function. This product is completely designed with CMOS to sharply reduce power consumption compared with bipolar or BiCMOS product. The M66007, developed as an input only expander IC necessary for microcomputer periphery, is widely applicable as a data parallel/serial conversion IC. PIN CONFIGURATION (TOP VIEW) LATCH INPUT/ LE/D ↔ SERIAL DATA OUTPUT CLOCK INPUT FEATURES • Control signals of only two pins including LE/D and CLK • Low power consumption of 50 µW/package maximum (Vcc=5V, Ta=25°C at time of standstill) • Schmitt triggered input (LE/D, CLK, D0 to D11) • Wide operating supply voltage range (Vcc=2~6V) • Wide operating temperature range (Ta=–20~75°C) 1 LE/D CLK → 2 CLK D11 15 ← D11 16 VCC D0 D1 PARALLEL DATA INPUT D2 D3 D4 → 3 D0 D10 14 ← D10 → 4 D1 D9 13 ← D9 → 5 D2 D8 12 ← D8 → 6 D3 D7 11 ← D7 → 7 D4 D6 10 ← D6 GND 8 D5 9 ← D5 PARALLEL DATA INPUT Outline 16P4 16P2N-A APPLICATION Parallel/serial data conversion for microcomputer periphery After this, change of CLK from “H” to “L” makes the shift register perform shift operation and LE/D outputs the contents of the shift register from D0 in order. In addition, the shift operation for up to the 12th bit is carried out and then LE/D is switched to the input mode at the falling edge of CLK of the 13th bit. When power is turned on, the input/output mode of LE/D is indeterminate. However, detection of 13 or more falling edges of CLK sets LE/D in the input mode. FUNCTION The M66007 uses a silicon gate CMOS process to achieve low power consumption and high noise margin. For control signals, this IC adopts only the two pins of latch input/serial data output LE/D and clock input CLK. Each bit of shift register of 12-bit parallel input-serial output consists of flip-flop for shift. When LE/D is placed in input mode, CLK is set to “H” and LE/ D changes from “H” to “L”, the status of parallel data inputs D0 to D11 at that time is latched with the flip-flop for shift and LE/ D is switched to output mode to output “L”. BLOCK DIAGRAM Vcc LATCH INPUT/ LE/D SERIAL DATA OUTPUT 1 QP CONTROL CIRCUIT LCLK QN SD CLK SHIFT REGISTER LE SQ CLOCK INPUT CLK Vcc 2 16 D11 D10 D9 D8 D0 Q11 Q10 Q9 Q8 Q0 LE PARALLEL LATCH GND 8 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 D11 D10 D9 12 11 D8 D7 10 D6 9 D5 7 D4 6 D3 5 D2 4 D1 3 D0 PARALLEL DATA INPUT 1 MITSUBISHI 〈DIGITAL ASSP〉 M66007P/FP 12-BIT INPUT EXPANDER DESCRIPTION OF OPERATION (1) When power is turned on, LE/D is placed in input/output indeterminate mode. However, detection of 13 or more of falling edges of CLK sets LE/D in input mode. (2) When LE/D is placed in input mode, and CLK is set to “H”, access starts at a falling edge of LE/D and the status of D 0 to D11 is latched. (3) In addition, LE/D switches from input mode to output mode and then outputs “L”. (4) At a falling edge of CLK from “H” to “L”, data latched in step (2) is shifted sequentially and is then output from LE/D in order of D0 to D11. (5) After the output of 12-bit data of D0 to D 11, LE/D is switched to input mode at the 13th falling edge of CLK to wait for next access. Keep the LE/D pin set to “H” until the next access starts. OPERATION TIMING CHART Power ON Rest sequence (13 clocks or more) 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK (5) (1) LE/D (IN) (OUT) (2) (4) Input/output indeterminate (3) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D0 ~ D11 D11 LE/D input/output mode 2 Indeterminate Input mode (Latch signal) Output mode (Output signal) Input mode MITSUBISHI 〈DIGITAL ASSP〉 M66007P/FP 12-BIT INPUT EXPANDER ABSOLUTE MAXIMUM RATINGS (Ta = 20 ~ 75°C unless otherwise noted) Symbol Parameter Conditions VCC VI VO Supply voltage Input voltage Output voltage IIK Input protection diode current IOK Output incidental diode current ICC Tstg Power/GND Storage temperature Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 –20 20 –20 20 ±20 –60 ~ 150 VI<0V VI>VCC VO<0V VO>VCC VCC, GND Unit V V V mA mA mA °C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Topr Parameter Limits Typ. Min. 2 0 0 –20 Supply voltage Input voltage Output voltage Operating temperature Max. 6 VCC VCC 75 Unit V V V °C ELECTRICAL CHARACTERISTICS (Vcc = 2 ~ 6V unless otherwise noted) Symbol Threshold voltage in positive direction Threshold voltage in negative direction VT+ VT– VOL Low-level output voltage VOH High-level output voltage Maximum output leak current Static consumption current IO ICC Conditions Parameter VO=0.1V, VCC–0.1V, IO=20µA VO=0.1V, VCC–0.1V, IO=20µA IOL=20µA VI=VT+, VT– VCC=4.5V IOL=1mA IOH=–20µA VI=VT+, VT– VCC=4.5V IOH=–1mA VO=VCC VI=VT+, VT– VCC=6V VO=GND VI=VCC, GND, VCC=6V, LE/D=“H” VI=VCC, GND, VCC=6V, LE/D=“L” Limits Ta=25˚C Min. Typ. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.1 0.4 4.4 4.1 1.0 –0.8 10.0 0.8 Ta= –20~75˚C Min. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.1 0.5 4.4 4.0 10.0 –1.2 100.0 1.2 Unit V V V V µA mA µA mA SWITCHING CHARACTERISTICS (Vcc=5V) Symbol fmax tPLH tPHL tPLZ tPHZ Parameter Conditions Maximum repetition frequency Output “L-H”, “H-L” propagation time CLK-LE/D Output “L-Z”, “H-Z” propagation time CLK-LE/D CL=50pF (Note 1) Limits Ta = –20 ~ 75˚C Min. Typ. Max. 2 400 400 400 400 Unit MHz ns ns ns ns 3 MITSUBISHI 〈DIGITAL ASSP〉 M66007P/FP 12-BIT INPUT EXPANDER TIMING REQUIREMENTS (VCC = 5V) Limits Symbol Parameter Conditions CLK pulse width LE/D pulse width (Input mode) CLK set up time for LE/D D0~D11 set up time for LE/D CLK hold time for LE/D D0~D11 hold time for LE/D tw tsu th Ta = –20 ~ 75˚C Min. Typ. Max. 250 250 100 100 200 200 Unit Note 1. Test Circuit Input (1) Characteristics (10%~90%) of pulse generator (PG) tr = 6ns, tf = 6ns (2) Electrostatic capacitance CL includes the floating capacitance of connection and probe input capacitance. VCC VCC RL=1kΩ SW1 PG DUT LE/D SW2 CL 50Ω GND 4 RL=1kΩ Item tPLH tPHL tPLZ tPHZ SW1 Open Open Close Open SW2 Open Open Open Close ns ns ns MITSUBISHI 〈DIGITAL ASSP〉 M66007P/FP 12-BIT INPUT EXPANDER TIMING DIAGRAM tw+ tw– VCL CLK 50% 50% 50% 0V tPZL tPLZ LE/D (OUT) 50% 50% VOL VCC CLK 50% 0V tPLZ LE/D Output mode LE/D Input mode 10% VOL VOH 90% tPHZ VCC CLK 50% tsu 50% 0V th VCC D0~D11 50% 50% 0V tw– 50% LED (IN) tsu VCC 10% th 0V 5 MITSUBISHI 〈DIGITAL ASSP〉 M66007P/FP 12-BIT INPUT EXPANDER PRECAUTIONS FOR APPLICATION 1. The following timing diagram shows the status of MCU port and LE/D pin of the M66007 when power is turned on. When MCU has been reset to make the collision period of MCU and LE/D line of the M66007 as short as possible, place the port (LE/D) in input mode and execute the reset sequence through the port (CLK) promptly to reset the M66007. As shown in the diagram, to prevent the IC from being broken due to collision of the LE/D line in the 1-2 section, set in the LE/D line in series a resistance of a degree to which the transmission speed cannot be affected. Power ON MCU reset 2. When the LE/D pin on each of the MPU and M66007 sides switches from input mode to output mode or from output mode to input mode, the LE/D pin may be placed in high impedance status, resulting in oscillation. To prevent malfunction due to this oscillation, pull up the LE/D line with a high resistance of a degree to which VOH and VOL levels cannot be affected. (with approx. 20kΩ pullup resistance built-in) M66007 reset sequence M66007 RESET Output mode Input mode MCU port (DATA) Input/output indeterminate M66007 LE/D Input/output indeterminate Input mode Input/output indeterminate Output mode Input/output indeterminate MCU port (CLK) 13 clocks or more 2 1 3 Status of MCU and M66007 with Power Turned on Pull-resistance Port (DATA) Serial resistance I/O=LE/D M66007 MCU Port (CLK) I=CLK Connection Example of MCU and M66007 6