Order this document by MC144110/D SEMICONDUCTOR TECHNICAL DATA CMOS LSI MC144110 The MC144110 and MC144111 are low–cost 6–bit D/A converters with serial interface ports to provide communication with CMOS microprocessors and microcomputers. The MC144110 contains six static D/A converters; the MC144111 contains four converters. Due to a unique feature of these DACs, the user is permitted easy scaling of the analog outputs of a system. Over a 5 to 15 V supply range, these DACs may be directly interfaced to CMOS MPUs operating at 5 V. • • • • • • • • P SUFFIX PLASTIC DIP CASE 707 18 1 Direct R–2R Network Outputs Buffered Emitter–Follower Outputs Serial Data Input Digital Data Output Facilitates Cascading Direct Interface to CMOS µP Wide Operating Voltage Range: 4.5 to 15 V Wide Operating Temperature Range: 0 to 85°C Software Information is Contained in Document M68HC11RM/AD DW SUFFIX SOG PACKAGE CASE 751D 20 1 MC144111 P SUFFIX PLASTIC DIP CASE 646 14 1 DW SUFFIX SOG PACKAGE CASE 751G BLOCK DIAGRAM 16 VDD Qn Rn R1 OUT OUT OUT Q1 OUT 1 ORDERING INFORMATION 2R 2R R R R R R 2R 2R 2R 2R 2R MC144110P MC144110DW Plastic DIP SOG Package MC144111P MC144111DW Plastic DIP SOG Package HEX BUFFER (INVERTING) C ENB CLK D * C Q Din HEX LATCH C D 6–BIT SHIFT REGISTER Dout * Transparent Latch REV 1 8/95 Motorola, Inc. 1995 MOTOROLA MC144110•MC144111 1 PIN ASSIGNMENTS MC144110P MC144110DW Din 1 18 VDD Din 1 20 VDD Q1 Out 2 17 Dout Q1 Out 2 19 Dout R1 Out 3 16 R6 Out R1 Out 3 18 R6 Out Q2 Out 4 15 Q6 Out Q2 Out 4 17 Q6 Out R2 Out 5 14 R5 Out R2 Out 5 16 R5 Out Q3 Out 6 13 Q5 Out Q3 Out 6 15 Q5 Out R3 Out 7 12 R4 Out R3 Out 7 14 R4 Out ENB 8 11 Q4 Out ENB 8 13 Q4 Out VSS 9 10 CLK VSS 9 12 CLK 10 11 NC NC MC144111P MC144111DW Din 1 14 VDD Din 1 16 VDD Q1 Out 2 13 Dout Q1 Out 2 15 Dout R1 Out 3 14 R4 Out R1 Out 3 12 R4 Out Q2 Out 4 11 Q4 Out Q2 Out 4 13 Q4 Out R2 Out 5 10 R3 Out R2 Out 5 12 R3 Out ENB 6 9 Q3 Out ENB 6 11 Q3 Out VSS 7 8 CLK VSS 7 10 CLK NC 8 9 NC NC = NO CONNECTION MC144110•MC144111 2 MOTOROLA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MAXIMUM RATINGS* (Voltages referenced to VSS) Parameter Symbol Value Unit VDD – 0.5 to + 18 V Vin – 0.5 to VDD + 0.5 V I ± 10 mA DC Supply Voltage Input Voltage, All Inputs DC Input Current, per Pin Power Dissipation (Per Output) TA = 70°C, MC144110 MC144111 TA = 85°C, MC144110 MC144111 POH mW 30 50 10 20 Power Dissipation (Per Package) TA = 70°C, MC144110 MC144111 TA = 85°C, MC144110 MC144111 PD Storage Temperature Range Tstg This device contains protection circuitry to guard against damage due to high static voltages or electric fields; however, it is advised that precautions be taken to avoid application of voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). mW 100 150 25 50 – 65 to + 150 °C * Maximum Ratings are those values beyond which damage to the device may occur. ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS, TA = 0 to 85°C unless otherwise indicated) Parameter Symbol Test Conditions VDD Min Max Unit VIH High–Level Input Voltage (Din, ENB, CLK) 5 10 15 3.0 3.5 4 — — — V VIL Low–Level Input Voltage (Din, ENB, CLK) 5 10 15 — — — 0.8 0.8 0.8 V IOH High–Level Output Current (Dout) Vout = VDD – 0.5 V 5 – 200 — µA IOL Low–Level Output Current (Dout) Vout = 0.5 V 5 200 — µA IDD Quiescent Supply Current 15 15 — — 12 8 mA MC144110 Iout = 0 µA MC144111 Input Leakage Current (Din, ENB, CLK) Vin = VDD or 0 V 15 — ±1 µA Vnonl Nonlinearity Voltage (Rn Out) See Figure 1 5 10 15 — — — 100 200 300 mV Vstep Step Size (Rn Out) See Figure 2 5 10 15 19 39 58 137 274 411 mV Voffset Offset Voltage from VSS Din = $00, See Figure 1 — — 1 LSB IE Emitter Leakage Current VRn Out = 0 V 15 — 10 µA hFE DC Current Gain IE = 0.1 to 10.0 mA TA = 25°C — 40 — — VBE Base–to–Emitter Voltage Drop IE = 1.0 mA — 0.4 0.7 V Iin MOTOROLA MC144110•MC144111 3 SWITCHING CHARACTERISTICS (Voltages referenced to VSS, TA = 0 to 85°C, CL = 50 pF, Input tr = tf = 20 ns unless otherwise indicated) Parameter Symbol VDD Min Max Unit twH Positive Pule Width, CLK (Figures 3 and 4) 5 10 15 2 1.5 1 — — — µs twL Negative Pulse Width, CLK (Figure 3 and 4) 5 10 15 5 3.5 2 — — — µs tsu Setup Time, ENB to CLK (Figures 3 and 4) 5 10 15 5 3.5 2 — — — µs tsu Setup Time, Din to CLK (Figures 3 and 4) 5 10 15 1000 750 500 — — — ns th Hold Time, CLK to ENB (Figures 3 and 4) 5 10 15 5 3.5 2 — — — µs th Hold Time, CLK to Din (Figures 3 and 4) 5 10 15 5 3.5 2 — — — µs Input Rise and Fall Times 5 – 15 — 2 µs Cin Input Capacitance 5 – 15 — 7.5 pF OUTPUT VOLTAGE @ Rn Out, % (VDD – VSS ) tr, tf 100 75 Vnonl ACTUAL 50 IDEAL 25 Voffset 0 0 $00 15 $0F 31 $1F 47 $2F 63 $3F PROGRAM STEP LINEARITY ERROR (integral linearity). A measure of how straight a device’s transfer function is, it indicates the worst–case deviation of linearity of the actual transfer function from the best– fit straight line. It is normally specified in parts of an LSB. Figure 1. D/A Transfer Function MC144110•MC144111 4 MOTOROLA VRn OUT STEP SIZE Step Size = VDD ± 0.75 VDD 64 64 (For any adjacent pair of digital numbers) DIGITAL NUMBER Figure 2. Definition of Step Size ENB 50% tsu CLK th 50% C1 C2 twH twL D1 Din CN D2 DN th tsu Figure 3. Serial Input, Positive Clock ENB tsu th CLK C1 twL Din C2 CN twH D1 D2 tsu DN th Figure 4. Serial Input, Negative Clock MOTOROLA MC144110•MC144111 5 OUTPUTS PIN DESCRIPTIONS INPUTS Dout Data Output Din Data Input The digital data output is primarily used for cascading the DACs and may be fed into Din of the next stage. Six–bit words are entered serially, MSB first, into digital data input, Din. Six words are loaded into the MC144110 during each D/A cycle; four words are loaded into the MC144111. The last 6–bit word shifted in determines the output level of pins Q1 Out and R1 Out. The next–to–last 6–bit word affects pins Q2 Out and R2 Out, etc. R1 Out through Rn Out Resistor Network Outputs These are the R–2R resistor network outputs. These outputs may be fed to high–impedance input FET op amps to bypass the on–chip bipolar transistors. The R value of the resistor network ranges from 7 to 15 kΩ . ENB Negative Logic Enable Q1 Out through Qn Out NPN Transistor Outputs The ENB pin must be low (active) during the serial load. On the low–to–high transition of ENB, data contained in the shift register is loaded into the latch. Buffered DAC outputs utilize an emitter–follower configuration for current–gain, thereby allowing interface to low–impedance circuits. SUPPLY PINS CLK Shift Register Clock Data is shifted into the register on the high–to–low transition of CLK. CLK is fed into the D–input of a transparent latch, which is used for inhibiting the clocking of the shift register when ENB is high. The number of clock cycles required for the MC144110 is usually 36. The MC144111 usually uses 24 cycles. See Table 1 for additional information. VSS Negative Supply Voltage This pin is usually ground. VDD Positive Supply Voltage The voltage applied to this pin is used to scale the analog output swing from 4.5 to 15 V p–p. Table 1. Number of Channels vs Clocks Required Number of Channels Required Number of Clock Cycles 1 6 Q1/R1 Q1/R1 2 12 Q1/R1, Q2/R2 Q1/R1, Q2/R2 3 18 Q1/R1, Q2/R2, Q3/R3 Q1/R1, Q2/R2, Q3/R3 4 24 Q1/R1, Q2/R2, Q3/R3, Q4/R4 Q1/R1, Q2/R2, Q3/R3, Q4/R4 5 30 Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5 Not Applicable 6 36 Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5, Q6/R6 Not Applicable MC144110•MC144111 6 Outputs Used on MC144110 Outputs Used on MC144111 MOTOROLA PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP CASE 707–02 18 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 10 B 1 9 A L C K N F H D J M SEATING PLANE G DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 15° 0° 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 15° 0° 0.020 0.040 DW SUFFIX SOG PACKAGE CASE 751D–04 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R C –T– 18X MOTOROLA G K SEATING PLANE X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M MC144110•MC144111 7 P SUFFIX PLASTIC DIP CASE 646–06 14 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 DW SUFFIX SOG PACKAGE CASE 751G–02 –A– 16 9 –B– 8X P 0.010 (0.25) 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. M B M 8 16X J D 0.010 (0.25) M T A S B S F R X 45 _ C –T– 14X G K SEATING PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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