MOTOROLA MC33984PNA

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33984
Rev 4.0, 09/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33984
Dual Intelligent High-Current
Self-Protected Silicon High-Side
Switch (4.0 mΩ)
DUAL HIGH-SIDE SWITCH
4.0 mΩ
Freescale Semiconductor, Inc...
The 33984 is a dual self-protected 4.0 mΩ silicon switch used to replace
electromechanical relays, fuses, and discrete devices in power management
applications. The 33984 is designed for harsh environments, and it includes
self-recovery features. The device is suitable for loads with high inrush current,
as well as motors and all types of resistive and inductive loads.
Programming, control, and diagnostics are implemented via the Serial
Peripheral Interface (SPI). A dedicated parallel input is available for alternate
and pulse-width modulation (PWM) control of each output. SPI-programmable
fault trip thresholds allow the device to be adjusted for optimal performance in
the application.
Bottom View
The 33984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN
package with exposed tabs.
PNA SUFFIX
SCALE
1:1
CASE 1402-02
Features
• Dual 4.0 mΩ Max High-Side Switch with Parallel Input or SPI Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring with Two SPI-Selectable Current Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Pin Status, and Program Status
• Enhanced -16 V Reverse Polarity VPWR Protection
16-TERMINAL PQFN (12 x 12)
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33984PNA/R2
-40°C to 125°C
16 PQFN
Simplified
ApplicationApplication
Diagram
33984
Simplified
Diagram
VDD
VDD
VPWR
VDD
33984
VDD
I/O
I/O
SO
SCLK
CS
MCU
SI
I/O
I/O
I/O
A/D
VPWR
FS
WAKE
SI
HS1
SCLK
CS
SO
HS0
RST
IN0
IN1
CSNS
FSI GND
GND
GND
LOAD
LOAD
PWR GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
VPWR
VDD
Internal
Regulator
IUP
VIC
Overvoltage
Protection
CS
Programmable
Switch Delay
0 ms –525 ms
SO
Freescale Semiconductor, Inc...
SPI
3.0 MHz
Selectable Slew
Rate Gate Drive
HS0
Selectable Overcurrent
High Detection
100 A or 75 A
SI
SCLK
FS
IN[0:1]
RST
WAKE
Logic
Selectable Overcurrent Low Detection
Blanking Time
0.15 ms–155 ms
Selectable Overcurrent
Low Detection
7.5 A –25 A
Open Load
Detection
IDWN
Overtemperature
Detection
RDWN
HS0
HS1
Programmable
Watchdog
310 ms–2500 ms
HS1
VIC
IUP
Selectable
Output Current
Recopy
1/20500 or 1/41000
FSI
CSNS
GND
Figure 1. 33984 Simplified Internal Block Diagram
33984
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Transparent Top View of Package
CSNS
WAKE
RST
IN0
FS
FSI
CS
SCLK
SI
VDD
Freescale Semiconductor, Inc...
SO
IN1
1
2
3
4
5
13
6
7 GND
8
9
10
11
12
16
HS0
15
HS1
14
VPWR
TERMINAL DEFINITIONS
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 15.
Terminal
Terminal
Name
Formal Name
Definition
1
CSNS
Output Current Monitoring
This terminal is used to output a current proportional to the designated HS0-1 output.
That current is fed into a ground-referenced resistor and its voltage is monitored by an
MCU's A/D. The channel to be monitored is selected via the SPI. This terminal can be
tri-stated through SPI.
2
WAKE
Wake
This terminal is used to input a logic [1] signal so as to enable the watchdog timer
function. An internal clamp protects this terminal from high damaging voltages when the
output is current limited with an external resistor. This input has a passive internal
pulldown.
3
RST
Reset (Active Low)
This input terminal is used to initialize the device configuration and fault registers, as
well as place the device in a low current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic LOW to logic HIGH. This terminal should
not be allowed to be logic HIGH until VDD is in regulation. This terminal has a passive
internal pulldown.
4
IN0
Serial Input
This input terminal is used to directly control the output HS0. This input has an active
internal pulldown current source and requires CMOS logic levels. This input may be
configured via SPI.
5
FS
Fault Status (Active Low)
This is an open drain configured output requiring an external pullup resistor to VDD for
fault reporting. When a device fault condition is detected, this terminal is active LOW.
Specific device diagnostic faults are reported via the SPI SO terminal.
6
FSI
Fail-Safe Input
The value of the resistance connected between this terminal and ground determines
the state of the outputs after a watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF, ON, or the output HSO only is ON. When the FSI
terminal is connected to GND, the watchdog circuit and fail-safe operation are disabled.
This terminal incorporates an active internal pullup current source.
7
CS
Chip Select (Active Low)
This input terminal is connected to a chip select output of a master microcontroller
(MCU). The MCU determines which device is addressed (selected) to receive data by
pulling the CS terminal of the selected device logic LOW, enabling SPI communication
with the device. Other unselected devices on the serial link having their CS terminals
pulled-up logic HIGH disregard the SPI communication data sent. This terminal
incorporates an active internal pullup current source.
8
SCLK
Serial Clock
This input terminal is connected to the MCU providing the required bit shift clock for SPI
communication. It transitions one time per bit transferred at an operating frequency,
fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level
serial clock signal is idle between command transfers. The signal is used to shift data
into and out of the device. This input has an active internal pulldown current source.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
TERMINAL DEFINITIONS (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 15.
Terminal
Terminal
Name
Formal Name
Definition
9
SI
Serial Input
This is a command data input terminal connected to the SPI Serial Data Output of the
MCU or to the SO terminal of the previous device of a daisy chain of devices. The input
requires CMOS logic-level signals and incorporates an active internal pulldown current
source. Device control is facilitated by the input's receiving the MSB first of a serial 8bit control command. The MCU ensures data is available upon the falling edge of
SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit
command into the internal command shift register.
10
VDD
Digital Drain Voltage
(Power)
This is an external voltage input terminal used to supply power to the SPI circuit. In the
event VDD is lost, an internal supply provides power to a portion of the logic, ensuring
limited functionality of the device.
11
SO
Serial Output
This output terminal is connected to the SPI Serial Data Input terminal of the MCU or
to the SI terminal of the next device of a daisy chain of devices. This output will remain
tri-stated (high impedance OFF condition) so long as the CS terminal of the device is
logic HIGH. SO is only active when the CS terminal of the device is asserted logic LOW.
The generated SO output signals are CMOS logic levels. SO output data is available
on the falling edge of SCLK and transitions immediately on the rising edge of SCLK.
12
IN1
Serial Input
This input terminal is used to directly control the output HS1. This input has an active
internal pulldown current source and requires CMOS logic levels. This input may be
configured via SPI.
13
GND
Ground
14
VPWR
Positive Power Supply
15
HS1
High-Side Output 1
Protected 4.0 mΩ high-side power output to the load.
16
HS0
High-Side Output 0
Protected 4.0 mΩ high-side power output to the load.
33984
4
This terminal is the ground for the logic and analog circuitry of the device.
This terminal connects to the positive power supply and is the source input of
operational power for the device. The VPWR terminal is a backside surface mount tab
of the package.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Operating Voltage Range
VPWR
V
-16 to 41
Steady-State
VDD Supply Voltage
Input/Output Voltage (Note 1)
VDD
0 to 5.5
V
VIN[0:1], RST, FSI
-0.3 to 7.0
V
CSNS, SI, SCLK,
Freescale Semiconductor, Inc...
CS, FS
SO Output Voltage (Note 1)
VSO
-0.3 to VDD +0.3
V
WAKE Input Clamp Current
ICL(WAKE)
2.5
mA
CSNS Input Clamp Current
ICL(CSNS)
10
mA
Output Current (Note 2)
IHS[0:1]
30
A
Output Clamp Energy (Note 3)
ECL[0:1]
0.75
J
Human Body Model (Note 4)
VESD1
±2000
Machine Model (Note 5)
VESD2
±200
Ambient
TA
-40 to 125
Junction
TJ
-40 to 150
TSTG
-55 to 150
Junction to Case
RθJC
<1.0
Junction to Ambient
RθJA
20
TSOLDER
230
V
ESD Voltage
THERMAL RATINGS
°C
Operating Temperature
Storage Temperature
°C
°C/W
Thermal Resistance (Note 6)
Peak Terminal Reflow Temperature During Solder Mounting (Note 7)
°C
Notes
1. Exceeding voltage limits on RST, IN[0:1], or FSI terminals may cause a malfunction or permanent damage to the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
4.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
5.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
6.
7.
Device mounted on a 2s2p test board according to JEDEC JESD51-2.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
5
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
VPWR
Full Operational
6.0
–
27
–
–
20
mA
IPWR(ON)
VPWR Operating Supply Current
Output ON, IHS0 and IHS1 = 0 A
VPWR Supply Current
Freescale Semiconductor, Inc...
V
IPWR(SBY)
Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD,
RST = VLOGIC HIGH
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
mA
–
–
5.0
µA
IPWR(SLEEP)
TJ = 25°C
–
–
10
TJ = 85°C
–
–
50
4.5
5.0
5.5
VDD Supply Voltage
VDD(ON)
VDD Supply Current
IDD(ON)
V
mA
No SPI Communication
–
–
1.0
3.0 MHz SPI Communication
–
–
5.0
VDD Sleep State Current
IDD(SLEEP)
–
–
5.0
µA
Overvoltage Shutdown Threshold
VPWR(OV)
28
32
36
V
Overvoltage Shutdown Hysteresis
VPWR(OVHYS)
0.2
0.8
1.5
V
VPWR(UV)
5.0
5.5
6.0
V
Undervoltage Hysteresis (Note 9)
VPWR(UVHYS)
–
0.25
–
V
Undervoltage Power-ON Reset
VPWR(UVPOR)
–
–
5.0
V
Undervoltage Output Shutdown Threshold (Note 8)
Notes
8. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external VDD supply is within specification.
9.
33984
6
This applies when the undervoltage fault is not latched (IN[0:1] = 0).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT
Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 25°C)
VPWR = 6.0 V
–
–
6.0
VPWR = 10 V
–
–
4.0
VPWR = 13 V
–
–
4.0
VPWR = 6.0 V
–
–
10.2
VPWR = 10 V
–
–
6.8
VPWR = 13 V
–
–
6.8
–
–
8.0
Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 150°C)
Freescale Semiconductor, Inc...
mΩ
RDS(ON)
Output Source-to-Drain ON Resistance IHS[0:1] = 15 A, TJ = 25°C (Note 10)
mΩ
RDS(ON)
RDS(ON)
VPWR = -12 V
mΩ
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
A
SOCH = 0
IOCH0
80
100
120
SOCH = 1
IOCH1
60
75
90
IOCL0
IOCL1
21
25
29
18
22.5
27
IOCL2
IOCL3
16
20
24
14
17.5
21
IOCL4
IOCL5
12
15
17
10
12.5
15
IOCL6
IOCL7
8.0
10
12
6.0
7.5
9.0
DICR D2 = 0
CSR0
–
1/20500
–
DICR D2 = 1
CSR1
–
1/41000
–
Overcurrent Low Detection Levels (SOCL[2:0])
000
001
010
011
100
101
110
111
A
–
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
%
CSR0_ACC
Current Sense Ratio (CSR0) Accuracy
Output Current
5.0 A
-20
–
20
10 A
-14
–
14
12.5 A
-13
–
13
15 A
-12
–
12
20 A
-13
–
13
25 A
-13
–
13
Notes
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
7
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (continued)
%
CSR1_ACC
Current Sense Ratio (CSR1) Accuracy
Freescale Semiconductor, Inc...
Output Current
5.0 A
-25
–
25
10 A
-19
–
19
12.5 A
-18
–
18
15 A
-17
–
17
20 A
-18
–
18
25 A
-18
–
18
4.5
6.0
7.0
30
–
100
Current Sense Clamp Voltage
VCL(CSNS)
CSNS Open; IHS[0:1] = 29 A
Open Load Detection Current (Note 11)
IOLDC
Output Fault Detection Threshold
V
V
VOLD(THRES)
2.0
3.0
4.0
-20
–
–
TSD
160
175
190
°C
TSD(HYS)
5.0
–
20
°C
Output Programmed OFF
Output Negative Clamp Voltage
V
VCL
0.5 A < IHS[0:1] < 2.0 A, Output OFF
Overtemperature Shutdown (Note 12)
Overtemperature Shutdown Hysteresis (Note 12)
µA
Notes
11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
12. Guaranteed by process monitoring. Not production tested.
33984
8
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Logic High Voltage (Note 13)
VIH
0.7VDD
–
–
V
Input Logic Low Voltage (Note 13)
VIL
–
–
0.2VDD
V
VIN[0:1](HYS)
100
350
750
mV
Input Logic Pulldown Current (SCLK, IN, SI)
IDWN
5.0
–
20
µA
RST Input Voltage Range
VRST
4.5
5.0
5.5
V
SO, FS Tri-State Capacitance (Note 15)
CSO
–
–
20
pF
RDWN
100
200
400
kΩ
CIN
–
4.0
12
pF
CONTROL INTERFACE
Freescale Semiconductor, Inc...
Input Logic Voltage Hysteresis (Note 14)
Input Logic Pulldown Resistor (RST) and WAKE
Input Capacitance (Note 15)
WAKE Input Clamp Voltage (Note 16)
VCL(WAKE)
V
7.0
ICL(WAKE) < 2.5 mA
WAKE Input Forward Voltage
–
14
VF(WAKE)
V
-2.0
–
-0.3
0.8 VDD
–
–
–
0.2
0.4
-5.0
0
5.0
5.0
–
20
RFSdis
–
0
1.0
FSI Enabled, HS[0:1] OFF
RFSoffoff
6.0
6.5
7.0
FSI Enabled, HS0 ON, HS1 OFF
RFSonoff
15
17
19
FSI Enabled, HS[0:1] ON
RFSonon
40
Infinite
–
ICL(WAKE) = -2.5 mA
SO High-State Output Voltage
VSOH
IOH = 1.0 mA
FS, SO Low-State Output Voltage
V
VSOL
IOL = -1.6 mA
SO Tri-State Leakage Current
V
µA
ISO(LEAK)
CS > 0.7 VDD
µA
IUP
Input Logic Pullup Current (Note 17)
CS, VIN[0:1] > 0.7 VDD
FSI Input Terminal External Pulldown Resistance
FSI Disabled, HS[0:1] Indeterminate
RFS
kΩ
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage reference to VPWR.
14. Parameter is guaranteed by processing monitoring but is not production tested.
15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
16. The current must be limited by a series resistance when using voltages > 7.0 V.
17. Pullup current is with CS OPEN. CS has an active internal pullup to VDD.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
9
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 18)
SRRA_SLOW
9.0 V < VPWR < 16 V
Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 19)
Freescale Semiconductor, Inc...
0.03
0.1
1.2
0.2
0.6
1.2
0.03
0.1
0.3
0.8
2.0
4.0
0.1
0.35
1.2
1.0
15
100
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
µs
t DLY_SLOW(OFF)
20
230
500
10
60
200
–
300
–
µs
t DLY_FAST(OFF)
DICR = 1
Direct Input Switching Frequency (DICR D3 = 0)
4.0
µs
DICR = 0
Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 21)
1.0
t DLY(ON)
DICR = 0, DICR = 1
Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 21)
0.4
V/µs
SRFB_FAST
9.0 V < VPWR < 16 V
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 20)
0.3
SRFA_FAST
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 19)
0.1
SRFB_SLOW
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 18)
0.03
SRFA_SLOW
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 19)
1.2
SRRB_FAST
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 18)
0.6
SRRA_FAST
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 19)
0.2
SRRB_SLOW
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 18)
V/µs
f PWM
Hz
Notes
18. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are
guaranteed by process monitoring.
19. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are
guaranteed by process monitoring.
20. Turn-ON delay time measured from rising edge of IN[0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 Ω resistive load.
21.
33984
10
Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR -0.5 V with RL = 5.0 Ω resistive load.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
t OCL0
t OCL1
t OCL2
t OCL3
108
155
202
Unit
POWER OUTPUT TIMING (continued)
Overcurrent Detection Blanking Time (OCLT[1:0])
00
01
10
11
Overcurrent High Detection Blanking Time
Freescale Semiconductor, Inc...
CS to CSNS Valid Time (Note 22)
ms
7.0
10
13
0.8
1.2
1.6
0.08
0.15
0.25
t OCH
1.0
10
20
µs
t CNSVAL
–
–
10
µs
t OSD0
t OSD1
t OSD2
t OSD3
t OSD4
t OSD5
t OSD6
t OSD7
–
0
–
HS0 Switching Delay Time (OSD[2:0])
ms
000
001
010
011
100
101
110
111
55
75
95
110
150
190
165
225
285
220
300
380
275
375
475
330
450
570
385
525
665
–
0
–
HS1 Switching Delay Time (OSD[2:0])
ms
t OSD0
t OSD1
t OSD2
t OSD3
t OSD4
t OSD5
t OSD6
t OSD7
000
001
010
011
100
101
110
111
–
0
–
110
150
190
110
150
190
220
300
380
220
300
380
330
450
570
330
450
570
Watchdog Timeout (WD[1:0]) (Note 23)
ms
00
t WDTO0
434
620
806
01
t WDTO1
207
310
403
10
t WDTO2
1750
2500
3250
11
t WDTO3
875
1250
1625
Notes
22. Time necessary for the CSNS to be within ±5% of the targeted value.
23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven
OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
11
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f SPI
–
–
3.0
MHz
t WRST
–
50
350
ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25)
t CS
–
–
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25)
t ENBL
–
–
5.0
µs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25)
t LEAD
–
50
167
ns
Required High State Duration of SCLK (Required Setup Time) (Note 25)
t WSCLKh
–
–
167
ns
Required Low State Duration of SCLK (Required Setup Time) (Note 25)
t WSCLKl
–
–
167
ns
t LAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time) (Note 26)
t SI(SU)
–
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time) (Note 26)
t SI(HOLD)
–
25
83
ns
–
25
50
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
Freescale Semiconductor, Inc...
Required Low State Duration for RST (Note 24)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25)
t RSO
SO Rise Time
CL = 200 pF
ns
t FSO
SO Fall Time
CL = 200 pF
ns
–
25
50
SI, CS, SCLK, Incoming Signal Rise Time (Note 26)
t RSI
–
–
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 26)
t RSI
–
–
50
ns
Time from Falling Edge of CS to SO Low Impedance (Note 27)
t SO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High Impedance (Note 28)
t SO(DIS)
–
65
145
ns
–
65
105
Time from Rising Edge of SCLK to SO Data Valid (Note 29)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
Notes
24.
25.
26.
27.
28.
29.
33984
12
t VALID
ns
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.
Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing Diagrams
CS
VPWR
VPWR
- 0.5V
VVPWR
PWR -0.5 V
VPWR
- 3VV
VPWR -3.5
SRFB
SRfB
SRRB
SRrB
SR
SRfA
FA
SRRA
SRrA
Freescale Semiconductor, Inc...
0.5V
0.5
V
t DLY(OFF)
Tdly(off)
t DLY(ON)
Tdly
(on)
Figure 2. Output Slew Rate and Time Delays
IOCHx
ILOAD1
Load
Current
ILOAD1
IOCLx
t OCH
Time
t OCLx
Figure 3. Overcurrent Shutdown
IOCH0
IOCH1
IOCL0
IOCL1
Load
Current
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
Time
t OCHx
t OCL3 t OCL2
t OCL1
t OCL0
Figure 4. Overcurrent Low and High Detection
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
13
Freescale Semiconductor, Inc.
VIH
V
IH
RSTB
RST
0.2
VDD
0.2
VDD
VIL
VIL
TwRSTB
t WRST
t ENBL
tTCSB
CS
TENBL
VIH
V
0.7
VDD
0.7VDD
CS
CSB
IH
0.7
VDD
0.7VDD
t WSCLKh
TwSCLKh
tTlead
LEAD
VIL
V
IL
t RSI
TrSI
t LAG Tlag
0.70.7VDD
VDD
SCLK
SCLK
VIH
VIH
0.2 VDD
0.2VDD
VIL
V
Freescale Semiconductor, Inc...
t TSIsu
SI(SU)
IL
t WSCLKl
TwSCLKl
tTfSI
FSI
t SI(HOLD)
TSI(hold)
SI
SI
VIH
V
0.7
0.7 V
VDD
DD
0.2VDD
0.2
VDD
Don’t Care
Don’t Care
Valid
Valid
Don’t Care
IH
VIH
VIL
Figure 5. Input Timing Switching Characteristics
t FSI
t RSI
TrSI
TfSI
VOH
VOH
3.5 V
3.5V
50%
SCLK
SCLK
1.0VV
1.0
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
0.7 V
VDD
DD
0.20.2
VDD
VDD
Low-to-High
Low
to High
VOH
VOH
VOL
VOL
TrSO
t RSO
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
0.7VDD
VDD
High to Low 0.7
High-to-Low
0.2VDD
0.2 VDD
TdlyHL
VOL
VOL
t SO(DIS)
Figure 6. SCLK Waveform and Valid SO Data Delay Time
33984
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33984 is a dual self-protected 4.0 mΩ silicon switch
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33984 is
designed for harsh environments, and it includes self-recovery
features. The device is suitable for loads with high inrush
current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented via
the Serial Peripheral Interface (SPI). A dedicated parallel input
is available for alternate and Pulse Width Modulation (PWM)
control of each output. SPI-programmable fault trip thresholds
allow the device to be adjusted for optimal performance in the
application.
The 33984 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
Freescale Semiconductor, Inc...
FUNCTIONAL DESCRIPTION
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Clock
(SCLK), Serial Input (SI), Serial Output (SO), and Chip Select
(CS).
The SI/SO terminals of the 33984 follow a first-in first-out
(D7/D0) protocol with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Clock (SCLK)
Serial clocks (SCLK) the internal shift registers of the 33984
device. The serial input (SI) terminal accepts data into the input
shift register on the falling edge of the SCLK signal while the
serial output (SO) terminal shifts data information out of the SO
line driver on the rising edge of the SCLK signal. It is important
that the SCLK terminal be in a logic low state whenever CS
makes any transition. For this reason, it is recommended that
the SCLK terminal be in a logic [0] state whenever the device is
not accessed (CS logic [1] state). SCLK has an active internal
pulldown, IDWN. When CS is logic [1], signals at the SCLK and
SI terminals are ignored and SO is tri-stated (high impedance).
(See Figure 7 and Figure 8 on page 16.)
Serial Input (SI)
This is a serial interface (SI) command data input terminal. SI
instruction is read on the falling edge of SCLK. An 8-bit stream
of serial data is required on the SI terminal, starting with D7 to
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
D0. The internal registers of the 33984 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table 1, page 16. Register addressing and configuration are
described in Table 2, page 17. The SI input has an active
internal pulldown, IDWN.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes states on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and Input Status descriptions are
provided in Table 11, page 21.
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33984 device latches
in data from the Input shift registers to the addressed registers
on the rising edge of CS. The device transfers status
information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS is
logic [0]. CS should transition from a logic [1] to a logic [0] state
only when SCLK is a logic [0]. CS has an active internal pullup,
IUP.
For More Information On This Product,
Go to: www.freescale.com
33984
15
Freescale Semiconductor, Inc.
CSB
CS
SCLK
SI
Freescale Semiconductor, Inc...
SO
SO
Notes
1.
NOTES:
2.
3.
D7
D6
OD7
D5
OD6
D4
OD5
D3
OD4
D2
OD3
D1
OD2
D0
OD1
OD0
1.
RSTisisin aa logic
state
during
the above
operation.
RST
RSTB
logic 1[1]
state
during
the above
operation.
2.
the
most
recent
entry entry
of data
intointo
thethe
device.
D0,D7:D0
D1, D2,relate
..., andtoD7
relate
to the
mostordered
recent ordered
of data
SPSS
OD0,
OD1, OD2,
..., and
relate8 to
theof
first
8 bits offault
ordered
and status
dataof
out
3.
OD7:OD0
relate
to OD7
the first
bits
ordered
andfault
status
data out
the device.
of the device.
Figure 7. Single 8-Bit Word SPI Communication
C
S B
CS
SCLK
S
C L K
SIS
I
S O
SO
D 7
O D 7
D 6
O D 6
D 5
D 2
O D 5
D 1
O D 2
D 0
O D 1
O D 0
D 7 *
D 6 *
D 7
D 5 *
D 6
D 2 *
D 5
D 2
D 1 *
D 0 *
D 1
D 0
1 .
B i s [1]
i n astate
l o g i c during
1 s t a t ethe
d u rabove
i n g t h eoperation.
a b o v e o p e r a t io n .
N O T E S1.
: RST
Notes
isRRD SaS0T,Tlogic
2 .
D 1 , D 2 , . .. , a n d D 7 r e la t e t o t h e m o s t r e c e n t o r d e r e d e n t r y o f d a t a in t o t h e S P S S
3 .
O relate
D 0 , O Dto
1 ,the
O D most
2 , . . . , recent
a n d O D
7 r e l a t e entry
t o t h eoff i rdata
s t 8 binto
i t s othe
f o r device.
d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e d e v ic e .
2. D7:D0
ordered
4 .
O D 0 , O D 1 , O D 2 , .. ., a n d O D 7 r e p r e s e n t t h e f ir s t 8 b its o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e S P S S
3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
4. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
F IG U R E
4 b .
M U L T IP L E
8 b it W O R D
S P I C O M M U N IC A T IO N
Figure 8. Multiple 8-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 8-bit messages.
A message is transmitted by the MCU starting with the MSB,
D7, and ending with the LSB, D0 (Table 1). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB (D7) is the watchdog bit
and in some cases a register address bit common to both
outputs or specific to an output; the next three bits, D6:D4, are
used to select the command register; and the remaining four
bits, D3:D0, are used to configure and control the outputs and
their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
Table 1. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D7
Register address bit for output selection. Also
used for Watchdog: toggled to satisfy
watchdog requirements.
LSB
D6:D4
Register address bits.
D3:D1
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
The 33984 has defined registers, which are used to
configure the device and to control the state of the output.
Table 2 page 17, summarizes the SI registers. The registers
are addressed via D6:D4 of the incoming SPI word (Table 1).
33984
16
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 2. Serial Input Address and Configuration Bit Map
Freescale Semiconductor, Inc...
SI
Register D7 D6 D5 D4
Serial Input Data
Address x010— Select Overcurrent High and Low Register
(SOCHLR)
DICR
s
1
0
0
FAST
SR s
OSDR
0
1
0
1
0
OSD2
OSD1
OSD0
The SOCHLR register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
Each output is independently selected for configuration based
on the state of the D7 bit; a write to this register when D7 is
logic [0] will configure the current detection levels for the HS0.
Similarly, if D7 is logic [1] when this register is written, HS1 is
configured. Each output can be configured to different levels. In
addition to protecting the device, this slow blow fuse emulation
feature can be used to optimize the load requirements matching
system characteristics. Bits D2:D0 set the overcurrent low
detection level to one of eight possible levels, as shown in
Table 3. Bit D3 sets the overcurrent high detection level to one
of two levels, which is described in Table 4.
WDR
1
1
0
1
0
0
WD1
WD0
Table 3. Overcurrent Low Detection Levels
NAR
0
1
1
0
0
0
0
0
UOVR
1
1
1
0
0
0
UV_dis
OV_dis
TEST
x
1
1
1
D3
D2
D1
D0
0
SOA2
SOA1
SOA0
STATR
SO
A3
0
0
0
OCR
x
0
0
1
SOCHLR
s
0
1
0
SOCL2s
SOCL1s
SOCL0s
CDTOLR
s
0
1
1 OL DIS s CD DIS s
CSNS1
EN
SOCHs
IN1_SPI
CSNS0
EN
IN0_SPI
OCLT1s
OCLT0s
CSNS
high s
IN DIS s
A/Os
Motorola Internal Use (Test)
x = Don’t care.
s = Selection of output: logic [0] = HS0, logic [1] = HS1.
Device Register Addressing
SOCL2
(D2)
SOCL1
(D1)
SOCL0
(D0)
Overcurrent Low Detection
(Amperes)
0
0
0
25
0
0
1
22.5
0
1
0
20
0
1
1
17.5
1
0
0
15
The following section describes the possible register
addresses and their impact on device operation.
1
0
1
12.5
1
1
0
10
Address x000—Status Register (STATR)
1
1
1
7.5
The STATR register is used to read the device status and the
various configuration register contents without disrupting the
device operation or the register contents. The register bits
D2:D0, determine the content of the first eight bits of SO data.
When register content is specific to one of the two outputs, bit
D7 is used to select the desired output. In addition to the device
status, this feature provides the ability to read the content of the
OCR, SOCHLR, CDTOLR, DICR, OSDR, WDR, NAR, and
UOVR registers. (Refer to the section entitled Serial Output
Communication (Device Status Return Data) beginning on
page 19.)
Address x001—Output Control Register (OCR)
The OCR register allows the MCU to control the outputs
through the SPI. Incoming message bit D0 reflects the desired
states of the high-side output HS0 (IN0_SPI): a logic [1]
enables the output switch and a logic [0] turns it OFF. A logic [1]
on message bit D1 enables the Current Sense (CSNS)
terminal. Similarly, incoming message bit D2 reflects the
desired states of the high-side output HS1 (IN1_SPI): logic [1]
enables the output switch and a logic [0] turns it OFF. A logic [1]
on message bit D3 enables the CSNS terminal. In the event that
the current sense is enabled for both outputs, the current will be
summed. Bit D7 is used to feed the watchdog if enabled.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Table 4. Overcurrent High Detection Levels
SOCH (D3)
Overcurrent High Detection
(Amperes)
0
100
1
75
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the
amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Each output is
independently selected for configuration based on the state of
the D7 bit. A write to this register when bit 7 is logic [0] will
configure the timeout for the HS0. Similarly, if D7 is logic [1]
when this register is written, then HS1 is configured. Bits D1:D0
allow the MCU to select one of four fault blanking times defined
in Table 5, page 18. Note that these timeouts apply only to the
overcurrent low detection levels. If the selected overcurrent
high level is reached, the device will latch off within 20 µs.
For More Information On This Product,
Go to: www.freescale.com
33984
17
Freescale Semiconductor, Inc.
Table 5. Overcurrent Low Detection
Blanking Time
OCLT[1:0]
Timing
00
155 ms
01
10 ms
10
1.2 ms
11
150 µs
A logic [1] on bit D2 disables the overcurrent low (CD dis)
detection timeout feature. A logic [1] on bit D3 disables the open
load (OL) detection feature.
Freescale Semiconductor, Inc...
Address x100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state of bit D7. A write to this register when bit D7 is logic [0] will
configure the direct input control for the HS0. Similarly, if D7 is
logic [1] when this register is written, then HS1 is configured.
A logic [0] on bit D1 will enable the output for direct control by
the IN terminal. A logic [1] on bit D1 will disable the output from
direct control. While addressing this register, if the input was
enabled for direct control, a logic [1] for the D0 bit will result in
a Boolean AND of the IN terminal with its corresponding D0
message bit when addressing the OCR register. Similarly, a
logic [0] on the D0 terminal results in a Boolean OR of the IN
terminal with the corresponding message bits when addressing
the OCR register.
The DICR register is useful if there is a need to
independently turn on and off several loads that are PWM’d at
the same frequency and duty cycle with only one PWM signal.
This type of operation can be accomplished by connecting the
pertinent direct IN terminals of several devices to a PWM output
port from the MCU and configuring each of the outputs to be
controlled via their respective direct IN terminal. The DICR is
then used to Boolean AND the direct IN(s) of each of the
outputs with the dedicated SPI bit that also controls the output.
Each configured SPI bit can now be used to enable and disable
the common PWM signal from controlling its assigned output.
A logic [1] on bit D2 is used to select the high ratio (CSR1,
1/41000) on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (CSR0, 1/20500).
A logic [1] on bit D3 is used to select the high speed slew rate
for the selected output. The default value [0] corresponds to the
low speed slew rate.
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register configures the device with a
programmable time delay that is active during Output ON
transitions initiated via SPI (not via direct input).
33984
18
A write to this register configures both outputs for different
delay. Whenever the input is commanded to transition from
logic [0] to logic [1], both outputs will be held OFF for the time
delay configured in the OSDR. The programming of the
contents of this register have no effect on device fail-safe mode
operation. The default value of the OSDR register is 000,
equating to no delay. This feature allows the user a way to
minimize inrush currents, or surges, thereby allowing loads to
be switched ON with a single command. There are eight
selectable output switching delay times that range from 0 ms to
525 ms (refer to Table 6).
Table 6. Switching Delay
OSD[2:0] (D2:D0)
Turn ON Delay (ms)
HS0
Turn ON Delay (ms)
HS1
000
0
0
001
75
0
010
150
150
011
225
150
100
300
300
101
375
300
110
450
450
111
525
450
Address 1101—Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1:D0. When D1:D0 bits are programmed for the desired
watchdog timeout period, the WD bit (D7) should be toggled as
well, ensuring the new timeout period is programmed at the
beginning of a new count sequence (refer to Table 7).
Table 7. Watchdog Timeout
WD[1:0] (D1:D0)
Timing (ms)
00
620
01
310
10
2500
11
1250
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows devices
to not be affected by commands being clocked over a daisychained SPI configuration, and by toggling the WD bit (D7), the
watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Address 1110—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register can be used to disable or enable
overvoltage and/or undervoltage protection. By default
(logic [0]), both protections are active. When disabled, an
undervoltage or overvoltage condition fault will not be reported
in the output fault register.
Address x111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Freescale Semiconductor, Inc...
Serial Output Communication (Device Status Return
Data)
When the CS terminal is pulled low, the output status register
is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI terminal. The
first eight bits of data clocking out of the SO, and following a CS
transition, are dependant upon the previously written SPI word.
Any bits clocked out of the SO terminal after the first eight will
be representative of the initial message bits clocked into the SI
terminal since the CS terminal first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
A valid message length is determined following a CS
transition of logic [0] to logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A valid
message length is a multiple of eight bits. At this time, the SO
terminal is tri-stated and the fault status register is now able to
accept new fault status information.
The output status register correctly reflects the status of the
STATR-selected register data at the time that the CS is pulled
to a logic [0] during SPI communication and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage VPWR condition should be
ignored.
• The RST terminal transition from a logic [0] to logic [1]
while the WAKE terminal is at logic [0] may result in
incorrect data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following this condition should be ignored.
Serial Output Bit Assignment
The 8 bits of serial output data depend on the previous serial
input message, as explained in the following paragraphs.
Table 8 summarizes the SO register content.
Table 8. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
UVF
OVF
FAULTs
s
0
0
0
s
OTFs
OCHFs
OCLFs
OLFs
x
0
0
1
x
0
0
1
CSNS1 EN
IN1_SPI
CSNS0 EN
IN0_SPI
s
0
1
0
s
0
1
0
SOCHs
SOCL2s
SOCL1s
SOCL0s
s
0
1
1
s
0
1
1
OL DIS s
CD DIS s
OCLT1s
OCLT0s
s
1
0
0
s
1
0
0
FAST SR s
CSNS high s
IN DIS s
A/Os
0
1
0
1
0
1
0
1
FSM_HS0
OSD2
OSD1
OSD0
1
1
0
1
1
1
0
1
FSM_HS1
WDTO
WD1
WD0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
–
–
UV_dis
OV_dis
x
1
1
1
–
–
–
–
–
–
–
–
IN1 Terminal IN0 Terminal FSI Terminal
WAKE
Terminal
s = Selection of output: logic [0] = HS0, logic [1] = HS1.
x = Don’t care.
Bit OD7 reflects the state of the watchdog bit (D7) addressed
during the prior communication. The value of the previous D7
will determine which output the status information applies to for
the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO
data will represent information ranging from fault status to
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
register contents, user selected by writing to the STATR bits
D2:D0. Note that the SO data will continue to reflect the
information for each output (depending on the previous D7
state) that was selected during the most recent STATR write
until changed with an updated STATR write.
For More Information On This Product,
Go to: www.freescale.com
33984
19
Freescale Semiconductor, Inc.
Previous Address SOA[2:0]=000
Previous Address SOA[2:0]=100
If the previous three MSBs are 000, bits OD6:OD0 will reflect
the current state of the Fault register (FLTR) corresponding to
the output previously selected with the bit OD7 (Table 9).
The returned data contain the programmed values in the
DICR.
Previous Address SOA[2:0]=101
Table 9. Fault Register
OD7
OD6
s
OTF
OD5
OD4
OCHFs OCLFs
OD3
OD2
OD1
OD0
OLFs
UVF
OVF
FAULTs
OD7 (s) = Selection of output: logic [0] = HS0, logic [1] = HS1.
OD6 (OTF) = Overtemperature Flag.
OD5 (OCHFs) = Overcurrent High Flag. (This fault is latched.)
OD4 (OCLFs) = Overcurrent Low Flag. (This fault is latched.)
Freescale Semiconductor, Inc...
OD3 (OLFs) = Open Load Flag.
OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.)
OD1 (OVF) = Overvoltage Flag.
OD0 (FAULTs) = This flag reports a fault and is reset by a read
operation.
Note The FS terminal reports a fault. For latched faults, this terminal
is reset by a new Switch ON command (via SPI or direct input IN).
• SOA3 = 0. The returned data contain the programmed
values in the OSDR. Bit OD3 (FSM_HS0) reflects the
state of the output HS0 in the Fail-Safe mode after a
watchdog timeout occurs.
• SOA3 = 1. The returned data contain the programmed
values in the WDR. Bit OD2 (WDTO) reflects the status of
the watchdog circuitry. If WDTO bit is logic [1], the
watchdog has timed out and the device is in Fail-Safe
mode. If WDTO is logic [0], the device is in Normal mode
(assuming the device is powered and not in Sleep mode),
with the watchdog either enabled or disabled. Bit OD3
(FSM_HS1) reflects the state of the output HS1 in the FailSafe mode after a watchdog timeout occurs.
Previous Address SOA[2:0] =110
• SOA3 = 0. OD3:OD0 return the state of the IN1, IN0, FSI,
and WAKE terminals, respectively (Table 10).
Previous Address SOA[2:0]=001
Table 10. Terminal Register
Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI
programmed bits, respectively. Data in bits OD3:OD2 contain
CSNS0 EN and IN0_SPI programmed bits, respectively.
Previous Address SOA[2:0]=010
The data in bit OD3 contain the programmed overcurrent
high detection level (refer to Table 4, page 17), and the data in
bits OD2:OD0 contain the programmed overcurrent low
detection levels (refer to Table 3, page 17).
Previous Address SOA[2:0]=011
Data returned in bits OD1 and OD0 are current values for the
overcurrent fault blanking time, illustrated in Table 5, page 18.
Bit OD2 reports if the overcurrent detection timeout feature is
active. OD3 reports if the open load circuitry is active.
33984
20
OD3
OD2
OD1
OD0
IN1 Terminal
IN0 Terminal
FSI Terminal
WAKE Terminal
• SOA3 = 1. The returned data contain the programmed
values in the UOVR. Bit OD1 reflects the state of the
undervoltage protection and bit OD0 reflects the state of
the overvoltage protection (refer to Table 8, page 19).
Previous Address SOA[2:0]=111
Null Data. No previous register Read Back command
received, so bits OD2:OD0 are null, or 000.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MODES OF OPERATION
The 33984 has four operating modes: Sleep, Normal, Fault,
and Fail-Safe. Table 11 summarizes details contained in
succeeding paragraphs.
Freescale Semiconductor, Inc...
Table 11. Fail-Safe Operation and
Transitions to Other 33984 Modes
Mode
FS
WAKE
RST
WDTO
Comments
Sleep
x
0
0
x
Device is in Sleep mode.
All outputs are OFF.
Normal
1
x
1
No
Normal mode. Watchdog
is active if enabled.
0
1
x
0
x
1
1
0
1
1
1
1
1
1
0
Fault
FailSafe
No
The device is currently in
Fault mode. The faulted
output(s) is (are) OFF.
Yes
Watchdog has timed out
and the device is in FailSafe mode. The outputs
are as configured with the
RFS resistor connected to
FSI. RST and WAKE must
be transitioned to logic [0]
simultaneously to bring
the device out of the FailSafe mode or momentarily
tied the FSI terminal to
ground.
x = Don’t care.
Sleep Mode
The default mode of the 33984 is the Sleep mode. This is the
state of the device after first applying battery voltage (VPWR),
prior to any I/O transitions. This is also the state of the device
when the WAKE and RST are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The device will transition to the Normal or Fail-Safe operating
modes based on the WAKE and RST inputs as defined in
Table 11.
Normal Mode
The 33984 is in Normal mode when:
• VPWR is within the normal voltage range.
• RST terminal is logic [1].
• No fault has occurred.
Fail-Safe Mode
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input terminal
transitions from logic [0] to logic [1]. The WAKE input is capable
of being pulled up to VPWR with a series of limiting resistance
that limits the internal clamp current according to the
specification.
The watchdog timeout is a multiple of an internal oscillator
and is specified in Table 7, page 18. As long as the WD bit (D7)
of an incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the programmed
value of the WDR the device will operate normally. If an internal
watchdog timeout occurs before the WD bit, the device will
revert to a Fail-Safe mode until the device is reinitialized.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI terminal,
regardless of the state of the various direct inputs and modes
(Table 12). In this mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, and
OCLT). Then the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
Table 12. Output State During Fail-Safe Mode
RFS (kΩ)
High-Side State
0
Fail-Safe Mode Disabled
6.0
Both HS0 and HS1 OFF
15
HS0 ON, HS1 OFF
30
Both HS0 and HS1 ON
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in fail-safe mode. The device can be brought out of the
Fail-Safe mode by transitioning the WAKE and RST terminals
from logic [1] to logic [0] or forcing the FSI terminal to logic [0].
Table 11 summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
Loss of VDD
If the external 5.0 V supply is not within specification, or even
disconnected, all register content is reset. The two outputs can
still be driven by the direct inputs IN1:IN0. The 33984 uses the
battery input to power the output MOSFET-related current
sense circuitry and any other internal logic providing fail-safe
device operation with no VDD supplied. In this state, the
watchdog, overvoltage, overtemperature, and overcurrent
circuitry are fully operational with default values.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
21
Freescale Semiconductor, Inc.
Fault Mode
Open Load Fault (Non-Latching)
The 33984 indicates the following faults as they occur by
driving the FS terminal to logic [0]:
The 33984 incorporates open load detection circuitry on
each output. Output open load fault (OLF) is detected and
reported as a fault condition when that output is disabled (OFF).
The open load fault is detected and latched into the status
register after the internal gate voltage is pulled low enough to
turn OFF the output. The OLF fault bit is set in the status
register. If the open load fault is removed, the status register will
be cleared after reading the register.
•
•
•
•
Overtemperature fault
Open load fault
Overcurrent fault (high and low)
Overvoltage and undervoltage fault
The FS terminal will automatically return to logic [1] when the
fault condition is removed, except for Overcurrent and in some
cases Undervoltage.
Freescale Semiconductor, Inc...
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 9, page 20).
Overtemperature Fault (Non-Latching)
The 33984 incorporates overtemperature detection and
shutdown circuitry in each output structure. Overtemperature
detection is enabled when an output is in the ON state.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely until
action is taken by the MCU to shut OFF the output, or until the
offending load is removed.
The open load protection can be disabled trough SPI (bit
OL_dis).
Overcurrent Fault (Latching)
The device has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent high
detection levels (IOCH) for maximum device protection. The two
selectable, simultaneously active overcurrent detection levels,
defined by IOCH and IOCL, are illustrated in Figure 4, page 13.
The eight different overcurrent low detect levels (IOCL0 :IOCL7)
are likewise illustrated in Figure 4.
If the load current level ever reaches the selected
overcurrent low detect level and the overcurrent condition
exceeds the programmed overcurrent time period (tOCx), the
device will latch the effected output OFF.
When experiencing this fault, the OTF fault bit will be set in
the status register and cleared after either a valid SPI read or a
power reset of the device.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF the
output, regardless of the selected tOCL driver.
Overvoltage Fault (Non-Latching)
For both cases, the device output will stay off indefinitely until
the device is commanded OFF and then ON again.
The 33984 shuts down the output during an overvoltage fault
(OVF) condition on the VPWR terminal. The output remains in
the OFF state until the overvoltage condition is removed. When
experiencing this fault, the OVF fault bit is set in the bit OD1 and
cleared after either a valid SPI read or a power reset of the
device.
The overvoltage protection and diagnostic can be disabled
trough SPI (bit OV_dis).
Undervoltage Shutdown (Latching or Non-Latching)
The output latches OFF at some battery voltage between
5.0 V and 6.0 V. As long as the VDD level stays within the
normal specified range, the internal logic states within the
device will be sustained. This ensures that when the battery
level then returns above 6.0 V, the device can be returned to
the state that it was in prior to the low VPWR excursion. Once the
output latches OFF, the outputs must be turned OFF and ON
again to re-enable them. In the case IN1:IN0 = 0, this fault is
non-latched.
Reverse Battery
The output survives the application of reverse voltage as low
as -16 V. Under these conditions, the output’s gates are
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are required.
Ground Disconnect Protection
In the event the 33984 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless the state of the output at the time of
disconnection.
The undervoltage protection and diagnostic can be disabled
through SPI (bit UV_dis).
33984
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Soldering Information
The 33984 is packaged in a surface mount power package
intended to be soldered directly on the printed circuit board.
The maximum peak temperature during the soldering
process should not exceed 230°C. The time at maximum
temperature should range from 10 s to 40 s maximum.
The 33984 was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
Freescale Semiconductor, Inc...
• Convection: 225°C +5.0/-0°C
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR)/Convection: 225°C +5.0/-0°C
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
23
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
PNA SUFFIX
16-TERMINAL PQFN
NONLEADED PACKAGE
CASE 1402-02
ISSUE B
12
A
12
1
M
2X
0.1 C
PIN 1
INDEX AREA
Freescale Semiconductor, Inc...
12
15
B
16
M
0.1 C
2X
PIN NUMBER
REF. ONLY
0.1 C
2.2 2.20
2.0 1.95
DETAIL G
0.6
0.2
0.1
M
C A B
0.05
M
C
10X
2X
0.95
0.55
0.1
0.05
6X
M
C A B
M
C
0.05
0.00
9X
0.1 C A B
5.0
4.6
0.9
2X 1.075
12
2.5
2.1
2.05
1.55
13
3.55
1.85
1.45
5.5
4X
1.05
5.1
0.1 C A B
14
(2)
6X
16
(2X 0.75)
(10X 0.4)
0.1 C A B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
5. MINIMUM METAL GAP SHOULD BE 0.25MM.
0.8
0.4
15
2X
2.25
1.75
SEATING PLANE
DETAIL G
6X
(10X 0.25)
C
4
VIEW ROTATED 90˚ CLOCKWISE
1
1.1
0.6
0.05 C
(0.5)
(10X 0.5)
10.7
10.3
0.1 C A B
1.28
0.88
0.15
0.05
6 PLACES
11.2
10.8
0.1 C A B
VIEW M-M
33984
24
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
25
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
33984
26
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33984
27
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2004
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center
3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan
81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre
2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE: http://motorola.com/semiconductors
For More Information On This Product,
Go to: www.freescale.com
MC33984