MOTOROLA MC33880

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33880/D
Rev 3.0, 01/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33880
Freescale Semiconductor, Inc...
Configurable Octal Serial Switch
with Serial Peripheral Interface I/O
The 33880 device is an eight-output hardware configurable high-side/lowside switch with 8-bit serial input control. Two of the outputs may be controlled
directly via microprocessor for PWM applications. The 33880 incorporates
SMARTMOS technology, with CMOS logic, bipolar/MOS analog circuitry,
and DMOS power MOSFETs. The 33880 controls various inductive or
incandescent loads by directly interfacing with a microcontroller. The circuit’s
innovative monitoring and protection features include very low standby
currents, cascade fault reporting, output-specific diagnostics, and
independent shutdown of output.
CONFIGURABLE OCTAL SERIAL
SWITCH WITH SERIAL
PERIPHERAL INTERFACE
Features
• Designed to Operate 5.5 V < VPWR < 24.5 V
• 8-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible
• Outputs Are Current Limited (0.8 A to 2.0 A) to Drive Incandescent
Lamps
• Output Voltage Clamp Is +45 V (Typical) (Low-Side Drive) and -20 V
(Typical) (High-Side Drive) During Inductive Switching
• Internal Reverse Battery Protection on VPWR
DW SUFFIX
CASE 751F-05
28-PIN SOIC
• Loss of Ground or Supply Will Not Energize Loads or Damage IC
• Maximum 5.0 µA IPWR Standby Current at 13 V VPWR up to 95°C
DWB SUFFIX
CASE 1324-02
32-PIN SOIC
ORDERING INFORMATION
• RDS(ON) of 0.55 Ω at 25°C Typical
Temperature
Range (TA)
Device
• Short Circuit Detect and Current Limit with Automatic Retry
• Independent Overtemperature Protection
• 32-Pin SOIC Has Pins 8, 9, 24, and 25 Grounded for Thermal
Performance
MC33880DW/R2
MC33880DWB/R2
-40°C to 125°C
Simplified Application
Diagram
33880 Simplified
Application
Diagram
VPWR
+5.0 V
VBAT
33880
A0
MCU
VPWR
VDD
EN
MOSI
SCLK
DI
SCLK
CS
MISO
CS
DO
PWM1
IN5
PWM2
IN6
GND
D1
D2
D3
D4
S1
S2
S3
S4
High-Side Drive
M
D5
D6
D7
D8
S5
S6
S7
S8
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
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H-Bridge Configuration
VBAT
VBAT
Low-Side Drive
Package
28 SOIC
32 SOIC
Freescale Semiconductor, Inc.
VDD
__
CS
VPWR
~50 µA
Internal
Bias
SCLK
Overvoltage
Shutdown/POR
Sleep State
Charge
Pump
DI
GND
DO
Freescale Semiconductor, Inc...
OV, POR, SLEEP
EN
~50 µA
SPI and
Interface
Logic
Typical of All 8 Output Drivers
TLIM
SPI Bit 0
IN5
~50 µA
IN6
Enable
Gate
Drive
Control
SPI Bit 4
Current
Limit
IN5
+
–
~50 µA
+
–
Open/Short Comparator
Open
Load
Detect
Current
~650 µA
+
S1
S2
S3
S4
S7
S8
_
~1.5 V Open/Short Threshold
TLIM
Open
Load
Detect
Current
~650 µA
Gate
Drive
Control
D1
D2
D3
D4
D7
D8
Drain
Outputs
Source
Outputs
D5
D6
Drain
Outputs
S5
Source
Outputs
Current
Limit
+
–
+
–
Open/Short Comparator
+ _
S6
~1.5 V Open/Short Threshold
Figure 1. 33880 Simplified Internal Block Diagram
33880
2
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GND
VDD
S8
S8
D8
S2
D2
S1
D1
D6
S6
IN6
17
DO
VPWR
S7
S7
D7
S4
D4
S3
D3
D5
S5
IN5
EN
13
16
CS
SCLK
14
15
DI
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
SOIC 28-PIN FUNCTION DESCRIPTON
Pin
Pin Name
Description
1
GND
Digital ground.
2
VDD
Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V).
3, 4
S8
Output 8 MOSFET source pins.
5
D8
Output 8 MOSFET drain pin.
6
S2
Output 2 MOSFET source pin.
7
D2
Output 2 MOSFET drain pin.
8
S1
Output 1 MOSFET source pin.
9
D1
Output 1 MOSFET drain pin.
10
D6
Output 6 MOSFET drain pin.
11
S6
Output 6 MOSFET source pin.
12
IN6
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
13
EN
Enable input. Allows control of outputs. Active high.
14
SCLK
15
DI
SPI control data input pin from MCU to the 33880. Logic [1] activates output.
16
CS
SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in.
17
IN5
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
18
S5
Output 5 MOSFET source pin.
19
D5
Output 5 MOSFET drain pin.
20
D3
Output 3 MOSFET drain pin.
21
S3
Output 3 MOSFET source pin.
22
D4
Output 4 MOSFET drain pin.
23
S4
Output 4 MOSFET source pin.
24
D7
Output 7 MOSFET drain pin.
25, 26
S7
Output 7 MOSFET source pins.
SPI control clock input pin.
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3
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SOIC 28-PIN FUNCTION DESCRIPTON (continued)
Pin Name
27
VPWR
28
DO
Description
Power supply pin to the 33880. VPWR has internal reverse battery protection.
SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.
Freescale Semiconductor, Inc...
Pin
33880
4
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GND
VDD
S8
S8
D8
S2
D2
GND
GND
S1
D1
D6
S6
IN6
EN
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DO
VPWR
S7
S7
D7
S4
D4
GND
GND
S3
D3
D5
S5
IN5
CS
DI
SOIC 32-PIN FUNCTION DESCRIPTON
Pin
Pin Name
Description
1, 8, 9,
24, 25
GND
Digital ground.
2
VDD
Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V).
3, 4
S8
Output 8 MOSFET source pins.
5
D8
Output 8 MOSFETdrain pin.
6
S2
Output 2 MOSFET source pin.
7
D2
Output 2 MOSFET drain pin.
10
S1
Output 1 MOSFET source pin.
11
D1
Output 1 MOSFET drain pin.
12
D6
Output 6 MOSFETdrain pin.
13
S6
Output 6 MOSFET source pin.
14
IN6
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
15
EN
Enable input. Allows control of outputs. Active high.
16
SCLK
17
DI
SPI control data input pin from MCU to the 33880. Logic [1] activates output.
18
CS
SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in.
19
IN5
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
20
S5
Output 5 MOSFET source pin.
21
D5
Output 5 MOSFET drain pin.
22
D3
Output 3 MOSFET drain pin.
23
S3
Output 3 MOSFET source pin.
26
D4
Output 4 MOSFET drain pin.
27
S4
Output 4 MOSFET source pin.
28
D7
Output 7 MOSFET drain pin.
29, 30
S7
Output 7 MOSFET source pins.
SPI control clock input pin.
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SOIC 32-PIN FUNCTION DESCRIPTON (continued)
Pin Name
31
VPWR
32
DO
Description
Power supply pin to the 33880. VPWR has internal reverse battery protection.
SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.
Freescale Semiconductor, Inc...
Pin
33880
6
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
VDD
-0.3 to 7.0
VDC
–
-0.3 to 7.0
VDC
VPWR
-16 to 50
VDC
VDD Supply Voltage (Note 1)
CS, DI, DO, SCLK, IN5, IN6, and EN (Note 1)
VPWR Supply Voltage (Note 1)
Drain 1–8 (Note 2)
–
Freescale Semiconductor, Inc...
5.0 mA ≤ IOUT ≤ 0.3 A
VDC
-18 to 40
Source 1–8 (Note 3)
–
5.0 mA ≤ IOUT ≤ 0.3 A
VDC
-28 to 40
Output Voltage Clamp Low-Side Drive (Note 4)
VOC
40 to 55
VDC
Output Voltage Clamp High-Side Drive (Note 4)
VOC
-15 to -25
VDC
ECLAMP
50
mJ
Human Body Model (Note 6)
VESD1
±2000
Machine Model (Note 7)
VESD2
±200
TSTG
-55 to 150
°C
Operating Case Temperature
TC
-40 to 125
°C
Operating Junction Temperature
TJ
-40 to 150
°C
Maximum Junction Temperature
–
-40 to 150
°C
Output Clamp Energy (Note 5)
ESD Voltage
V
Storage Temperature
Power Dissipation (TA = 25°C) (Note 8)
W
PD
28 SOIC, Case 751F-05
1.3
32 SOIC, Case 1324-02
1.7
Thermal Resistance, Junction-to-Ambient, 28 SOIC, Case 751F-05
RθJA
94
°C/W
Thermal Resistance, Junction-to-Ambient, 32 SOIC, Case 1324-02
RθJA
70
°C/W
Thermal Resistance, Junction-to-Thermal Ground Leads, 32 SOIC, Case 1324-02
RθJL
18
Notes
1.
2.
3.
4.
5.
6.
Exceeding these limits may cause malfunction or permanent damage to the device.
Configured as low-side driver with 300 mA load as current limit.
Configured as high-side driver with 300 mA load as current limit.
With outputs OFF and 10 mA of test current for low-side driver, 30 mA test current for high-side driver.
Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
7.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
8.
Maximum power dissipation with no heatsink used.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
5.5
–
24.5
–
8.0
14
Temperature = -40°C to 95°C
–
2.0
5.0
Temperature = 95°C to 125°C
–
5.0
20
VOV
25
27
30
V
VOV(HYS)
0.15
0.8
2.5
V
Logic Supply Voltage
VDD
4.75
–
5.25
V
Logic Supply Current
IDD
0.5
2.6
4.0
mA
VDD(UNVOL)
3.9
4.3
4.7
V
VDD(UNVOL-HYS)
100
150
300
mV
IOUT = 0.25 A, TJ = 125°C
–
0.75
1.1
IOUT = 0.25 A, TJ = 25°C
–
0.55
0.85
IOUT = 0.25 A, TJ = -40°C
–
0.45
0.80
POWER INPUT
Supply Voltage Range
VPWR(FO)
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Fully Operational
Supply Current
IPWR(ON)
Sleep State Supply Current (VDD and EN = 0 V, VPWR = 16 V)
IPWR(SS)
Overvoltage Shutdown
Overvoltage Shutdown Hysteresis
Logic Supply Undervoltage Lockout Threshold
Logic Supply Undervoltage Hysteresis
V
mA
µA
POWER OUTPUT
Drain-to-Source ON Resistance (VPWR = 16 V)
Output Self-Limiting Current High-Side and Low-Side Configurations
IOUT(LIM)
VPWR = 16 V
Output Fault Detect Threshold (Note 9), (Note 10)
A
0.8
1.4
2.0
1.0
–
3.0
0.30
0.55
1.0
40
45
55
-15
-20
-25
–
1.0
7.0
TLIM
155
–
185
°C
TLIM(HYST)
5.0
10
15
°C
VOUTth(F)
Outputs Programmed OFF
Output Off Open Load Detect Current (Note 9)
Ω
RDS(ON)
V
IOCO
Outputs Programmed OFF
Output Clamp Voltage Low-Side Drive
mA
VOC(LSD)
ID = 10 mA
Output Clamp Voltage High-Side Drive
V
VOC(HSD)
IS = -30 mA
Output Leakage Current High-Side and Low-Side Configuration
Overtemperature Shutdown Hysteresis (Note 10)
µA
IOUT(LKG)
VDD = 0 V, VDS = 16 V
Overtemperature Shutdown (Note 10)
V
Notes
9. Output Fault Detect Thresholds with outputs programmed OFF. Output fault detect threshold are the same for output open and shorts.
10. This parameter is guaranteed by design but is not production tested.
33880
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Logic Voltage Thresholds (Note 11)
VINLOGIC
0.8
–
2.2
V
-10
–
10
30
45
100
-10
–
10
-10
–
10
-30
–
-100
VDD - 0.8
–
VDD
–
–
0.4
–
–
20
DIGITAL INTERFACE
IN5, IN6, and EN Input Logic Current
µA
IIN5, IN6, EN
IN5, IN6, EN = 0 V
IN5, IN6, and EN Pull-Down Current
µA
IIN5, IN6, EN
Freescale Semiconductor, Inc...
0.8 V to VDD
SCLK, DI, and Tri-State DO Input
µA
ISCK, SI, TriSO
0 V to VDD
µA
IICS
CS Input Current
CS = VDD
µA
IICS
CS Pull-Up Current
CS = 0 V
DO High-State Output Voltage
VDOHIGH
IDO-HIGH = -200 µA
DO Low-State Output Voltage
V
VDOLOW
IDO-HIGH = 1.6 mA
Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (Note 12)
CIN
V
pF
Notes
11. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
12. This parameter is guaranteed by design but is not production tested.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
0.1
0.5
1.2
0.1
0.5
1.2
0.1
0.3
1.2
0.1
0.3
1.2
Units
POWER OUTPUT TIMING
Output Slew Rate Low-Side Configuration (Note 13)
Output Slew Rate Low-Side Configuration (Note 13)
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V/µs
tR
RL = 620 Ω
Output Slew Rate High-Side Configuration (Note 13)
V/µs
tF
RL = 620 Ω
Output Slew Rate High-Side Configuration (Note 13)
V/µs
tR
RL = 620 Ω
tF
RL = 620 Ω
V/µs
Output Turn ON Delay Time, High-Side and Low-Side Configuration (Note 14)
tDLY(ON)
1.0
15
50
µs
Output Turn OFF Delay Time, High-Side and Low-Side Configuration (Note 14)
tDLY(OFF)
1.0
30
100
µs
tFAULT
100
–
300
µs
Output Fault Delay Time (Note 15)
Notes:
13. Output Rise and Fall time respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
14. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to 90 and 10 percent of initial voltage.
15. Duration of fault before fault bit is set. Duration between access times must be greater than 300 µs to read faults.
33880
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Units
–
–
4.0
6.0
MHz
–
4.0
10
DIGITAL INTERFACE TIMING
Recommended Frequency of SPI Operation
Required Low State Duration on VDD for Reset (Note 16)
VDD ≤ 0.2 V
Freescale Semiconductor, Inc...
µs
tRESET
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
tLEAD
100
–
–
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
tLAG
50
–
–
ns
DI to Falling Edge of SCLK (Required Setup Time)
tDI(su)
16
–
–
ns
Falling Edge of SCLK to DI (Required Hold Time)
tDI(HOLD)
20
–
–
ns
DI, CS, SCLK Signal Rise Time (Note 17)
tR(DI)
–
5.0
–
ns
DI, CS, SCLK Signal Fall Time (Note 17)
tF(DI)
–
5.0
–
ns
Time from Falling Edge of CS to DO Low Impedance (Note 18)
tDO(EN)
–
–
60
ns
Time from Rising Edge of CS to DO High Impedance (Note 19)
tDO(DIS)
–
–
60
ns
tVALID
–
25
60
ns
Time from Rising Edge of SCLK to DO Data Valid (Note 20)
Notes
16.
17.
18.
19.
20.
This parameter is guaranteed by design but is not production tested.
Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at DO pin.
Time required for output status data to be terminated at DO pin
Time required to obtain valid data out from DO following the rise of SCLK.
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Timing Diagrams
CS
0.2 VDD
tLEAD
tLAG
0.7 VDD
SCLK
0.2 VDD
tDI(SU) tDI(HOLD)
0.7 VDD
0.2 VDD
Freescale Semiconductor, Inc...
DI
MSB in
tDO(EN)
tVALID
0.7 VDD
0.2 VDD
DO
tDO(DIS)
MSB out
LSB out
Figure 2. SPI Timing Diagram
VDD = 5.0 V
SCLK
33880
Under
Test
VDD = 5.0 V
DO
CL = 200 pF
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 3. Valid Data Delay Time and Valid Time Test Circuit
33880
12
33880
CS
Under
Test
VPull-Up = 2.5 V
RL = 1.0 kΩ
DO
CL = 200 pF
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 4. Enable and Disable Time Test Circuit
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tR(DI)
VDD = 5.0 V
VPWR = 13 V
RL = 620 Ω
33880
Under
Test
CS
tF(DI)
<50 ns
CS
90%
0.2 VDD (2.5 V)
10%
<50 ns
0
tDO(dis)
VTri-State
tDO(EN)
Output
DO
(Tri-State to Low)
CL
5.0 V
0.7 VDD
90%
10%
tDO(EN)
Freescale Semiconductor, Inc...
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 5. Switching Time Test Circuit
0.7 VDD (2.5 V)
SCLK
tF(DI)
< 50 ns
DO
(Low-to-High)
DO
(High-to-Low)
0.7 VDD
0.2 VDD
tVALID
0
VOH
tF(DI)
<50 ns
<50 ns
90%
CS
0.2 VDD (2.5 V)
10%
tDO(EN)
DO
(Tri-State to Low)
tDO(DIS)
VTri-State
10% t
SO(DIS)
tDO(EN)
Figure 6. Valid Data Delay Time and Valid Time Waveforms
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
tDO(DIS)
90%
DO
VOL
0
90%
VOH
0.2 VDD
5.0 V
0.7 VDD
VOL
tr(DO)
0.7 VDD
tDLY(HL)
tR(DI)
< 50 ns
0.2 VDD
tDLY(LH)
VTri-State
10%
Figure 7. Enable and Disable Time Waveforms
5.0 V
50%
VOH
90%
DO
(Tri-State to High)
tR(DI)
tSO(DIS)
tDO(DIS)
10%
VOH
VTri-State
(Tri-State to High)
Figure 8. Turn-ON/OFF Waveforms
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1.4
VPWR @ 16 V
12
10
1.0
All Outputs ON
8
All Outputs OFF
6
VPWR @ 16 V
1.2
RDS(ON) (Ω)
IPWR Current into VPWR Pin (mA)
14
4
2
0.8
0.6
0.4
0.2
-40 -25
0
25
50
75
100
125
-40 -25
TA, Ambient Temperature (°C)
50
75
100
125
1.4
VPWR @ 16 V
VPWR @ 16 V
1.2
1.0
0.8
0.6
0.4
0.2
-40 -25
-40 -25
0
0
25
50
75 100
25
50
75
100
TA, Ambient Temperature
TA, Ambient Temperature (°C)
125
125
0
1.6
TA = 25°C
IOUT(LIM), Current Limit (A)
50
40
30
20
10
0
5.0
10
15
20
VPWR
10
15
20
25
Figure 13. RDS(ON) vs. VPWR @ 250 mA
70
60
5.0
VPWR (V)
Figure 10. Sleep State IPWR vs. Temperature
25
1.5
VPWR @ 16 V
1.4
1.3
1.2
1.1
1.0
-40 -25
0
25
50
75
100
125
TA, Ambient Temperature (°C)
Figure 11. Sleep State IPWR vs. VPWR
33880
14
25
Figure 12. RDS(ON) vs. Temperature @ 250 mA
RDS(ON) (Ω)
IPWR
IPWR
Current
Current
into
into
VPWR
VPWR
Pin
Pin
(µA)
(uA)
14
14
12
12
10
10
8
8
6
6
4
4
2
2
0
TA, Ambient Temperature (°C)
Figure 9. IPWR vs. Temperature
Sleep State IPWR versus Temperature
IPWR Current into VPWR Pin (µA)
Freescale Semiconductor, Inc...
Typical Electrical Characteristics
Figure 14. Current Limit IOUT(LIM) vs. Temperature
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IOCO Open Load (mA)
1.2
1.4
VPWR @ 16 V
High-Side Configuration
1.0
0.8
0.6
0.4
0.2
-40 -25
0
25
50
75
100
TA = 25°C
1.2
1.0
0.8
0.6
0.4
0.2
0
125
5.0
10
TA, Ambient Temperature (°C)
15
20
25
VPWR (V)
Figure 15. Open Load Detect Current vs. Temperature
IOUT(LKG), Leakage Current (µA)
Freescale Semiconductor, Inc...
IOCO, Open Load (mA)
1.4
Figure 16. Open Load Detect Current vs. VPWR
1.4
TA = 25°C
1.2
1.0
0.8
0.6
0.4
0.2
0
5.0
10
15
20
25
VPWR (V)
Figure 17. Sleep State Output Leakage vs. VPWR
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33880
15
Freescale Semiconductor, Inc.
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33880 is an eight-output hardware configurable power
switch with 8-bit serial control. The 33880 incorporates
SMARTMOS 5 technology with CMOS logic, bipolar/MOS
analog circuitry, and independent double diffused DMOS power
output transistors. Many benefits are realized as a direct result
of using this mixed technology. A simplified internal block
diagram of the 33880 is shown in Figure 1, page 2.
The 33880 device uses high-efficiency updrain power DMOS
output transistors exhibiting low drain-to-source ON resistance
values (RDS(ON) ≤ 0.55 Ω at 25°C) and dense CMOS control
logic. All outputs have independent voltage clamps to provide
fast inductive turn-off and transient protection. Operational bias
currents of less than 4.0 mA on VDD and 12 mA on VPWR with
any combination of outputs ON are a direct result of using
SMARTMOS 5 technology.
Freescale Semiconductor, Inc...
MCU INTERFACE DESCRIPTION
In operation the 33880 functions as an eight-output serial
switch serving as a microcontroller (MCU) bus expander and
buffer with fault management and fault reporting features. In
doing so, the device directly relieves the MCU of the fault
management functions. This device directly interfaces to an
MCU using a Serial Peripheral Interface (SPI) for control and
diagnostic readout. Figure 18 (below) and Figure 21, page 17,
illustrate the basic SPI configuration between an MCU and one
33880.
MC68HCxx
Microcontroller
Parallel Port
CS
MC68xx
MISO
MCU
DO
DI
with
SPI Interface
33880
33880
MOSI
DI
MISO
DO
Shift Register
8 Outputs
DO
DI
CS SCLK
DO
DI
33880
33880
8 Outputs
8 Outputs
Shift Register
Receive
Buffer
Figure 19. 33880 SPI System Daisy Chain
To
Logic
CS
Multiple 33880 devices can be controlled in a parallel input
fashion using the SPI. Figure 20 illustrates 24 loads being
controlled by three dedicated parallel MCU ports used for chip
select.
MOSI
SCLK
MISO
Figure 18. SPI Interface with Microcontroller
All inputs are compatible with 5.0 V and 3.3 V CMOS logic
levels and incorporate positive logic. Whenever an input is
programmed to a logic low state (<0.8 V) the corresponding
output will be OFF. Conversely, whenever an input is
programmed to a logic high state (>2.2 V), the output being
controlled will be ON. Diagnostics are treated in a similar
manner. Outputs with a fault will feedback (via DO) to the
microcontroller as a logic [1] while normal operating outputs will
provide a logic [0].
Figure 19 illustrates the Daisy Chain configuration using the
33880. Data from the MCU is clocked daisy chain through each
device while the Chip Select (CS) bit is commanded low by the
MCU. During each clock cycle output status from the daisy
chain, the 33880 is being transferred to the MCU via the Master
In Slave Out (MISO) line. On rising edge of CS data stored in
the input register is then transferred to the output driver.
33880
16
CS SCLK
MOSI
SCLK
Parallel
Ports
SCLK
DI
SCLK
DO
8 Outputs
CS
MC68xx
Microcontroller
SPI
DI
SCLK
DO
8 Outputs
CS
Parallel
Ports
A
B
C
DI
SCLK
DO
8 Outputs
CS
Figure 20. Parallel Input SPI Control
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Figure 21. Data Transfer Timing
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17
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FUNCTIONAL PIN DESCRIPTION
Freescale Semiconductor, Inc...
CS Pin
The system MCU selects the 33880 to communicate through
the use of the CS pin. Whenever the pin is in a logic low state,
data can be transferred from the MCU to the 33880 device and
vice versa. Clocked-in data from the MCU is transferred from
the 33880 shift register and latched into the power outputs on
the rising edge of the CS signal. On the falling edge of the CS
signal, output status information is transferred from the power
outputs status register into the device's shift register. The falling
edge of CS enables the DO output driver. Whenever the CS pin
goes to a logic low state, the DO pin output is enabled, thereby
allowing information to be transferred from the 33880 to the
MCU. To avoid any spurious data, it is essential the high-to-low
transition of the CS signal occurs only when SCLK is in a logic
low state.
SCLK Pin
The system clock pin (SCLK) clocks the internal shift
registers of the 33880. The serial data input (DI) is latched into
the input shift register on the falling edge of the SCLK. The
serial data output pin (DO) shifts data out of the shift register on
the rising edge of the SCLK signal. False clocking of the shift
register must be avoided to guarantee validity of data. It is
essential the SCLK pin be in a logic low state whenever chip
select pin (CS) makes any transition. For this reason, it is
recommended the SCLK pin is commanded to a logic low state
when the device is not accessed (CS in logic high state). When
the CS is in a logic high state, any signal at the SCLK and DI pin
is ignored and the DO is tri-stated (high impedance).
DI Pin
This pin is used for serial instruction data input. DI
information is latched into the input register on the falling edge
of SCLK. A logic high state present on DI will program a specific
output on. The specific output will turn on with the rising edge of
the CS signal. Conversely, a logic low state present on the DI
pin will program the output off. The specific output will turn off
with the rising edge of the CS signal. To program the eight
outputs of the 33880 device on or off, enter the DI pin beginning
with Output 8, followed by Output 7, Output 6, and so on to
Output 1. For each falling edge of the SCLK while CS is logic
low, a data bit instruction (on or off) is loaded into the shift
register per the data bit DI state. Eight bits of entered
information fills the shift register. To preserve data integrity, do
not transition DI as SCLK transitions from a high to low logic
state.
DO Pin
The serial data output (DO) pin is the output from the shift
register. The DO pin remains tri-state until the CS pin goes to a
logic low state. All faults on the 33880 device are reported as
logic [1] through the DO data pin. Regardless of the
configuration of the driver, open loads and shorted loads are
33880
18
reported as logic [1]. Conversely, normal operating outputs with
non-faulted loads are reported as logic [0]. The first positive
transition of SCLK will make output eight status available on DO
pin. Each successive positive clock will make the next output
status available. The DI/DO shifting of data follows a first-infirst-out protocol with both input and output words transferring
the most significant bit (MSB) first.
EN Pin
The EN pin on the 33880 device either enables or disables
the internal charge pump. The EN pin must be high for this
device to enhance the gates of the output drivers, perform fault
detection, and reporting. Active outputs during a low transition
of the EN pin will become active again when the EN transitions
high. If this feature is not required, it is recommended the EN
pin be connected to VDD.
IN5 and IN6 Pins
The IN5 and IN6 pins command inputs allowing outputs five
and six to be used in PWM applications. IN5 and IN6 pins are
ORed with the SPI communication input. For SPI control of
outputs five and six, the IN5 and IN6 pins should be grounded
or held low by the microprocessor. In the same manner, when
using the PWM feature the SPI port must command the outputs
off. Maximum PWM frequency for each output is 2.0 kHz.
VDD Pin
The VDD pin supplies logic power to the 33880 device and is
used for power-on reset (POR). To achieve low standby current
on VPWR supply, power must be removed from the VDD pin. The
device will be in reset with all drivers off when VDD is below
3.9 VDC.
D1–D8 Pins
The D1–D8 pins are the open drain outputs of the 33880. For
High-Side Drive configurations, the drain pins are connected to
battery supply. In Low-Side Drive configurations, the drain pins
are connected to the low side of the load. All outputs may be
configured individually as desired. When Low-Side Drive is
used, the 33880 limits the positive transient for inductive loads
to 45 V.
S1–S8 Pins
The S1–S8 pins are the source outputs of the 33880. For
High-Side Drive configurations, the source pins are connected
directly to the load. In Low-Side Drive configurations the source
is connected to ground. All outputs may be configured
individually as desired. When High-Side drive is used, the
33880 will limit the negative transient for inductive loads to
-20 V.
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FAULT OPERATION
On each SPI communication, an 8-bit command word is sent
to the 33880 and an 8-bit fault word is received from the 33880.
The Most Significant Bit (MSB) is sent and received first (see
below).
Command Register Definition:
0 = Output Command Off
1 = Output Command On
Fault Register Definition:
MSB
OUT8
LSB
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
0 = No fault
1 = Fault.
Table 1. Fault Operation
Freescale Semiconductor, Inc...
Serial Output (SO) Pins Reports
Overtemperature
Fault reported by Serial Output (DO) pin.
Overcurrent
DO pin reports short to battery/supply or overcurrent condition.
Output ON Open Load Fault
Not reported.
Output OFF Open Load Fault
DO pin reports output OFF open load condition.
Device Shutdowns
Overvoltage
Total device shutdown at VPWR = 25 V to 30 V. Resumes normal operation with proper voltage. All outputs
assuming the previous state upon recovery from overvoltage.
Overtemperature
Only the output experiencing an overtemperature fault shuts down. Output assumes previous state upon
recovery from overtemperature.
APPLICATIONS
Power Consumption
The 33880 device has been designed with one sleep and
one operational mode. In the sleep mode (VDD ≤ 2.0 V), the
current consumed by VPWR pin is less than 25 µA. To place the
33880 in the sleep mode, turn all outputs off, then remove
power from VDD and the EN (enable) input pin. Prior to
removing power from the device, it is recommended all control
inputs from the microcontroller are low. During normal
operation, 4.0 mA will be drawn from the VDD supply and 12 mA
from the VPWR supply.
Paralleling of Outputs
Using MOSFETs as output switches allows the connection of
any combination of outputs together. RDS(ON) of MOSFETs
have an inherent positive temperature coefficient, providing
balanced current sharing between outputs without destructive
operation. The device can even be operated with all outputs tied
together. This mode of operation may be desirable in the event
the application requires lower power dissipation or the added
capability of switching higher currents. Performance of parallel
operation results in a corresponding decrease in RDS(ON) while
the outputs OFF open load detect currents and the output
current limits increase correspondingly (by a factor of eight if all
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
outputs are paralleled). Paralleling outputs from two or more
different IC devices are possible but not recommended.
Fault Logic Operation
Fault logic of the 33880 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs faulted,
all status bits being received by the MCU will be zero. When
outputs are faulted (off state open circuit or on state short
circuit/overtemperature), the status bits being received by the
MCU will be one. The distinction between open circuit fault and
short circuit/overtemperature is completed via the command
word. For example, when a zero command bit is sent and a one
fault is received in the following word, the fault is open/short-tobattery for high-side drive or open/short to ground for low-side
drive. In the same manner, when a one command bit is sent and
a one fault is received in the following word the fault is a shortto-ground/overtemperature for high-side drive or short-tobattery/overtemperature for low-side drive. The timing between
two write words must be greater than 300 µs to allow adequate
time to sense and report the proper fault status.
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33880
19
Freescale Semiconductor, Inc.
SPI Integrity Check
It is recommended that one check the integrity of the SPI
communication with the initial power-up of the VDD and EN pins.
After initial system start-up or reset, the MCU will write one
16-bit pattern to the 33880. The first eight bits read by the MCU
will be the fault status of the outputs, while the second eight bits
will be the first byte of the bit pattern. Bus integrity is confirmed
by the MCU receiving the same bit pattern it sent. Please note
that the second byte the MCU sends to the device is the
command byte and will be transferred to the outputs with rising
edge of CS.
Freescale Semiconductor, Inc...
Overtemperature Fault
Overtemperature detect and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an overtemperature condition is
independent of the system clock or any other logic signal. Each
independent output shuts down at 155°C to 185°C. When an
output shuts down due to an overtemperature fault, no other
outputs are affected. The MCU recognizes the fault by a one in
the fault status register. After the 33880 device has cooled
below the switch point temperature and 15°C hysteresis, the
output will activate unless told otherwise by the MCU via SPI to
shut down.
Overvoltage Fault
An overvoltage condition on the VPWR pin will cause the
device to shut down all outputs until the overvoltage condition
is removed. When the overvoltage condition is removed, the
outputs will resume their previous state. This device does not
detect an overvoltage on the VDD pin. The overvoltage
threshold on the VPWR pin is specified as 25 V to 30 V with
1.0 V typical hysteresis. A VPWR overvoltage detect is global,
causing all outputs to be turned OFF.
This device has an internal 650 µA current source connected
from drain to source of the output MOSFET. This prevents
either configuration of the driver from having a floating output.
To achieve low sleep mode quiescent currents, the open load
detect current source of each driver is switched off when VDD is
removed.
During output switching, especially with capacitive loads, a
false output OFF open load fault may be triggered. To prevent
this false fault from being reported, an internal fault filter of
100 µs to 300 µs is incorporated. A false fault reporting is a
function of the load impedance, RDS(ON) , COUT of the MOSFET,
as well as the supply voltage, VPWR. The rising edge of CS
triggers the built-in fault delay timer. The timer will time out
before the fault comparator is enabled and the fault is detected.
Once the condition causing the open load fault is removed, the
device will resume normal operation. The open load fault
however, will be latched in the output DO register for the MCU
to read.
Shorted Load Fault
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply or an output causing the
device to current limit (linear short).
There are two safety circuits progressively in operation
during load short conditions providing system protection:
1. The device’s output current is monitored in an analog
fashion using SENSEFET approach and current
limited.
2. The device’s output thermal limit is sensed and when
attained causes only the specific faulted output to shut
down. The output will remain off until cooled. The device
will then reassert the output automatically. The cycle will
continue until the fault is remove or the command bit
instructs the output off.
Output OFF Open Load Fault
Undervoltage Shutdown
An output OFF open load fault is the detection and reporting
of an open load when the corresponding output is disabled
(input bit programmed to a logic low state). The output OFF
open load fault is detected by comparing the drain-to-source
voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.
An undervoltage VDD condition will result in the global
shutdown of all outputs. The undervoltage threshold is between
3.9 V and 4.6 V. When VDD goes below the threshold, all
outputs are turned OFF and the Fault Status (FS) register is
cleared. As VDD returns to normal levels, the FS register will
resume normal operation.
An output off open load fault is indicated when the drain-tosource voltage is less than the output threshold voltage
(VTHRES) of 1.0 V to 3.0 V. Hence, the 33880 will declare the
load open in the OFF state when the VDS is less than 1.0 V.
33880
20
An undervoltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5 V and
9.0 V, the output will operate per the command word. However,
the status as reported by the serial data output (DO) pin may
not be accurate below 9.0 V VPWR. Proper operation at VPWR
voltages below 5.5 V cannot be guaranteed.
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Output Voltage Clamp
SPI Configurations
Each output of the 33880 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of each
output. Each clamp independently limits the drain-to-source
voltage to 45 V for low-side drive configurations and -20 V for
high-side drive configurations (see Figure 22). The total energy
clamped (EJ ) can be calculated by multiplying the current area
under the current curve (IA) times the clamp voltage (VCL).
The SPI configuration on the 33880 device is consistent with
other devices in the OSS family. This device may be used in
serial SPI or parallel SPI with the 33291 and 33298. Different
SPI configurations may be provided. For more information,
contact Analog Products Division.
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.3 A, indicates the maximum energy
to be 50 mJ at 150°C junction temperature per output.
The 33880 has been designed with reverse battery
protection on the VPWR pin. However, the device does not
protect the load from reverse battery. During the reverse battery
condition, current will flow through the load via the output
MOSFET substrate diode. Under this circumstance relays may
energize and lamps will turn on. If load reverse battery
protection is desired, a diode must be placed in series with the
load.
Drain-to-Source Clamp
Voltage (VCL = 45 V)
Drain Voltage
Drain Current
(ID = 0.3 A)
Drain-to-Source ON
Voltage (VDS(ON))
Reverse Battery
Clamp Energy
(EJ = IA x VCL)
Current
Area (IA)
Time
GND
VBAT
Drain-to-Source ON
Voltage (VDS(ON))
GND
Time
Current
Area (IA)
Clamp Energy
(EJ = IA x VCL)
Source Current
(IS = 0.3 A)
Source Clamp Voltage
(VCL = -20 V)
Source Voltage
Figure 22. Output Voltage Clamping
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21
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PACKAGE DIMENSIONS
DW SUFFIX
28-PIN SOIC
PLASTIC PACKAGE
CASE 751-05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
15
M
0.25
E
H
B
M
28
Freescale Semiconductor, Inc...
1
14
PIN 1 IDENT
A1
A
B
e
B
0.025
33880
22
C
M
C A
S
B
S
L
0.10
SEATING
PLANE
C
θ
DIM
A
A1
B
C
D
E
e
H
L
θ
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0°
8°
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DWB SUFFIX
32-PIN SOIC
PLASTIC PACKAGE
CASE 1324-02
ISSUE A
10.3
7.6
7.4
C
5
Freescale Semiconductor, Inc...
1
B
2.65
2.35
9
30X
32
0.65
PIN 1 ID
4
B
9
B
16
11.1
10.9
CL
17
A
5.15
32X
2X 16 TIPS
0.3
SEATING
PLANE
0.10 A
A B C
A
(0.29)
A
0.25
0.19
BASE METAL
(0.203)
6
0.13
0.38
0.22
M
C A
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
R0.08 MIN
0.25
PLATING
M
B
SECTION A-A
ROTATED 90 ° CLOCKWISE
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4
MM PER SIDE. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD
SHALL NOT LESS THAN 0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM
THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
GAUGE PLANE
8
8°
0°
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0°
MIN
0.29
0.13
0.9
0.5
SECTION B-B
33880
23
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217.
1-303-675-2140 or 1-800-441-2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan.
81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T.,
Hong Kong. 852-26668334
TECHNICAL INFORMATION CENTER: 1-800-521-6274
For More Information On This Product,
Go to: www.freescale.com
MC33880/D