MC54/74F168 MC54/74F169 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS The MC54/74F168 and MC54/74F169 are fully synchronous 4-stage up/ down counters. The F168 is a BCD decade counter; the F169 is a modulo-16 binary counter. Both feature a preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. • Asynchronous Counting and Loading • Built-In Lookahead Carry Capability • Presettable for Programmable Operation 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTERS FAST SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM (TOP VIEW) VCC TC Q0 Q1 Q2 Q3 CET PE 16 15 14 13 12 11 10 9 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 2 3 4 5 6 7 8 U/D CP P0 P1 P2 P3 CEP GND 1 MODE SELECT TABLE PE CEP CET D SUFFIX SOIC CASE 751B-03 16 1 Action on Rising Clock Edge U/D Load (Pn º L X X X H L L H Qn) Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC H = HIGH Voltage Level; L = LOW Voltage Level; X = Don’t Care LOGIC SYMBOL STATE DIAGRAMS MC54/74F169 0 1 2 3 4 9 3 4 5 6 MC54/74F168 0 1 10 2 3 15 15 9 4 11 14 7 6 5 14 6 13 7 13 1 7 10 2 PE P0 P1 P2 P3 U/D CEP TC CET CP Q0 Q1 Q2 Q3 14 13 12 11 8 COUNT DOWN COUNT UP 5 12 12 11 10 9 8 COUNT DOWN COUNT UP FAST AND LS TTL DATA 4-82 VCC = Pin 16 GND = Pin 8 15 MC54/74F168 • MC54/74F169 LOGIC DIAGRAMS MC54/74F168 P0 PE P1 P2 P3 CEP CET T LD TC AT AF ENF U/D BT BF UP DN DETAIL A ENF UP DN CP CP LD T DETAIL A J CP K Q Q DETAIL A DETAIL A Q2 Q3 CP Q Q Q0 Q1 MC54/74F169 P0 PE P1 P2 P3 CEP CET T LD TC AT AF ENF U/D BT BF UP UP DN DETAIL A ENF DN CP LD T CP DETAIL A J CP K Q Q DETAIL A DETAIL A Q2 Q3 CP Q Q Q0 Q1 NOTE: These diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. FAST AND LS TTL DATA 4-83 MC54/74F168 • MC54/74F169 FUNCTIONAL DESCRIPTION The F168 and F169 use edge-triggered J-K type flip-flops and have no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0-P3 inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 9 (15 for the F169) in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. The TC output of the F168 decade counter can also be LOW in the illegal states 11, 13, and 15, which can occur when power is turned on or via parallel loading. If an illegal state occurs, the F168 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1) Count Enable = CEP • CET • PE 2) Up: (′F168): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET (′F169): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET 3) Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 54, 74 4.5 5.0 5.5 V 54 –55 25 125 °C 74 0 25 70 VCC Supply Voltage TA Operating Ambient Temperature Range IOH Output Current — High 54, 74 –1.0 mA IOL Output Current — Low 54, 74 20 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage Min Typ Max Unit 2.0 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs 0.8 V Guaranteed Input LOW Voltage for All Inputs –1.2 V VCC = MIN, IIN = – 18 mA 54, 74 2.5 3.4 V IOH = – 1.0 mA VCC = 4.50 V 74 2.7 3.4 V IOH = – 1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V CET –1.2 mA VCC = MAX, VIN = 0.5 V Other Inputs –0.6 –150 mA VCC= MAX, VOUT = 0 V 52 mA VCC = MAX VOL Output LOW Voltage IIH Input HIGH Current 0.35 Input LOW Current IIL IOS Output Short Circuit Current (Note 2) ICC Power Supply Current –60 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-84 MC54/74F168 • MC54/74F169 AC CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C TA = –55°C to +125°C TA = 0°C to 70°C VCC = +5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% CL = 50 pF CL = 50 pF CL = 50 pF Min Max Min Max Min Maximum Clock Frequency 100 tPLH tPHL Propagation Delay 3.0 4.0 8.5 11.5 3.0 4.0 10.5 14 3.0 4.0 9.5 13 ns tPLH tPHL Propagation Delay 5.5 4.0 15.5 11 5.5 4.0 18 13.5 5.5 4.0 17 12.5 ns (F168) tPLH tPHL Propagation Delay 5.0 4.0 15.5 11 5.0 4.0 18 13.5 5.0 4.0 17 12.5 ns (F169) tPLH tPHL Propagation Delay 2.5 2.5 6.0 8.0 2.5 2.5 8.0 10 2.5 2.5 7.0 9.0 ns tPLH tPHL Propagation Delay 3.5 4.0 11 16 3.5 4.0 13.5 18.5 3.5 4.0 12.5 17.5 ns (F168) tPLH tPHL Propagation Delay 3.5 4.0 11 10.5 3.5 4.0 13.5 13 3.5 4.0 12.5 12 ns (F169) CP to TC CP to TC CET to TC U/D to TC U/D to TC 85 Unit fmax CP to Qn (PE HIGH or LOW) 60 Max MHz AC OPERATING REQUIREMENTS Symbol Parameter ts(H) ts(L) Setup Time, HIGH or LOW th(H) th(L) Hold Time, HIGH or LOW ts(H) ts(L) Setup Time, HIGH or LOW th(H) th(L) Hold Time HIGH or LOW ts(H) ts(L) Setup Time, HIGH or LOW th(H) th(L) Hold Time, HIGH or LOW ts(H) ts(L) Setup Time, HIGH or LOW (F168) ts(H) ts(L) Setup Time, HIGH or LOW (F169) th(H) th(L) Hold time, HIGH or LOW tw(H) tw(L) CP Pulse Width Pn to CP Pn to CP CEP or CET to CP CEP or CET to CP PE to CP PE to CP U/D to CP U/D to CP U/D to CP HIGH or LOW 54/74F 54F 74F TA = +25°C TA = –55°C to +125°C TA = 0°C to 70°C VCC = +5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% Min Max Min Max Min Max Unit 4.0 4.0 5.5 5.5 4.5 4.5 ns 3.0 3.0 3.5 3.5 3.5 3.5 ns 5.0 5.0 7.0 7.0 6.0 6.0 ns 0 0 0 0 0 0 ns 8.0 8.0 10 10 9.0 9.0 ns 0 0 0 0 0 0 ns 11 16.5 13.5 19 12.5 18 ns 11 7.0 13.5 9.0 12.5 8.0 ns 0 0 0 0 0 0 ns 5.0 5.0 8.0 8.0 5.5 5.5 ns FAST AND LS TTL DATA 4-85