MC54/74F259 8-BIT ADDRESSABLE LATCH The MC54/74F259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW Common Clear for resetting all latches, as well as an active LOW Enable. • Serial-to-Parallel Conversion • Eight Bits of Storage with Output of Each Bit Available • Random (Addressable) Data Entry • Active High Demultiplexing or Decoding Capability • Easily Expandable • Common Clear 8-BIT ADDRESSABLE LATCH FAST SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 FUNCTIONAL DESCRIPTION The MC54/74F259 has four modes of operation as shown in the Mode Select Table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states in the memory mode. All the latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the D input with all other outputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the MC54/74F259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The Truth Table below summarizes the operations of the MC54/74F259. N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 16 1 ORDERING INFORMATION CONNECTION DIAGRAM VCC MR E D Q7 Q6 Q5 Q4 16 15 14 13 12 11 10 9 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 1 A0 2 A1 3 A2 4 Q0 5 Q1 6 Q2 7 Q3 13 1 2 8 GND 3 D A0 14 15 E MR A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 FAST AND LS TTL DATA 4-133 5 6 7 9 10 11 12 MC54/74F259 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 54, 74 4.5 5.0 5.5 V 54 –55 25 125 74 0 25 70 VCC Supply Voltage TA Operating Ambient Temperature Range IOH Output Current — High 54, 74 –1.0 mA IOL Output Current — Low 54, 74 20 mA Q7 Q6 Q5 MR Q4 Q3 A2 A1 Q2 A0 Q1 D E Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FAST AND LS TTL DATA 4-134 °C MC54/74F259 MODE SELECT TABLE E MR L H L H H H L L Mode Addressable Latch Memory Active HIGH 8-Channel Demultiplexer Clear H = HIGH Voltage Level L = LOW Voltage Level FUNCTION TABLE Operating Mode Master Reset Demultiplex (Active HIGH Decoder when D = H) Store (Do Nothing) Addressable Latch Inputs Outputs MR E D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X X L L L L L L L L L L L • • • L L L L • • • L d d d • • • d L H L • • • H L L H • • • H L L L • • • H Q=d L L • • • L L Q=d L • • • L L L Q=d • • • L L L L • • • L L L L • • • L L L L • • • L L L L • • • L L L L • • • Q=d H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 H H H • • • H L L L • • • L d d d • • • d L H L • • • H L L H • • • H L L L • • • H Q=d q0 q0 • • • q0 q1 Q=d q1 • • • q1 q2 q2 Q=d • • • q2 q3 q3 q3 • • • q3 q4 q4 q4 • • • q4 q5 q5 q5 • • • q5 q6 q6 q6 • • • q6 q7 q7 q7 • • • Q=d H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition. q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. FAST AND LS TTL DATA 4-135 MC54/74F259 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Output Short Circuit Current (Note 2) ICC Power Supply Current Total, Output HIGH Total, Output LOW Typ Max 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V VCC = MIN, IIN = –18 mA 54, 74 2.5 V IOL = –1.0 mA VCC = MIN 74 2.7 V IOL = –1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 20 µA VCC = MAX, VIN = 2.7 V – 60 0.1 mA VCC = MAX,VIN = 7.0 V – 0.6 mA VCC = MAX, VIN = 0.5 V –150 mA VCC = MAX, VOUT = 0 V 46 mA VCC = MAX 75 mA VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more then one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = –55 to + 125°C VCC = 5.0 V ±10% CL = 50 pF TA = 0 to + 70°C VCC = 5.0 V ±10% CL = 50 pF Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay E to Qn 4.0 3.0 10.5 7.0 4.0 3.0 13 8.5 4.0 3.0 12 7.0 ns tPLH tPHL Propagation Delay Dn to Qn 3.5 3.0 9.0 6.5 3.5 2.5 11.5 8.5 3.5 2.5 10 7.0 ns tPLH tPHL Propagation Delay An to Qn 3.5 4.0 13 9.0 3.5 4.0 15.5 11 3.5 4.0 14.5 9.5 ns tPHL Propagation Delay MR to Qn 5.0 9.0 4.5 11.5 4.5 10 ns FAST AND LS TTL DATA 4-136 MC54/74F259 AC OPERATING REQUIREMENTS Symbol Parameter 54/74F 54F 74F TA = +25°C VCC = +5.0 V TA = –55 to +125°C VCC = 5.0 ±10% TA = 0 to +70 °C VCC = 5.0 V ±10% Min Max Min Max Min Max Unit ts(H) ts(L) Setup Time, HIGH or LOW Dn to E 4.0 4.0 5.0 5.0 4.0 4.0 ns th(H) th(L) Hold Time, HIGH or LOW Dn to E 2.0 2.0 2.0 2.0 2.0 2.0 ns ts(H) ts(L) Setup Time, HIGH or LOW A to E(a) 4.0 4.0 4.0 4.0 4.0 4.0 ns th(H) th(L) Hold Time, HIGH or LOW A to E(b) 0 0 0 0 0 0 ns tW E Pulse Width 4.0 4.0 4.0 ns tW MR Pulse Width 4.0 4.0 4.0 ns a. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. b. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. FAST AND LS TTL DATA 4-137