MOTOROLA MCM69P536CTQ7

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
32K x 36 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM69P536C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family,
PowerPC, 486, i960, and Pentium microprocessors. It is organized as 32K
words of 36 bits each. This device integrates input registers, an output register,
a 2–bit address counter, and high speed SRAM onto a single monolithic circuit
for reduced parts count in cache data RAM applications. Synchronous design
allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69P536C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and
synchronous write enable SW are provided to allow writes to either individual
bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected
byte writes SBx are asserted with SW. All bytes are written if either SGW is
asserted or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P536C operates from a 3.3 V power supply and all inputs and
outputs are LVTTL compatible.
Order this document
by MCM69P536C/D
MCM69P536C
TQ PACKAGE
TQFP
CASE 983A–01
• MCM69P536C–4 = 4 ns Access / 7.5 ns Cycle
MCM69P536C–4.5 = 4.5 ns Access / 8 ns Cycle
MCM69P536C–5 = 5 ns Access / 10 ns Cycle
MCM69P536C–6 = 6 ns Access / 12 ns Cycle
MCM69P536C–7 = 7 ns Access / 13.3 ns Cycle
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• 5 V Tolerant on all Pins (Inputs and I/Os)
• 100–Pin TQFP Package
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.
REV 3
2/9/98

Motorola, Inc. 1998
MOTOROLA
FAST SRAM
MCM69P536C
1
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
ADSC
BURST
COUNTER
K2
2
15
32K x 36 ARRAY
CLR
ADSP
2
SA
SA1
SA0
ADDRESS
REGISTER
15
13
SGW
SW
SBa
SBb
WRITE
REGISTER
a
36
36
WRITE
REGISTER
b
4
SBc
SBd
G
MCM69P536C
2
DATA–OUT
REGISTER
K
WRITE
REGISTER
d
K2
SE1
SE2
SE3
DATA–IN
REGISTER
WRITE
REGISTER
c
ENABLE
REGISTER
K
ENABLE
REGISTER
DQa – DQd
MOTOROLA FAST SRAM
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
VDD
VSS
K
SGW
SW
G
ADSC
ADSP
ADV
SA
SA
PIN ASSIGNMENT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQb
DQb
DQb
VDD
VSS
DQb
DQb
DQb
DQb
VSS
VDD
DQb
DQb
VSS
NC
VDD
NC
DQa
DQa
VDD
VSS
DQa
DQa
DQa
DQa
VSS
VDD
DQa
DQa
DQa
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
NC
NC
DQc
DQc
DQc
VDD
VSS
DQc
DQc
DQc
DQc
VSS
VDD
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDD
VSS
DQd
DQd
DQd
DQd
VSS
VDD
DQd
DQd
DQd
MOTOROLA FAST SRAM
MCM69P536C
3
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
85
ADSC
Input
Synchronous Address Status Controller: Initiates READ, WRITE, or
chip deselect cycle.
84
ADSP
Input
Synchronous Address Status Processor: Initiates READ, WRITE, or
chip deselect cycle (exception — chip deselect does not occur when
ADSP is asserted and SE1 is high).
83
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
DQx
I/O
86
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
89
K
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1,SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high–blocks ADSP or deselects chip when ADSC is asserted.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
4, 11, 15, 20, 27, 41, 54,
61, 65, 70, 77, 91
VDD
Supply
Power Supply: 3.3 V + 10%, – 5%.
5, 10, 17, 21, 26, 40, 55,
60, 67, 71, 76, 90
VSS
Supply
Ground.
64
NC
Input
14, 16, 38, 39, 42, 43, 49, 50, 66
NC
—
MCM69P536C
4
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
No Connection: There is no connection to the chip. For compatibility
reasons, it is recommended that this pin be tied low for system designs
that do not have a sleep mode associated with the cache/memory
controller. Other vendors’ RAMs may have implemented the Sleep
Mode (ZZ) feature.
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 through 4)
Address
Used
SE1
SE2
SE3
ADSP
Deselect
None
1
X
X
Deselect
None
0
X
1
Deselect
None
0
0
Deselect
None
X
Deselect
None
X
Begin Read
External
0
Begin Read
Next Cycle
ADSC
ADV
G3
DQx
Write 2, 4
X
0
X
X
High–Z
X
0
X
X
X
High–Z
X
X
0
X
X
X
High–Z
X
X
1
1
0
X
X
High–Z
X
0
X
1
0
X
X
High–Z
X
1
0
0
X
X
X
High–Z
READ
External
0
1
0
1
0
X
X
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
0
DQ
READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1
X
X
X
1
0
0
DQ
READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ
READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ
READ
Begin Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Begin Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
Begin Write
External
0
1
0
1
0
X
X
High–Z
WRITE
Continue Write
Next
X
X
X
1
1
0
X
High–Z
WRITE
Continue Write
Next
1
X
X
X
1
0
X
High–Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
NOTES: 1.
2.
3.
4.
X = Don’t Care. 1 = logic high. 0 = logic low.
Write is defined as either 1) any SBx and SW low or 2) SGW is low.
G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.
G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
4th Address (Internal)
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
SW
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte a
H
L
L
H
H
H
Write Byte b
H
L
H
L
H
H
Write Byte c
H
L
H
H
L
H
Write Byte d
H
L
H
H
H
L
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
MOTOROLA FAST SRAM
SBa
SBb
SBc
SBd
MCM69P536C
5
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Symbol
Value
Unit
VDD
– 0.5 to + 4.6
V
Vin, Vout
– 0.5 to 6.0
V
Iout
± 20
mA
Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VDD
Output Current (per I/O)
Package Power Dissipation (See Note 2)
Temperature Under Bias
Storage Temperature
PD
1.6
W
Tbias
– 10 to 85
°C
Tstg
– 55 to 125
°C
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
RθJA
40
25
°C/W
1, 2
Thermal Resistance Junction to Board (Bottom)
RθJB
17
°C/W
1, 3
Thermal Resistance Junction to Case (Top)
RθJC
9
°C/W
1, 4
Thermal Resistance Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method
1012.1).
MCM69P536C
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.6
V
Input Low Voltage
VIL
– 0.5*
—
0.8
V
Input High Voltage
VIH
2
—
5.5**
V
Supply Voltage
* VIL ≥ – 2 V for t ≤ tKHKH / 2.
** VIH ≤ 6 V for tKHKH / 2.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Max
Unit
Input Leakage Current (0 V ≤ Vin ≤ VDD) (Excluding LBO)
Ilkg(I)
—
±1
µA
Output Leakage Current (0 V ≤ Vin ≤ VDD)
Ilkg(O)
—
±1
µA
Notes
AC Supply Current (Device Selected,
All Outputs Open, Cycle Time ≥ tKHKH min)
MCM69P536C–4
MCM69P536C–4.5
MCM69P536C–5
MCM69P536C–6
MCM69P536C–7
IDDA
—
420
410
380
360
350
mA
1, 2, 3
CMOS Standby Supply Current (Deselected,
Clock (K) Cycle Time ≥ tKHKH,
All Inputs Toggling at CMOS Levels
Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
MCM69P536C–4
MCM69P536C–4.5
MCM69P536C–5
MCM69P536C–6
MCM69P536C–7
ISB1
—
170
170
150
140
130
mA
4
Clock Running Supply Current (Deselected,
Clock (K) Cycle Time ≥ tKHKH,
All Other Inputs Held to Static CMOS Levels
Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
MCM69P536C–4
MCM69P536C–4.5
MCM69P536C–5
MCM69P536C–6
MCM69P536C–7
ISB2
—
60
60
55
50
45
mA
4
Output Low Voltage (IOL = 8 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4 mA)
VOH
2.4
—
V
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing.
2. All addresses transition simultaneously low (LSB) and then high (HSB).
3. Data states are all zero.
4. Device in deselected mode as defined by the Truth Table.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
4
6
pF
Input/Output Capacitance
CI/O
—
7
9
pF
Parameter
MOTOROLA FAST SRAM
MCM69P536C
7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 30%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
69P536C–4
P
Parameter
69P536C–4.5
69P536C–5
69P536C–6
69P536C–7
S b l
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
Cycle Time
tKHKH
7.5
—
8
—
10
—
12
—
13.3
—
ns
Clock High Pulse Width
tKHKL
3
—
3
—
3
—
4
—
4.5
—
ns
Clock Low Pulse Width
tKLKH
3
—
3
—
3
—
4
—
4.5
—
ns
Clock Access Time
tKHQV
—
4
—
4.5
—
5
—
6
—
7
ns
Output Enable to Output
Valid
tGLQV
—
4
—
4.5
—
5
—
5
—
6
ns
Clock High to Output Active
tKHQX1
1.5
—
1.5
—
0
—
0
—
0
—
ns
4
Clock High to Output Change
tKHQX2
1.5
—
1.5
—
2
—
2
—
2
—
ns
4
Output Enable to Output
Active
tGLQX
0
—
0
—
0
—
0
—
0
—
ns
4
Output Disable to Q High–Z
tGHQZ
—
4
—
4.5
—
5
—
5
—
5
ns
4, 5
Clock High to Q High–Z
tKHQZ
2
4
2
4.5
2
5
2
5
2
5
ns
4, 5
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
2
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VT = 1.5 V
Figure 1. AC Test Load
MCM69P536C
8
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
MCM69P536C
9
Q(n)
B
SINGLE READ
tKHQX1
A
Q(A)
t KHQV
tKHKL
NOTE: E low = SE2 high and SE3 low.
W low = SGW low and/or SW and SBx low.
DESELECTED
tKHQZ
DQx
G
W
E
SE1
ADV
ADSC
ADSP
SA
K
tKHKH
tKHQX2
Q(B)
Q(B+2)
BURST READ
Q(B+1)
tGHQZ
Q(B+3)
BURST WRAPS AROUND
tKLKH
Q(B)
ADSP, SA
SE2, SE3
IGNORED
READ/WRITE CYCLES
D(C)
C
D(C+2)
BURST WRITE
D(C+1)
D(C+3)
tGLQX
D
SINGLE READ
Q(D)
t KHQV
APPLICATION INFORMATION
The MCM69P536C BurstRAM is a high speed synchronous SRAM that is intended for use primarily in secondary or
level two (L2) cache memory applications. L2 caches are
found in a variety of classes of computers — from the desktop personal computer to the high–end servers and transaction processing machines. For simplicity, the majority of L2
caches today are direct mapped and are single bank implementations. These caches tend to be designed for bus
speeds in the range of 33 to 66 MHz. At these bus rates,
non–pipelined (flow–through) BurstRAMs can be used since
their access times meet the speed requirements for a minimum–latency, zero–wait state L2 cache interface. Latency is
a measure (time) of “dead” time the memory system exhibits
as a result of a memory request.
For those applications that demand bus operation at
greater than 66 MHz or multi–bank L2 caches at 66 MHz, the
pipelined (register/register) version of the 32Kx36 BurstRAM
(MCM69P536C) allows the designer to maintain zero–wait
state operation. Multiple banks of BurstRAMs create additional bus loading and can cause the system to otherwise
miss its timing requirements. The access time (clock–to–
valid–data) of a pipelined BurstRAM is inherently faster than
a non–pipelined device by a few nanoseconds. This does not
come without cost. The cost is latency — “dead” time.
Since most L2 caches are tied to the processor bus and
bus speeds continue to increase over time, pipelined (R/R)
BurstRAMs are the best choice in achieving zero–wait state
L2 cache performance. At bus speeds ranging from 66 MHz
to 100 MHz, pipelined BurstRAMs are able to provide fast
clock to valid data times required of these high speed buses.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for 68K–,
PowerPC–, 486–, i960–, and Pentium–based systems,
these SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous interface can make use of the MCM69P536C. The burst counter
feature of the BurstRAM can be disabled, and the SRAM can
be configured to act upon a continuous stream of addresses.
See Figure 2.
CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL)
Non–Burst
ADSP
ADSC
ADV
SE1
SE2
LBO
Sync Non–Burst,
Pipelined SRAM
H
L
H
L
H
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
SE3
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
READS
D(G)
D(H)
WRITES
Figure 2. Example Configuration as Non–Burst Synchronous SRAM
MCM69P536C
10
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
69P536C XX
X
X
Motorola Memory Prefix
Blank = Trays, R = Tape and Reel
Part Number
Speed (4 = 4 ns, 4.5 = 4.5 ns, 5 = 5 ns,
6 = 6 ns, 7 = 7 ns)
Package (TQ = TQFP)
Full Part Numbers — MCM69P536CTQ4
MCM69P536CTQ4.5
MCM69P536CTQ5
MCM69P536CTQ6
MCM69P536CTQ7
MCM69P536CTQ4R
MCM69P536CTQ4.5R
MCM69P536CTQ5R
MCM69P536CTQ6R
MCM69P536CTQ7R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM69P536C
11
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
e
4X
0.20 (0.008) H A–B D
2X 30 TIPS
e/2
0.20 (0.008) C A–B D
–D–
80
51
B
50
81
–A–
–X–
B
E/2
X=A, B, OR D
–B–
VIEW Y
E1 E
BASE
METAL
PLATING
c
31
100
1
30
D1/2
0.13 (0.005)
0.20 (0.008) C A–B D
A
q
2
0.10 (0.004) C
–H–
–C–
SEATING
PLANE
q
3
VIEW AB
S
S
q
1
0.25 (0.010)
R2
A2
L2
L
L1
R1
M
C A–B
S
D
S
SECTION B–B
2X 20 TIPS
A1
c1
b
D/2
D1
D
0.05 (0.002)
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
b1
E1/2
GAGE PLANE
q
VIEW AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
DIM
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
L2
S
R1
R2
q
1
2
q3
q
q
MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.22
0.38
0.22
0.33
0.09
0.20
0.09
0.16
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
–––
0.08
–––
0.08
0.20
0_
7_
0_
–––
11 _
13 _
11 _
13 _
INCHES
MIN
MAX
–––
0.063
0.002
0.006
0.053
0.057
0.009
0.015
0.009
0.013
0.004
0.008
0.004
0.006
0.866 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
0.018
0.030
0.039 REF
0.020 REF
0.008
–––
0.003
–––
0.003
0.008
0_
7_
0_
–––
11 _
13 _
11 _
13 _
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CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM69P536C
12
◊
MOTOROLAMCM69P536C/D
FAST SRAM