Order this document by MTP55N06Z/D SEMICONDUCTOR TECHNICAL DATA N–Channel Enhancement–Mode Silicon Gate TMOS POWER FET 55 AMPERES 60 VOLTS RDS(on) = 18 mΩ This advanced high voltage TMOS E–FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain–to–source diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Capability Specified at Elevated Temperature • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Low Stored Gate Charge for Efficient Switching • Internal Source–to–Drain Diode Designed to Replace External Zener Transient Suppressor–Absorbs High Energy in the Avalanche Mode • ESD Protected. Designed to Typically Withstand 400 V Machine Model and 4000 V Human Body Model. D G CASE 221A–06, Style 5 TO–220AB S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS 60 Vdc Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc Gate–to–Source Voltage — Continuous Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous @ TC = 25°C Drain Current — Continuous @ TC = 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 55 35.5 165 Adc Total Power Dissipation @ TC = 25°C Derate above 25°C PD 113 0.91 Watts W/°C TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 mH, RG = 25 Ω) EAS 454 mJ Thermal Resistance — Junction–to–Case Thermal Resistance — Junction–to–Ambient RθJC RθJA 1.1 62.5 °C/W TL 260 °C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Apk This document contains information on a new product. Specifications and information herein are subject to change without notice. E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. REV 1 TMOS Motorola Motorola, Inc. 1997 Power MOSFET Transistor Device Data 1 MTP55N06Z ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 — — 53 — — — — — — 1.0 10 — — 100 2.0 — 3.0 6.0 4.0 — — 14 16 — — 0.825 0.74 1.2 1.0 gFS 12 15 — Mhos Ciss — 1390 1950 pF Coss — 520 730 Crss — 119 238 td(on) — 27 54 tr — 157 314 td(off) — 116 232 tf — 126 252 QT — 40 56 Q1 — 7.0 — Q2 — 18 — Q3 — 15 — — — 0.93 0.82 1.1 — trr — 57 — ta — 32 — tb — 25 — QRR — 0.11 — — — 3.5 4.5 — — — 7.5 — OFF CHARACTERISTICS (Cpk ≥ 2.0) Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C µAdc nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) (Cpk ≥ 2.0) Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 27.5 Adc) (Cpk ≥ 2.0) VGS(th) Vdc RDS(on) Drain–to–Source On–Voltage (VGS = 10 Vdc) (ID = 55 Adc) (ID = 27.5 Adc, TJ = 125°C) mΩ VDS(on) Forward Transconductance (VDS = 4.0 Vdc, ID = 27.5 Adc) mV/°C Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, Vdc VGS = 0 Vdc, Vdc f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time Rise Time Turn–Off Delay Time (VDD = 30 Vdc, Vd ID = 55 Adc, Ad VGS(on) = 10 Vdc Vdc, RG = 9.1 Ω)) Fall Time Gate Charge (See Figure 8) ((VDS = 48 Vdc, Vd , ID = 55 Adc, Ad , VGS = 10 Vdc) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 55 Adc, VGS = 0 Vdc) (IS = 55 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time ((IS = 55 Adc, Ad , VGS = 0 Vdc, Vd , dIS/dt = 100 A/µs) Reverse Recovery Stored Charge VSD Vdc ns µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS nH (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTP55N06Z 60 60 9.0 V 8.0 V 50 VDS ≥ 10 V TJ = 25°C ID , DRAIN CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) 10 V 6.0 V 7.0 V 40 30 20 5.0 V 10 50 40 30 100°C 25°C 20 10 TJ = –55°C VGS = 4.0 V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.5 4.0 5.0 2.0 2.4 2.8 3.2 3.6 4.4 4.0 4.8 5.2 5.6 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics 24 VGS = 10 V TJ = 100°C 20 16 25°C 12 –55°C 8.0 20 10 30 40 50 60 R DS(on) , DRAIN–TO–SOURCE RESISTANCE (m W ) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 6.0 TJ = 25°C 14.6 VGS = 10 V 14.2 13.8 15 V 13.4 13.0 10 20 40 30 50 ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage 1.8 1.6 60 1000 125°C VGS = 0 V VGS = 10 V ID = 15 A 100 1.4 1.2 1.0 100°C 10 1.0 TJ = 25°C 0.1 0.8 0.6 –50 6.4 15.0 ID, DRAIN CURRENT (AMPS) IDSS , LEAKAGE (nA) R DS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) R DS(on) , DRAIN–TO–SOURCE RESISTANCE (m W ) 0 0.01 –25 0 25 50 75 100 125 150 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–to–Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 60 3 VDS = 0 V TJ = 25°C Ciss 3200 C, CAPACITANCE (pF) VGS = 0 V VGS , GATE–TO–SOURCE VOLTAGE (VOLTS) 4000 2400 Crss Ciss 1600 Coss 800 Crss 0 –10 12 48 QT 10 40 VGS 8.0 Q1 6.0 16 2.0 TJ = 25°C ID = 30 A Q3 0 10 5.0 15 20 0 25 4.0 VDS 8.0 VDS 8.0 12 16 20 24 0 28 32 36 40 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate–to–Source and Drain–to–Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 30 IS , SOURCE CURRENT (AMPS) TJ = 25°C ID = 30 A VDD = 30 V VGS = 10 V t, TIME (ns) 24 4.0 GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) tr tf td(off) 100 td(on) 10 TJ = 25°C VGS = 0 V 20 10 0 1.0 0.5 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90 0.94 100 10 RG, GATE RESISTANCE (OHMS) VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 500 100 ms VGS = 20 V SINGLE PULSE TC = 25°C EAS , SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) 100 ID , DRAIN CURRENT (AMPS) Q2 0 –5.0 VGS 10 ms 10 1.0 ms 10 ms dc 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LMIT ID = 30 A 400 300 200 100 0 0.1 0.1 4 32 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) MTP55N06Z 1.0 10 100 25 50 75 100 125 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature Motorola TMOS Power MOSFET Transistor Device Data MTP55N06Z r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.0001 0.00001 0.001 0.01 0.1 1.0 10 t, TIME (seconds) Figure 13. Thermal Response PACKAGE DIMENSIONS –T– B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. SEATING PLANE C F T S 4 A Q 1 2 3 STYLE 5: PIN 1. 2. 3. 4. U H K Z L R V J G D N GATE DRAIN SOURCE DRAIN DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 CASE 221A–06 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 5 MTP55N06Z Motorola reserves the right to make changes without further notice to any products herein. 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