Order this document by MTY100N10E/D SEMICONDUCTOR TECHNICAL DATA Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate TMOS POWER FET 100 AMPERES 100 VOLTS RDS(on) = 0.011 OHM This advanced TMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters, PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature D G MAXIMUM RATINGS (TC = 25°C unless otherwise noted) CASE 340G–02, STYLE 1 TO–264 S Symbol Value Unit Drain–Source Voltage VDSS 100 Vdc Drain–Gate Voltage (RGS = 1 MΩ) VDGR 100 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous @ TC = 25°C Drain Current — Single Pulse (tp ≤ 10 µs) ID IDM 100 300 Adc Apk Total Power Dissipation Derate above 25°C PD 300 2.38 Watts W/°C TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25 Ω ) EAS 250 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient RθJC RθJA 0.42 40 °C/W TL 260 °C Rating Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 2 Motorola Motorola, Inc.TMOS 1995 Power MOSFET Transistor Device Data 1 MTY100N10E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 — — 115 — — Vdc mV/°C — — — — 10 200 — — 100 nAdc 2.0 — — 7 4 — Vdc mV/°C — — 0.011 Ohm — — 1.0 — 1.2 1.0 gFS 30 49 — mhos Ciss — 7600 10640 pF Coss — 3300 4620 Crss — 1200 2400 td(on) — 48 96 tr — 490 980 td(off) — 186 372 OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0, ID = 250 µA) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS µAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 50 Adc) RDS(on) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 100 Adc) (ID = 50 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time (VDD = 50 Vdc, ID = 100 Adc, VGS = 10 Vdc, RG = 9.1 Ω) Rise Time Turn–Off Delay Time Fall Time ns tf — 384 768 QT — 270 378 Q1 — 50 — Q2 — 150 — Q3 — 118 — — — 1 0.9 1.2 — trr — 145 — ta — 90 — tb — 55 — QRR — 2.34 — µC Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD — 4.5 — nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 13 — nH Gate Charge (See Figure 8) (VDS = 80 Vdc, ID = 100 Adc, VGS = 10 Vdc) nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 100 Adc, VGS = 0 Vdc) (IS = 100 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (See Figure 14) (IS = 100 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTY100N10E TYPICAL ELECTRICAL CHARACTERISTICS VGS = 10 V 9V 160 120 TJ = 25°C 8V 7V I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 200 120 6V 80 40 VDS ≥ 10 V 100 80 60 40 100°C 20 5V TJ = – 55°C 25°C 0 2 4 6 8 10 2 3 4 5 7 6 8 9 Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics VGS = 10 V TJ = 100°C 0.014 0.012 25°C 0.01 0.008 – 55°C 0 100 50 200 150 RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 0.016 0.006 0 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0.018 10 0.011 TJ = 25°C VGS = 10 V 0.0105 0.01 0.0095 15 V 0.009 0.0085 0.008 0 50 100 150 200 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage 1.8 1.6 1000000 VGS = 0 V VGS = 10 V ID = 50 A 100000 I DSS , LEAKAGE (nA) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) 0 1.4 1.2 1 1000 100°C 100 25°C 10 0.8 0.6 – 50 TJ = 125°C – 25 0 25 50 75 100 125 150 1 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–To–Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 120 3 MTY100N10E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 24000 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 20000 Ciss 16000 12000 Crss Ciss 8000 Coss 4000 Crss 0 10 5 0 VGS 5 10 15 20 25 VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data 120 QT 10 100 VGS 8 80 Q2 Q1 6 60 TJ = 25°C ID = 100 A 4 2 0 40 20 VDS Q3 0 50 100 150 200 0 300 250 10000 t, TIME (ns) 12 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) MTY100N10E VDD = 50 V ID = 100 A VGS = 10 V TJ = 25°C 1000 tr tf td(off) 100 td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate Charge versus Gate–to–Source Voltage 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN–TO–SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 100 VGS = 0 V TJ = 25°C 80 60 40 20 0 0.5 0.6 0.7 0.8 0.9 1 1.1 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reli- Motorola TMOS Power MOSFET Transistor Device Data able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 5 MTY100N10E SAFE OPERATING AREA 250 VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 10 µs 100 100 µs 1 ms 10 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 0.1 1 10 ID = 100 A 200 150 100 50 0 100 25 50 75 100 125 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1 D = 0.5 0.2 0.1 P(pk) 0.05 0.1 0.02 0.01 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 1.0E+00 1.0E+01 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTY100N10E PACKAGE DIMENSIONS 0.25 (0.010) M T B M –T– C E U N A 1 R 2 L 3 P K W F 2 PL G J H D 3 PL 0.25 (0.010) M Y Q S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D E F G H J K L N P Q R U W MILLIMETERS MIN MAX 2.8 2.9 19.3 20.3 4.7 5.3 0.93 1.48 1.9 2.1 2.2 2.4 5.45 BSC 2.6 3.0 0.43 0.78 17.6 18.8 11.0 11.4 3.95 4.75 2.2 2.6 3.1 3.5 2.15 2.35 6.1 6.5 2.8 3.2 INCHES MIN MAX 1.102 1.142 0.760 0.800 0.185 0.209 0.037 0.058 0.075 0.083 0.087 0.102 0.215 BSC 0.102 0.118 0.017 0.031 0.693 0.740 0.433 0.449 0.156 0.187 0.087 0.102 0.122 0.137 0.085 0.093 0.240 0.256 0.110 0.125 STYLE 1: PIN 1. GATE 2. DRAIN 3. SOURCE CASE 340G–02 TO–264 ISSUE E Motorola TMOS Power MOSFET Transistor Device Data 7 MTY100N10E Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 8 ◊ *MTY100N10E/D* Motorola TMOS Power MOSFET Transistor Device Data MTY100N10E/D