www.fairchildsemi.com AN-6982 Power Factor Correction Converter Design with FAN6982 Introduction The FAN6982 is a 14-pin, Continuous Conduction Mode (CCM) Power Factor Correction (PFC) controller IC, that employs leading-edge modulation for average current control and has a number of advanced features for better performance and reliability. The variable output voltage function (range function) reduces PFC output voltage at light-load and low-line conditions to improve light-load efficiency, but can be also easily disabled using EN pin. The RDY signal can be used for power-on sequence control of the downstream DC/DC converter. A TriFault Detect™ function helps reduce external components and provides full protection for feedback loops such as open, short, and over voltage. FAN6982 also includes PFC soft- LBOOST F1 start, peak current limiting, line feed-forward, and input voltage brownout protection. This application note describes the theory of operation and step-by-step design considerations for a power factor correction power supply using the FAN6982 controller. A typical application circuit is shown in Figure 1, where the supply voltage, VDD, is supplied from a standby auxiliary power supply and the supply voltage for the downstream converter is controlled by the RDY pin. DBOOST VBOUT VOUT AC Input CIF2 RDRV Q1 CIF1 D2 RLF RRMS1 CRMS1 RIAC RRMS2 PWM Controller CIC2 RIC RFB1 IEA VEA IAC FBPFC RVC VREF VRMS RRMS3 CLF vCC CIC1 ISENSE CRMS2 Downstream DC/DC Converter RPL RCS D1 CBOOST VDD RDY OPFC EN PGND RT/CT SGND CVC2 CDD RFB2 CFB CVC1 Rreg1 FAN6982 Q2 REN Range Enabled/Disabled VEN = VVREF : Enabled VEN = GND : Disabled CT RT CREF Rreg2 Rreg3 CRDY From Standby Auxiliary Power Supply Figure 1. Typical FAN6982 Application Circuit © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com AN-6982 APPLICATION NOTE Functional Description where the internal resistor RM is typically 5.7kΩ; the output current of gain modulator, IMO, is given as a function of input current of IAC pin; and voltages of the VRMS and VEA pins are calculated as: Widely used operation modes for the boost converter are continuous conduction mode (CCM) and boundary conduction mode (BCM). These two descriptive names refer to the current flowing through the energy storage inductor of the boost converter, as depicted in Figure 2. The inductor current in CCM is continuous; while in BCM, the new switching period is initiated when the inductor current returns to zero, which is at the boundary of continuous conduction and discontinuous conduction operations. CCM PFC is commonly used for high-power applications above 300W since the inductor current has a small ripple and higher power factor can be obtained than BCM operation. Due to the reverse-recovery current of the output diode, using a high-speed diode with a small reverse recovery current is crucial to achieve high efficiency and low EMI. I MO = I AC × 10.5 × (VEA - 0.7) VRMS 2 (VEA MAX - 0.7) (2) Figure 3. Current and Voltage Control Feedback Circuit = I MO ⋅ RM RCS Figure 2. CCM vs. BCM Control Figure 4. Operation Waveforms of CCM PFC The voltage-control loop regulates PFC output voltage using an internal error amplifier such that the FBPFC voltage is same as the internal reference of 2.5V. Note that, from Equation (2), the voltages of VEA should be almost constant to obtain pure sinusoidal reference for the input current shaping. Because there is always twice the line frequency ripple in the PFC output voltage, a narrow bandwidth should be used for the output voltage-control loop to minimize the line frequency ripple. Otherwise, the control loop tries to remove the output voltage ripple, changing the error amplifier output voltage as shown in Figure 5, which causes distortion of the input current. Current and Voltage Control of PFC As shown in Figure 3, the FAN6982 employs two control loops for power factor correction: a current-control loop and a voltage-control loop. The current-control loop shapes inductor current, as shown in Figure 4, such that voltage drop across the internal resistor RM should be same as the averaged voltage drop across the sensing resistor, RCS, during one switching cycle: 1 TS TS ∫ (I L ⋅ RCS )dt = I MO ⋅ RM (1) 0 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 2 AN-6982 APPLICATION NOTE G∝ 1 VRMS 2 IAC VBOUT BW<<Twice Line Frequency VEAO IREF VRMS IIN VRMS-UVP Figure 6. Modulation Gain Characteristics IAC VBOUT BW VEAO Twice Line Frequency IAC VEAO IREF IIN IIN IREF Figure 5. Control Bandwidth and Inductor Current Figure 7. Effect of Line Feed-Forward Line Feed-Forward Line Voltage Sensing Since rectified line voltage provides the sinusoidal reference for the input current shaping of the currentcontrol loop, the increase of the line voltage causes increase of input current. However, from an input and output power balance point of view, input current should be reduced when input voltage increases to keep input power same. When the error amplifier has adequate bandwidth, as in most DC-DC applications, it is able to maintain regulation within a tolerable output voltage range during input voltage changes. However, for PFC applications, some severe output voltage overshoot/undershoot is unavoidable during line transient due to the narrow bandwidth of output regulation control loop. Since FAN6982 uses line voltage information for line feedforward and brownout protection, the RMS value of line voltage should be sensed. To sense the RMS value of the line voltage, an averaging circuit with two poles is typically employed, as shown in Figure 3. The voltage of VRMS pin in normal PFC operation is given as: VRMS = VLINE (3) where VLINE is RMS value of line voltage. Once PFC stops switching operation, the junction capacitance of bridge diode and input bypass capacitor are not discharged and VIN of Figure 3 is clamped at the peak of the line voltage as illustrated in Figure 8. Then, the voltage of VRMS pin is given by: One measure to address this issue is line feed-forward, which changes the gain of the gain modulator as inversely proportional to the RMS value of line voltage, as shown in Figure 6. This negates the effect of input voltage variations on the output voltage and eliminates the need for any correction by the error amplifier, as shown in Figure 7. VRMS NS = VLINE The second benefit of line feed-forward is that the output of the error amplifier becomes directly proportional to the input power of the converter, independently of line voltage variation. This makes the control-to-output transfer function independent of line voltage and simplifies control loop design. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 2 RRMS 3 2 ⋅ RRMS 1 + RRMS 2 + RRMS 3 π 2 RRMS 3 RRMS 1 + RRMS 2 + RRMS 3 (4) Therefore, the voltage divider for VRMS should be designed considering the brownout protection trip point and PFC startup threshold (1.05V/1.9V). www.fairchildsemi.com 3 AN-6982 APPLICATION NOTE Oscillator The internal oscillator frequency is determined by the timing resistor and capacitor on the RT/CT pin. The frequency of the internal oscillator is given by: 1 (6) 0.56 ⋅ RT ⋅ CT + 360CT Dead time for the PFC gate drive signal is determined by: fOSC = tDEAD = 360CT (7) Dead time should be smaller than 2% of the switching period to minimize line current distortion around the line zero crossing. The duty cycle is determined by comparing IEA voltage with the sawtooth waveform on the RT/CT pin. Note that FAN6982 employs leading-edge modulation and the duty cycle reduces as IEA voltage increases. Figure 8. VRMS According to the PFC Operation Range Function To improve system efficiency at low AC line voltage and light load condition, FAN6982 provides two-level PFC output voltage. As shown in Figure 9, FAN6982 monitors VEA and VRMS voltages to adjust the PFC output voltage. When VEA and VRMS are lower than the thresholds, an internal current source of 20µA is enabled and flows through RFB2, increasing the voltage of the FBPFC pin. This causes the PFC output voltage to reduce when 20µA is enabled, calculated as: VOPFC 2 = RFB1 + RFB 2 × (2.5 - 20 μA × RFB 2 ) RFB 2 Figure 10. Timing Diagram (5) RDY Function The RDY function shown in Figure 11 is controlled by the voltage of FBPFC. When the voltage of FBPFC is over than 96% of 2.5V, the RDY pin is be connected to SGND. Meanwhile, the internal MOSFET is turned off and the RDY pin is floated when FBPFC pin voltage is lower than 46% of 2.5V. This is typically used to control the startup and shutdown of downstream converter by connecting and disconnecting supply voltage of the downstream converter as shown in Figure 11. Typically, a bypass capacitor is connected across the RDY pin and ground to minimize noise interference. It is typical to set the second boost output voltage as 340V~300V. Figure 9. Two-Level PFC Output Block Figure 11. RDY Application Circuit © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 4 AN-6982 APPLICATION NOTE Soft-Start Function Nominal Output Voltage 96% of Nominal Output Voltage The soft-start is combined with RDY pin operation. During startup, the RDY pin remains floating until the PFC output voltage reaches 96% of its nominal value. When the supply voltage of the downstream converter is controlled by the RDY pin, the PFC stage starts with no load since the downstream converter does not operate until the PFC output voltage is built to a certain level. VOUT Usually the error amplifier output VEA is saturated to HIGH during the startup since the actual output voltage is less than the target value. VEA remains saturated to HIGH until the PFC output voltage reaches its target value. Once the PFC output reaches its target value, the error amplifier comes out of saturation. However, it takes several line cycles for VEA to drop to its proper value for the output regulation, which delivers more power to the load than required, causing output voltage overshoot. VEA 2.8V Input Line Current To prevent output voltage overshoot during startup caused by the saturation of error amplifier; FAN6982 clamps the error amplifier output voltage (VEA) at 2.8V, which is half of its maximum value, until PFC output reaches 96% of its nominal value. Once the PFC output voltage reaches 96% of its nominal value, the clamping function of VEA is disabled. Then the voltage of PFC output is regulated by voltage control loop. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 VEASAT VDD of Downstream DC/DC Figure 12. PFC Soft-Start www.fairchildsemi.com 5 AN-6982 APPLICATION NOTE Design Considerations In this section, a design procedure is presented using the schematic in Figure 13 as reference. A 350W PFC power supply application with universal input range is selected as a design example. The design specifications are summarized in Table 1. Table 1. Design Specifications Brownout Protection Line Voltage 72VAC Line Voltage Range 85~264VAC AC Input Voltage Frequency fline = 50 ~ 60Hz Nominal PFC output voltage VBOUT = 387V Minimum PFC Output Voltage During Holdup Time 310V Hold-up Time tHLD = 20ms Rated Output Power POUT = 350W Efficiency η = 0.94 Switching Frequency fSW = 65KHz PFC Inductor Ripple Current Maximum ∆IL is 50% of Average Inductor Current at Full Load PFC Output Voltage Ripple 12VPP LBOOST F1 DBOOST VBOUT VOUT AC Input CIF2 RDRV Q1 CIF1 D2 RLF RRMS1 CRMS1 RIAC RRMS2 PWM Controller CIC2 RIC RFB1 IEA VEA IAC FBPFC RVC VREF VRMS RRMS3 CLF vCC CIC1 ISENSE CRMS2 Downstream DC/DC Converter RPL RCS D1 CBOOST VDD RDY OPFC EN PGND RT/CT SGND CVC2 CDD RFB2 CFB CVC1 Rreg1 FAN6982 Q2 REN Range Enabled/Disabled VEN = VVREF : Enabled VEN = GND : Disabled CT RT CREF Rreg2 Rreg3 CRDY From Standby Auxiliary Power Supply Figure 13. Reference Circuit for Design Example © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 6 AN-6982 APPLICATION NOTE 2 RRMS 3 2 ⋅ RRMS 1 + RRMS 2 + RRMS 3 π (10) 2 RRMS 3 RRMS1 + RRMS 2 + RRMS 3 (11) [STEP-1] Frequency Setting VRMS −UVL = VLINE .BO The switching frequency is determined by the timing resistor and capacitor (RT and CT) as: 1 f SW ≅ (8) 0.56 ⋅ RT ⋅ CT VRMS −UVH < VLINE .MIN where VRMS-UVL and VRMS-UVH are the brownout/in thresholds of VRMS. The timing capacitor value determines the maximum duty cycle of PFC gate drive signal as: It is typical to set RRMS2 as 10% of RRMS1. The poles of the low-pass filter are given as: tDEAD = 1 − 360 ⋅ CT ⋅ f SW (9) tSW It is typical to use a 470pF~1nF capacitor for 50~75kHz switching frequency operation, such that maximum duty cycle of 99~98% is obtained. DMAX . PFC = 1 − (Design Example) Since the switching frequency is f P1 ≅ 1 2π ⋅ CRMS 1 ⋅ RRMS 2 (12) fP2 ≅ 1 2π ⋅ CRMS 2 ⋅ RRMS 3 (13) 65kHz, CT is selected as 1nF to obtain maximum duty cycle as: To properly attenuate the twice line frequency ripple in VRMS, it is typical to set the poles around 10~20Hz. DMAX . PFC = 1 − 360 ⋅ CT ⋅ f SW = 0.98 The resistor RIAC should be large enough to prevent saturation of the gain modulator as: Then, the timing resistor is determined as: 1 = 27 k Ω RT = 0.56 f SW CT 2VLINE. BO MAX ⋅G < 159μ A (14) RIAC where VLINE.BO is the brownout protection line voltage, GMAX is the maximum modulator gain when VRMS is 1.08V (which is typically 9 as can be found in the datasheet), and 159µA is the maximum output current of the gain modulator. [STEP-2] Line Sensing Circuit Design FAN6982 senses the RMS value and instantaneous value of line voltage using the VRMS and IAC pins, respectively, as shown in Figure 14. The RMS value of the line voltage is obtained by an averaging circuit using low-pass filter with two poles. Meanwhile, the instantaneous line voltage information is obtained by sensing the current flowing into the IAC pin through RIAC. (Design Example) The brownout protection thresholds are 1.05V (VRMS-UVL) and 1.9V (VRMS-UVH), respectively. Then, the scaling down factor of the voltage divider is: RRMS 3 V π = RMS −UVL ⋅ RRMS 1 + RRMS 2 + RRMS 3 VLINE .BO 2 2 = 1.05 π ⋅ = 0.0162 72 2 2 The startup of the PFC controller at the minimum line voltage is checked as: VLINE .MIN ⋅ 2 RRMS 3 = 85 ⋅ 2 ⋅ 0.0162 = 1.95 > 1.9V RRMS 1 + RRMS 2 + RRMS 3 The resistors of the voltage divider network are selected as RRMS1=2MΩ, RRMS2=200kΩ, and RRMS3=36kΩ. VRMS VIN To place the poles of the low-pass filter at 15Hz and 22Hz, the capacitors are obtained as: 1 1 CRMS 1 = = = 53nF 2π ⋅ f P1 ⋅ RRMS 2 2π ⋅ 15 ⋅ 200 × 103 CRMS 2 ≅ Figure 14. Line-Sensing Circuits 2π ⋅ f P 2 ⋅ RRMS 3 = 1 = 200nF 2π ⋅ 22 ⋅ 36 × 103 The condition for Resistor RIAC is: 2VLINE. BO MAX 2 ⋅ 72 ⋅ 9 RIAC > ⋅G = = 5.8M Ω 159 × 10−6 159 × 10−6 RMS sensing circuit should be designed considering the nominal operation range of line voltage and brownout protection trip point as: © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 1 Therefore, 6MΩ resistor is selected for RIAC. www.fairchildsemi.com 7 AN-6982 APPLICATION NOTE (Design Example) The largest ripple factor is obtained at a line voltage as: [STEP-3] PFC Inductor Design The duty cycle of boost switch at the peak of line voltage is given as: DLP = VBOUT − 2VLINE VBOUT (15) 2VLINE VBOUT − 2VLINE 1 ⋅ ⋅ LBOOST VBOUT f SW LBOOST = (16) 2 POUT VLINE ⋅η The inductor current ripple at low line is obtained as: ΔI L I L. AVG = η ⋅ VLINE 2 VBOUT − 2VLINE 1 ⋅ ⋅ POUT ⋅ LBOOST VBOUT f SW = I L. AVG = I L PK = I L. AVG + ΔI L / 2 = 6.19 + 1.39 / 2 = 6.89 A (19) [STEP-4] PFC Output Capacitor Selection ΔI L. AVG IL K RF = 2 POUT 2 ⋅ 350 = = 6.19 A VLINE .MIN ⋅η 85 ⋅ 0.94 The maximum of the inductor current at low line is obtained as: As depicted in Figure 15, the ripple factor has the maximum value when the line voltage is: VLINE .MRF = 2 ⋅ 85 387 − 2 ⋅ 85 1 ⋅ ⋅ = 1.39 A 387 916 × 10−6 65 × 103 The average inductor current at the peak of the line voltage for low line is obtained as: (18) 2VBOUT 3 2VLINE VBOUT − 2VLINE 1 ⋅ ⋅ LBOOST VBOUT f SW ΔI L = (17) The ripple factor (KRF), the ratio between the inductor current ripple and average inductor current at the peak of line voltage load is given as: K RF = 2VBOUT 2 ⋅η 1 2 ⋅ 387 2 ⋅ 0.94 1 ⋅ = ⋅ K RF ⋅ POUT 27 f SW 0.5 ⋅ 350 27 ⋅ 65 × 103 = 916 μ H The average of boost inductor current over one switching cycle at the peak of the line voltage is given as: I L. AVG = 2 ⋅ 387 = 182VAC 3 With the ripple current specification (50%), the boost inductor is obtained as: Then the current ripple of the boost inductor at the peak of line voltage is given as: ΔI L = 2VBOUT = 3 VLINE = The output voltage ripple should be considered when selecting the PFC output capacitor. Figure 16 shows the twice line frequency ripple on the output voltage. With a given specification of output ripple, the condition for the output capacitor is obtained as: I L. AVG CBOUT > ΔI L I BOUT 2π ⋅ f LINE ⋅ VBOUT , RIPPLE (21) where IBOUT is nominal output current of boost PFC stage and VBOUT,RIPPLE is the peak-to-peak output voltage ripple specification. I L. AVG The hold-up time also should be considered when determining the output capacitor as: CBOUT > 85VAC 2VBOUT / 3 2 POUT ⋅ tHOLD VBOUT 2 − VBOUT , MIN 2 (22) where POUT is nominal output power of boost PFC stage, tHOLD is the required hold-up time, and VBOUT,MIN is the allowable minimum PFC output voltage during hold-up time. 264VAC Figure 15. Ripple Factor with Different Line Voltages Therefore, with a given current ripple factor (KRF=ΔIL/ILAVG), the boost inductor value is obtained as: LBOOST = 2VBOUT 2 ⋅η 1 ⋅ K RF ⋅ POUT 27 f SW © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 (20) www.fairchildsemi.com 8 AN-6982 APPLICATION NOTE ID EN VREF V BOUT - - + VBOUT , RIPPLE = I BOUT 2π f LINE CBOUT (Design Example) With the ripple specification of 12VPP, the capacitor should be: RFB 2 = 2.5V RFB1 + RFB 2 RFB 2 = (1 − Since minimum allowable output voltage during one cycle line (20ms) drop-outs is 310V, the capacitor should be: 387 2 − 3102 VEA (25) (Design Example) Assuming the second level of PFC output voltage is 347V: I BOUT 0.9 > = = 239 μ F 2π ⋅ f LINE ⋅ VBOUT , RIPPLE 2π ⋅ 50 ⋅12 VOUT 2 − VOUT , MIN 2 1.95/2.45 The voltage divider network for the PFC output voltage sensing should be designed such that FBPFC voltage is 2.5V at nominal PFC output voltage: VBOUT × 2 ⋅ 349 ⋅ 20 × 10−3 - Figure 17. Block of Range Function Figure 16. PFC Output Voltage Ripple = 1.95/2 .45 2.5V RFB2 VBOUT 2 PBOUT ⋅ t HOLD 20 µA FBPFC I BOUT VRMS + RFB1 I D , AVG = I BOUT (1 − cos(4π ⋅ f LINE ⋅ t )) CBOUT > + V DD I D , AVG CBOUT 3.75 SGND = (1 − = 260 μ F VBOUT 2 2.5 )⋅ VBOUT 20 ×10 −6 347 2.5 = 12.9k Ω )⋅ 387 20 × 10−6 13kΩ is selected for RFB2. It is checked if the output voltage is higher than the peak of the line voltage: Thus, 270μF capacitor is selected for the PFC output capacitor. RRMS 1 + RRMS 2 + RRMS 3 π ⋅ ⋅ 2.45 RRMS 3 2 2 × 106 + 200 × 103 + 36 × 103 π ⋅ ⋅ 2.45 36 × 103 2 = 239V < 347V [STEP-5] PFC Output Sensing Circuit = To improve system efficiency at low-line and light-load condition, FAN6982 provides two-level PFC output voltage. As shown in Figure 17, the range function can be enabled or disabled through a resistor connected to ground or VREF. FAN6982 monitors VEA and VRMS voltages to adjust the PFC output voltage and enables a 20µA current source. Then, to obtain 387V for nominal PFC output, The PFC output voltage when 20µA is enabled is given as: =( RFB1 = ( 20 μA × RFB 2 ) (23) 2.5 It is typical to set the second boost output voltage as 340V~300V. It should be checked if the output voltage is higher than the peak of the line voltage VBOUT 2 = VBOUT × (1 - RRMS 1 + RRMS 2 + RRMS 3 π ⋅ ⋅ 2.45 < VBOUT 2 2 RRMS 3 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 VBOUT − 1) ⋅ RFB 2 2.5 387 − 1) ⋅ 13 × 103 = 1999k Ω 2.5 2MΩ is selected for RFB1. (24) www.fairchildsemi.com 9 AN-6982 APPLICATION NOTE [STEP-6] PFC Current-Sensing Circuit Design Figure 18 shows the PFC compensation circuits for the input current shaping and output voltage regulation. The first step in compensation network design is to select the current-sensing resistor of PFC converter considering the maximum power limit. Since line feed-forward is used, the output power is proportional to the voltage control error amplifier voltage as: VEA − 0.6 (26) VEA SAT − 0.6 SAT where VEA is 5.6V and the maximum power limit of PFC given by the maximum VEA voltage is: POUT (VEA ) = POUT MAX ⋅ POUT MAX = VLINE .BO 2 ⋅ G MAX ⋅ RM RIAC RCS (27) where RM is internal modulator resistor whose typical value is 5.7kΩ, RIAC is a resistor connected between IAC pin, and PFC input and GMAX is the maximum of ratio of IAC pin current and modulator output current (IMO/IAC). The typical value of GMAX is 9 when VRMS pin voltage is 1.05V, which is related to the brownout protection threshold of line voltage (VLINE.BO). Figure 18. Gain Modulation Block (Design Example) Setting the maximum power limit of the PFC stage as 450W (around 130% of nominal output power), the current sensing resistor is obtained as: It is typical to set the maximum power limit of the PFC stage around 1.2~1.5 of its nominal output power, such that the VEA is around 4~4.5V at nominal output power. By adjusting the current-sensing resistor for the PFC converter, the maximum power limit of the PFC stage can be programmed. RCS = VLINE . BO 2 ⋅ G MAX ⋅ RM 722 ⋅ 9 ⋅ 5.7 ×103 = = 0.098Ω RIAC PBOUT MAX 6 × 106 ⋅ 450 Thus, 0.1Ω resistor is selected. [STEP-8] PFC Current Loop Design To filter out the current ripple of switching frequency, an RC filter is typically used for the ISENSE pin. RLF should not be larger than 100Ω and the time constant of the filter should be 300~500ns to properly remove the leading-edge current spike caused by reverse recovery of output diode. The transfer function from duty cycle to the inductor current of boost power stage is given as: ) iL V ) = BOUT (28) sL d BOOST Diodes D1 and D2 are required to prevent over-voltage on the ISENSE pin due to the inrush current that might damage FAN6982. A fast recovery diode or ultra-fast recovery diode is recommended. The transfer function from the output of the current control error amplifier to the inductor current-sensing voltage is obtained as: ) vCS RCS ⋅ VBOUT (29) ) = vIEA VRAMP ⋅ sLBOOST where VRAMP is the peak to peak voltage of ramp signal for current control PWM comparator, which is 2.55V. The transfer function of the compensation circuit is given as: s 1+ ) 2π f IC vIEA 2π f II ⋅ ) = s vCS s 1+ 2π f IP © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 (30) www.fairchildsemi.com 10 AN-6982 APPLICATION NOTE where: f II = f IP = GMI 1 , f IZ = and 2π ⋅ CIC1 2π ⋅ RIC ⋅ CIC1 1 (Design Example) Setting the crossover frequency as 6kHz (around 1/10 of switching frequency): ) vCS 1 RCS ⋅ VBOUT = ) vIEA @ f = f VRAMP ⋅ 2π f IC ⋅ LBOOST (31) 2π ⋅ RIC ⋅ CIC 2 IC where GMI is the gain of transconductance error amplifier. = The procedure to design the feedback loop is as follows: (a) Determine the crossover frequency (fIC) around 1/10~1/6 of the switching frequency. Then calculate the gain of the transfer function of Equation (29) at crossover frequency as: ) vCS ) vIEA = @ f = f IC RCS ⋅ VBOUT VRAMP ⋅ 2π f IC ⋅ LBOOST RIC = 1 ) vCS GMI ⋅ ) vIEA @ f = f IC 1 = 0.10nF 2π ⋅ 60 × 103 ⋅ 26 × 103 [STEP-9] PFC Voltage Loop Design Since FAN6982 employs line feed-forward, the powerstage transfer function becomes independent of the line voltage. Then the low-frequency, small-signal, control-tooutput transfer function is obtained as: vˆBOUT I BOUT ⋅ K MAX 1 ≅ ⋅ 5 vˆEA sCBOUT (34) (36) where K MAX = POUT MAX / POUT and 5V is the control window of error amplifier (5.6V-0.6V=5V). (d) Place compensator high-frequency pole (fCP) at least a decade higher than fIC to ensure that it does not interfere with the phase margin of the current loop at its crossover frequency. Proportional and integration (PI) control with highfrequency pole is typically used for compensation. The compensation zero (fVZ) introduces phase boost, while the high-frequency compensation pole (fVP) attenuates the switching ripple, as shown in Figure 20. (35) Figure 20. Voltage Loop Compensation Figure 19. Current Loop Compensation © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 2π ⋅ f IP ⋅ RIC = RIC=27kΩ, CIC1=3.3nF, and CIC2=100pF. @ f = f IC 1 2π ⋅ f IP ⋅ RIC 1 The actual components are a little changed for the offthe-shelf components as: (33) 1 = RIC ⋅ 2π fC / 3 CIC 2 = 1 = 26k Ω 88 × 10−6 ⋅ 0.44 1 1 = = 3.1nF RIC ⋅ 2π f C / 3 26 × 103 ⋅ 2π ⋅ 6 × 103 / 3 CIC 2 = (c) Since the control-to-output transfer function of power stage has -20dB/dec slope and -90o phase at the crossover frequency is 0dB, as shown in Figure 19, it is necessary to place the zero of the compensation network (fIZ) around 1/3 of the crossover frequency so that more than 45° phase margin is obtained. Then the capacitor CIC1 is determined as: C IC1 = Setting the pole of the compensator at 60kHz, (b) Calculate RIC that makes the closed-loop gain unity at crossover frequency: RIC = 1 ) v GMI ⋅ )CS vIEA C IC1 = (32) 0.1 ⋅ 387 = 0.44 2.55 ⋅ 2π ⋅ 6 ×103 ⋅ 916 × 10 −6 www.fairchildsemi.com 11 AN-6982 APPLICATION NOTE The transfer function of the compensation network is obtained as: s 1+ vˆCOMP 2π fVI 2π fVZ = ⋅ (37) s vˆOUT s 1+ 2π fVP where: fVI = fVP = GMV 2.5 1 ⋅ , fVZ = VBOUT 2π ⋅ CVC1 2π ⋅ RVC ⋅ CVC1 1 2π ⋅ RVC ⋅ CVC 2 (b) Place compensator high-frequency pole (fVP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter so noise can be effectively attenuated. Then, the capacitor CVC2 is determined as: CVC 2 = and (38) 1 2π ⋅ fVP ⋅ RVC (41) (Design Example) Setting the crossover frequency as 22Hz: The procedure to design the feedback loop is as follows: (a) Determine the crossover frequency (fVC) around 1/10~1/5 of the line frequency. Since the control-tooutput transfer function of power stage has -20dB/dec slope and -90o phase at the crossover frequency, as shown in Figure 20 as 0dB; it is necessary to place the zero of the compensation network (fVZ) around the crossover frequency so that 45° phase margin is obtained. Then, the capacitor CVC1 is determined as: CVC1 = = RVC = GMV ⋅ I BOUT ⋅ K MAX 2.5 ⋅ (39) 5 ⋅ C BOUT ⋅ (2π fVC ) 2 VBOUT where GMV is the gain of the transconductance error amplifier for the output voltage regulation. GMV ⋅ I BOUT ⋅ K MAX 2.5 ⋅ 2 5 ⋅ CBOUT ⋅ (2π fVC ) VBOUT 70 × 10−6 ⋅ 0.9 ⋅1.27 2.5 ⋅ = 20nF 5 ⋅ 270 × 10−6 ⋅ (2π ⋅ 22) 2 387 1 1 = = 362k Ω 2π ⋅ fVC ⋅ CVC1 2π ⋅ 22 ⋅ 20 ×10−9 Setting the pole of the compensator at 120Hz: CVC1 = CVC 2 = 1 1 = = 3.7 nF 2π ⋅ fVP ⋅ RVC 2π ⋅120 ⋅ 362 × 103 To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: RVC = 1 2π ⋅ fVC ⋅ CVC1 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 (40) www.fairchildsemi.com 12 AN-6982 APPLICATION NOTE 1. Design Summary Application Output Power Input Voltage Output Voltage / Output Current PFC Power Supply 350W 85~264VAC 387V/0.9A Features Switch-charge technique of gain modulator provides better PF and lower THD Over-Voltage Protection (OVP), Under-Voltage (UVP), Open-Loop (OLP), and maximum current limit Protections Range function improves system efficiency at low AC line voltage and light load condition Ready pin function provides power-on sequence for the downstream converter Figure 21. Final Schematic of Design Example © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 13 AN-6982 APPLICATION NOTE Appendix A MOSFET and Diode Reference Specification PFC MOSFETs Voltage Rating Part Number 500V FQP13N50C, FQPF13N50C, FDPF20N50(T) FDP18N50, FDPF18N50, FDA18N50, FDP20N50(T), 600V FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCP20N60S, FCPF20N60S, FCA20N60S, FCP20N60, FCPF20N60 Boost Diodes 600V FFP08H60S, FFPF10H60S, FFP08S60S, FPF08S60SN, BYC10600 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 www.fairchildsemi.com 14 AN-6982 APPLICATION NOTE References FAN6982 — CCM Power Factor Correction Controller AN-8027 — FAN480X PFC+PWM Combo Controller Application AN-6004 — 500W Power Factor Corrected (PFC) Design with FAN4810 AN-6032 — FAN4800 Combo Controller Applications AN-42009 — ML4824 Combo Controller Applications ATX 350W Evaluation Board of FAN6982+FSBH0F70A DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 2. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 6/8/10 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 15