FAIRCHILD AN-9730

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AN-9730
LED Application Design Guide Using Half-Bridge LLC
Resonant Converter for 160W Street Lighting
Introduction
This application note describes the LED driving system
using a half-bridge LLC resonant converter for high
power LED lighting applications, such as outdoor or
street lighting. Due to the existence of the non-isolation
DC-DC converter to control the LED current and the light
intensity, the conventional PWM DC-DC converter has
the problem of low-power conversion efficiency. The
half-bridge LLC converter can perform the LED current
control and the efficiency can be significantly improved.
Moreover, the cost and the volume of the whole LED
driving system can be reduced.
Consideration of LED Drive
Among various kinds of resonant converters, the simplest
and most popular is the LC series resonant converter, where
the rectifier-load network is placed in series with the L-C
resonant network, as depicted in Figure 1[2-4]. In this
configuration, the resonant network and the load act as a
voltage divider. By changing the frequency of driving
voltage Vd, the impedance of the resonant network changes.
The input voltage is split between this impedance and the
reflected load. Since it is a voltage divider, the DC gain of a
LC series resonant converter is always <1. At light-load
condition, the impedance of the load is large compared to
the impedance of the resonant network; all the input voltage
is imposed on the load. This makes it difficult to regulate
the output at light load. Theoretically, frequency should be
infinite to regulate the output at no load.
LED lighting is rapidly replacing conventional lighting
sources like incandescent bulbs, fluorescent tubes, and
halogens because LED lighting reduces energy
consumption. LED lighting has greater longevity,
contains no toxic materials, and emits no harmful UV
rays, which are 5 ~ 20 times longer than fluorescent tubes
and incandescent bulbs. All metal halide and fluorescent
lamps, including CFLs, n contain mercury.
The amount of current through an LED determines the
light it emits. The LED characteristics determine the
forward voltage necessary to achieve the required level of
current. Due to the variation in LED voltage versus
current characteristics, controlling only the voltage across
the LED leads to variability in light output. Therefore,
most LED drivers use current regulation to support
brightness control. Brightness can be controlled directly
by changing the LED current.
Consideration of LLC Resonant
Converter
The attempt to obtain ever-increasing power density of
switched-mode power supplies has been limited by the
size of passive components. Operation at higher
frequencies considerably reduces the size of passive
components, such as transformers and filters; however,
switching losses have been an obstacle to high-frequency
operation. To reduce switching losses and allow highfrequency operation, resonant switching techniques have
been developed. These techniques process power in a
sinusoidal manner and the switching devices are softly
commutated. Therefore, the switching losses and noise
can be dramatically reduced[1-7].
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
Figure 1. Half-Bridge, LC Series Resonant Converter
To overcome the limitation of series resonant converters,
the LLC resonant converter has been proposed[8-12]. The
LLC resonant converter is a modified LC series resonant
converter implemented by placing a shunt inductor across
the transformer primary winding, as depicted in Figure 2.
When this topology was first presented, it did not receive
much attention due to the counterintuitive concept that
increasing the circulating current in the primary side with
a shunt inductor can be beneficial to circuit operation.
However, it can be very effective in improving efficiency
for high-input voltage applications where the switching
loss is more dominant than the conduction loss.
In most practical designs, this shunt inductor is realized
using the magnetizing inductance of the transformer. The
circuit diagram of LLC resonant converter looks much the
same as the LC series resonant converter: the only
difference is the value of the magnetizing inductor. While
the series resonant converter has a magnetizing
inductance larger than the LC series resonant inductor
(Lr), the magnetizing inductance in an LLC resonant
converter is just 3~8 times Lr, which is usually
implemented by introducing an air gap in the transformer.
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AN-9730
Figure 2. Half-Bridge LLC Resonant Converter
APPLICATION NOTE

An LLC resonant converter has many advantages over a
series resonant converter. It can regulate the output over
wide line and load variations with a relatively small
variation of switching frequency. It can achieve zero
voltage switching (ZVS) over the entire operating range.
All essential parasitic elements, including junction
capacitances of all semiconductor devices and the leakage
inductance and magnetizing inductance of the
transformer, are utilized to achieve soft switching.
network even though a square-wave voltage is
applied to the resonant network. The current (Ip) lags
the voltage applied to the resonant network (that is,
the fundamental component of the square-wave
voltage (Vd) applied to the half-bridge totem pole),
which allows the MOSFETs to be turned on with
zero voltage. As shown in Figure 4, the MOSFET
turns on while the voltage across the MOSFET is
zero by flowing current through the anti-parallel
diode.
The rectifier network produces DC voltage by
rectifying the AC current with rectifier diodes and a
capacitor. The rectifier network can be implemented
as a full-wave bridge or center-tapped configuration
with capacitive output filter.
Square-Wave Generator
Q1
IDS1
This application note presents design considerations of an
LLC resonant half-bridge converter employing
Fairchild’s FLS-XS series. It includes explanation of the
LLC resonant converter operation principles, designing
the transformer and resonant network, and selecting the
components. The step-by-step design procedure,
explained with a design example, helps design the LLC
resonant converter.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
Vd
Im
-
Cr
n:1
Rectifier
Network
ID
Io
Ro
+
VO
Lm
-
Figure 3. Schematic of Half-Bridge LLC
Resonant Converter
Ip
Im
IDS1
ID
VIN
Vd
Vgs1
In general, the LLC resonant topology consists of three
stages shown in Figure 3; square-wave generator,
resonant network, and rectifier network.

+
Q2
Figure 3 shows a simplified schematic of a half-bridge
LLC resonant converter, where Lm is the magnetizing
inductance that acts as a shunt inductor, Lr is the series
resonant inductor, and Cr is the resonant capacitor.
Figure 4 illustrates the typical waveforms of the LLC
resonant converter. It is assumed that the operation
frequency is same as the resonance frequency, determined
by the resonance between Lr and Cr. Since the
magnetizing inductor is relatively small, a considerable
amount of magnetizing current (Im) exists, which
freewheels in the primary side without being involved in
the power transfer. The primary-side current (Ip) is sum of
the magnetizing current and the secondary-side current
referred to the primary.
The square-wave generator produces a square-wave
voltage, Vd, by driving switches Q1 and Q2 alternately
with 50% duty cycle for each switch. A small dead
time is usually introduced between the consecutive
transitions. The square-wave generator stage can be
built as a full-bridge or half-bridge type.
The resonant network consists of a capacitor, leakage
inductances, and the magnetizing inductance of the
transformer. The resonant network filters the higher
harmonic currents. Essentially, only sinusoidal
current is allowed to flow through the resonant
Ip
Lr
VIN
LLC Resonant Converter and
Fundamental Approximation

Resonant
Network
Vgs2
Figure 4. Typical Waveforms of Half-Bridge LLC
Resonant Converter
The filtering action of the resonant network allows use of
the fundamental approximation to obtain the voltage gain
of the resonant converter, which assumes that only the
fundamental component of the square-wave voltage input
to the resonant network contributes to the power transfer
to the output. Because the rectifier circuit in the
secondary side acts as an impedance transformer, the
equivalent load resistance is different from actual load
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AN-9730
APPLICATION NOTE
resistance. Figure 5 shows how this equivalent load
resistance is derived. The primary-side circuit is replaced
by a sinusoidal current source, Iac, and a square wave of
voltage, VRI, appears at the input to the rectifier. Since the
average of |Iac| is the output current, Io, Iac, is obtained as:
I ac 
  Io
2
sin(t )
Cr
Vd
+
VIN
if sin(t )  0
VRI 
4Vo

Np:Ns
Rac 
n=Np/Ns
(2)
VRI F
8 V
8
 2 o  2 Ro
I ac
 Io 
8n

Rac
Lm
(nVRIF)
4n  Vo
sin(t )
VRO F n  VRI F
2n  Vo
 

M F 
F
4 Vin
Vd
Vd
Vin
sin(t )
 2
(4)
Ro
VRoF
Lr
With the equivalent load resistance obtained in Equation
5, the characteristics of the LLC resonant converter can
be derived. Using the AC equivalent circuit of Figure 6,
the voltage gain, M, is obtained as:
(6)
 2
) ( m  1)
o

2

 2
( 2  1)  j ( 2  1)( m  1)Q
p
o o
(
2
2
Ro
Figure 6. AC Equivalent Circuit for LLC
Resonant Converter
Considering the transformer turns ratio (n=Np/Ns), the
equivalent load resistance shown in the primary side is
obtained as:
Rac 
2
Cr
(3)
Since harmonic components of VRI are not involved in the
power transfer, AC equivalent load resistance can be
calculated by dividing VRIF by Iac as:
Rac 
8n
-
2
VdF
sin(t )
Ro
-
-
The fundamental component of VRI is given as:
F
VRI
Lm
(1)
VRI  Vo if sin(t )  0
where Vo is the output voltage.
+
VO
+
and VRI is given as:
VRI  Vo
Lr
(5)
where:
By using the equivalent load resistance, the AC
equivalent circuit is obtained, as illustrated in Figure 6,
where VdF and VROF are the fundamental components of
the driving voltage, Vd and reflected output voltage,
VRO (nVRI), respectively.
I ac
Lp  Lm  Lr , Rac 
Q
Lr 1
, o 
Cr Rac
8n 2
2
Ro , m 
Lp
Lr
1
, p 
Lr Cr
1
L p Cr
As can be seen in Equation (6), there are two resonant
frequencies. One is determined by Lr and Cr, while the
other is determined by Lp and Cr.
pk
Equation (6) shows the gain is unity at resonant frequency
(ωo), regardless of the load variation, which is given as:
M
I ac 
  Io
VRI F 
2
sin( wt )
4Vo

sin( wt )
Figure 5. Derivation of Equivalent Load Resistance Rac
2
2n  Vo (m  1)   p

 1 at   o
o 2   p 2
Vin
(7)
The gain of Equation (6) is plotted in Figure 7 for
different Q values with m=3, fo=100kHz, and fp=57kHz.
As observed in Figure 7, the LLC resonant converter
shows gain characteristics that are almost independent of
the load when the switching frequency is around the
resonant frequency, fo. This is a distinct advantage of
LLC-type resonant converter over the conventional series
resonant converter. Therefore, it is natural to operate the
converter around the resonant frequency to minimize the
switching frequency variation.
The operating range of the LLC resonant converter is
limited by the peak gain (attainable maximum gain),
which is indicated with ‘Q’ in Figure 7. Note that the
peak voltage gain does not occur at fo or fp. The peak gain
frequency where the peak gain is obtained exists between
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
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3
AN-9730
APPLICATION NOTE
fp and fo, as shown in Figure 7. As Q decreases (as load
decreases), the peak gain frequency moves to fp and
higher peak gain is obtained. Meanwhile, as Q increases
(as load increases), the peak gain frequency moves to fo
and the peak gain drops; the full load condition should be
worst case for the resonant network design.
fp 
1
2 L p Cr
fo 
In Figure 8, the effective series inductor (Lp) and shunt
inductor (Lp-Lr) are obtained by assuming n2Llks=Llkp and
referring the secondary-side leakage inductance to the
primary side as:
Lp  Lm  Llkp
Lr  Llkp  Lm //(n 2 Llks )  Llkp  Lm // Llkp
1
2 Lr Cr
Q
When handling an actual transformer, equivalent circuit
with Lp and Lr is preferred since these values can be
measured with a given transformer. In an actual
transformer, Lp and Lr can be measured in the primary
side with the secondary-side winding open circuited and
short circuited, respectively.
Lr / Cr
Rac
In Figure 9, notice that a virtual gain MV is introduced,
which is caused by the secondary-side leakage
inductance. By adjusting the gain equation of Equation
(6) using the modified equivalent circuit of Figure 9, the
gain equation for integrated transformer is obtained by:
M @ fo  1
2n  VO
M 

Vin
Figure 7. Typical Gain Curves of LLC Resonant
Converter (m=3)
For practical design, it is common to implement the
magnetic components (series inductor and shunt inductor)
using an integrated transformer; where the leakage
inductance is used as a series inductor, while the
magnetizing inductor is used as a shunt inductor. When
building the magnetizing components in this way, the
equivalent circuit in Figure 6 should be modified as
shown in Figure 8 because leakage inductance exists, not
only in the primary side, but also in the secondary side.
Not considering the leakage inductance in the transformer
secondary side generally results in an ineffective design.
2
) m(m  1)
o 2

2

2
( 2  1)  j ( )  ( 2  1)  (m  1)  Q e
p
o o
1: M V
(M V 
Lp
Lp  Lr
where:
(9)
Rac e 
L
8n Ro
, m p
 2 MV 2
Lr
Qe 
Lr 1
, o 
Cr Rac e
2
1
, p 
Lr Cr
1
L p Cr
The gain at the resonant frequency (ωo) is fixed
regardless of the load variation, which is given as:
M  MV 
Lp
Lp  Lr

m
m 1
at   o
(10)
The gain at the resonant frequency (ωo) is unity when
using individual core for series inductor, as shown in
Equation 7. However, when implementing the magnetic
components with integrated transformer, the gain at the
resonant frequency (ωo) is larger than unity due to the
virtual gain caused by the leakage inductance in the
transformer secondary side.
Lr  Llkp  Lm //( n 2 Llks )
 Llkp  Lm // Llkp
 2
)  (m  1)  M V
o
2


2
( 2  1)  j ( )  ( 2  1)  (m  1)Q e
p
o o
(
(
Consideration for Integrated
Transformer
Lp  Llkp  Lm
(8)
)
Rac
The gain of Equation (9) is plotted in Figure 10 for
different Qe values with m=3, fo=100kHz, and fp=57kHz.
As observed in Figure 9, the LLC resonant converter shows
gain characteristics almost independent of the load when
the switching frequency is around the resonant frequency,
fo.
Figure 8. Modified Equivalent Circuit to
Accommodate the Secondary-Side Leakage
Inductance
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
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4
AN-9730
APPLICATION NOTE
fp 
1
2 L p Cr
fo 
1
2 Lr Cr
Gain (M)
Qe 
B
A
Lr / Cr
Rac e
Load Increase
I
II
Above
Resonance
(fs>fo )
Below
Resonance
(fs<fo)
M @ fo  M V
fo
fs
Figure 10. Operation Modes According to the
Operation Frequency
Figure 9. Typical Gain Curves of LLC Resonant
Converter (m=3) Using an Integrated Transformer
1
2 fo
Ip
Im
Consideration of Operation Mode
and Attainable Maximum Gain
(I) fs < fo
1
2 fS
IDS1
Operation Mode
The LLC resonant converter can operate at frequency
below or above the resonance frequency (fo), as illustrated
in Figure 10. Figure 11 shows the waveforms of the
currents in the transformer primary side and secondary
side for each operation mode. Operation below the
resonant frequency (case I) allows the soft commutation
of the rectifier diodes in the secondary side, while the
circulating current is relatively large. The circulating
current increases more as the operation frequency moves
downward from the resonant frequency. Meanwhile,
operation above the resonant frequency (case II) allows
the circulating current to be minimized, but the rectifier
diodes are not softly commutated. Below-resonance
operation is preferred for high output voltage
applications, such as street LED lighting systems where
the reverse-recovery loss in the rectifier diode is severe.
Below-resonance operation has a narrow frequency range
with respect to the load variation since the frequency is
limited below the resonance frequency even at no-load
condition.
On the other hand, above-resonance operation has less
conduction loss than the below-resonance operation. It
can show better efficiency for low output voltage
applications, such as Liquid Crystal Display (LCD) TV or
laptop adaptor, where Schottky diodes are available for
the secondary-side rectifiers and reverse-recovery
problems are insignificant. However, operation above the
resonant frequency may cause too much frequency
increase at light-load condition. Above-frequency
operation requires frequency skipping to prevent too
much increase of the switching frequency.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
IO
ID
Ip
(II) fs > fo
Im
IDS1
ID
IO
Figure 11. Waveforms of Each Operation Mode
Required Maximum Gain and Peak Gain
Above the peak gain frequency, the input impedance of
the resonant network is inductive and the input current of
the resonant network (Ip) lags the voltage applied to the
resonant network (Vd). This permits the MOSFETs to turn
on with zero voltage (ZVS), as illustrated in Figure 12.
Meanwhile, the input impedance of the resonant network
becomes capacitive and Ip leads Vd below the peak gain
frequency. When operating in capacitive region, the
MOSFET body diode is reverse recovered during the
switching transition, which results in severe noise.
Another problem of entering the capacitive region is that
the output voltage becomes out of control since the slope
of the gain is reversed. The minimum switching
frequency should be limited above the peak gain
frequency.
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AN-9730
APPLICATION NOTE
Even though the peak gain at a given condition can be
obtained using the gain in Equation (6), it is difficult to
express the peak gain in explicit form. To simplify the
analysis and design, the peak gains are obtained using
simulation tools and depicted in Figure 14, which shows
how the peak gain (attainable maximum gain) varies with
Q for different m values. It appears that higher peak gain
can be obtained by reducing m or Q values. With a given
resonant frequency (fo) and Q value, decreasing m means
reducing the magnetizing inductance, which results in
increased circulating current. There is a trade-off between
the available gain range and conduction loss.
M
Capacitive
Region
Peak Gain
Inductive
Region
fs
Vd
Vd
Ip
Ip
2.2
2.1
IDS1
IDS1
2
1.9
Reverse Recovery
ZVS
1.8
Figure 12. Operation Waveforms for Capacitive
and Inductive Regions
The available input voltage range of the LLC resonant
converter is determined by the peak voltage gain. Thus,
the resonant network should be designed so that the gain
curve has an enough peak gain to cover the input voltage
range. However, ZVS condition is lost below the peak
gain point, as depicted in Figure 12. Therefore, some
margin is required when determining the maximum gain
to guarantee stable ZVS operation during the load
transient and startup. Typically 10~20% of the maximum
gain is used as a margin, as shown in Figure 13.
Peak Gain
1.7
1.5
m=2.25
1.4
m=2.5
1.3
m=3.0
1.2
m=6.0
m=9.0 m=8.0 m=7.0
1.1
Gain (M)
m=3.5
m=4.0
m=4.5
m=5.0
1
0.2
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
Figure 14. Peak Gain (Attainable Maximum Gain)
vs. Q for Different m Values
Maximum Operation
Gain
(Mmax)
fo
0.3
Q
Peak Gain
10~20% of Mmax
1.6
fs
Figure 13. Determining the Maximum Gain
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
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6
AN-9730
APPLICATION NOTE
Features of FLS-XS Series
Table 1. Pin Description
FLS-XS series is an integrated Pulse Frequency
Modulation (PFM) controller and MOSFETs specifically
designed for Zero Voltage Switching (ZVS) half-bridge
converters with minimal external components. The
internal controller includes an under-voltage lockout,
optimized high-side / low-side gate driver, temperaturecompensated precise current controlled oscillator, and
self-protection circuitry. Compared with discrete
MOSFET and PWM controller solutions, FLS-XS series
can reduce total cost, component count, size, and weight;
while simultaneously increasing efficiency, productivity,
and system reliability.
Pin#
Description
VDL
This pin is the drain of the high-side
MOSFET, typically connected to the
input DC link voltage.
AR
This pin is for discharging the external
soft-start capacitor when any
protections are triggered. When the
voltage of this pin drops to 0.2V, all
protections are reset and the controller
starts to operate again.
RT
This pin is to program the switching
frequency. Typically, opto-coupler and
resistor are connected to this pin to
regulate the output voltage.
4
CS
This pin is to sense the current flowing
through the low-side MOSFET.
Typically negative voltage is applied
on this pin.
5
SG
This pin is the control ground.
6
PG
This pin is the power ground. This pin
is connected to the source of the lowside MOSFET.
7
LVCC
8
NC
9
HVCC
This pin is the supply voltage of the
high-side drive circuit.
10
VCTR
This pin is the drain of the low-side
MOSFET. Typically transformer is
connected to this pin.
1
2
3
Figure 15. Package Diagram
VREF
Name
This pin is the supply voltage of the
control IC.
No connection.
LVCC
VDL
7
1
VREF
IRT
IRT
2IRT
LVCC Good
3V
S
1V
R
Q
VREF
9
HVCC
10
VCTR
6
PG
5
SG
Internal
Bias
LUV+ / LUV-
HUV+ / HUV-
2V
RT
Time
Delay
350ns
3
Level
Shifter
High-Side
Gate Driver
Divider
AR
2
Time
Delay
350ns
VCssH / VCssL
5k
S
R
LVCC good
Q
Balancing
Delay
Low-Side
Gate Driver
Shutdown
TSD
VAOCP
LVCC
Delay
50ns
VOVP
VOCP
Delay
1.5 s
-1
4
CS
Figure 16. Functional Block Diagram of FSFR-Series
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
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7
APPLICATION NOTE
FLS-XS
Series
AN-9730
Figure 17. Reference Circuit for Design Example of LLC Resonant Half-Bridge Converter
Design Procedure
In this section, a design procedure is presented using the
schematic in Figure 17 as a reference. An integrated
transformer with center tap, secondary side is used and
input is supplied from Power Factor Correction (PFC) preregulator. A DC-DC converter with 160W/115V output
has been selected as a design example. The design
specifications are as follows:
Even though the input voltage is regulated as constant by
PFC pre-regulator, it drops during the hold-up time. The
minimum input voltage considering the hold-up time
requirement is given as:
Vin min  VO. PFC 2 
 Nominal input voltage: 400VDC (output of PFC
stage)
 Output: 115V/1.4A (160W)
 Hold-up time requirement: 30ms (50Hz line freq.)
 DC link capacitor of PFC output: 240µF
(Design Example) Assuming the efficiency is 92%,
P
161
Pin  o 
 175W
E ff
0.92
Vin max  VO.PFC  400V
Estimated Efficiency (Eff): The power conversion
efficiency must be estimated to calculate the maximum
input power with a given maximum output power. If no
reference data is available, use Eff = 0.88~0.92 for lowvoltage output applications and Eff = 0.92~0.96 for highvoltage output applications. With the estimated efficiency,
the maximum input power is given as:
Po
E ff
Vin
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
min
 VO. PFC 
 400 2 
2
2 PinTHU
C DL
2  175  30  10 3
240  10 6
 341V
[STEP-2] Determine Maximum and Minimum
Voltage Gains of the Resonant Network
(11)
As discussed in the previous section, it is typical to operate
the LLC resonant converter around the resonant frequency
(fo) to minimize switching frequency variation. Since the
input of the LLC resonant converter is supplied from PFC
output voltage, the converter should be designed to operate
at fo for the nominal PFC output voltage.
Input Voltage Range (Vinmin and Vinmax): The maximum
input voltage would be the nominal PFC output voltage as:
Vin max  VO.PFC
(13)
where VO.PFC is the nominal PFC output voltage, THU is
a hold-up time, and CDL is the DC link bulk capacitor.
[STEP-1] Define System Specifications
Pin 
2 PinTHU
CDL
(12)
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AN-9730
APPLICATION NOTE
As observed in Equation (10), the gain at fo is a function of
m (m=Lp/Lr). The gain at fo is determined by choosing that
value of m. While a higher peak gain can be obtained with
a small m value, too small m value results in poor coupling
of the transformer and deteriorates the efficiency. It is
typical to set m to be 3~7, which results in a voltage gain
of 1.1~1.2 at the resonant frequency (fo).
[STEP-4] Calculate Equivalent Load
Resistance
With the transformer turns ratio obtained from Equation
(16), the equivalent load resistance is obtained as:
Rac 
With the chosen m value, the voltage gain for the nominal
PFC output voltage is obtained as:
m @f=f
o
m 1
M min 
Rac 
(14)
Vin max min
M
Vin min
With m value chosen in STEP-2, read proper Q value from
the peak gain curves in Figure 14 that allows enough peak
gain. Considering the load transient and stable zerovoltage-switching (ZVS) operation, 10~20% margin
should be introduced on the maximum gain when
determining the peak gain. Once the Q value is
determined, the resonant parameters are obtained as:
(15)
1
2 Q  f o  Rac
1
Lr 
(2 f o ) 2 Cr
Cr 
(Design Example) The ratio (m) between Lp and Lr is
chosen as 5. The minimum and maximum gains are
obtained as:
V RO
M
max
Vin max

Vin
m

m 1

Vin min
5
 1.12
5 1
m
min
400

1.12  1.31
341
Gain (M)
1.31
M 
(20)
As calculated in STEP-2, the maximum voltage gain
(M max) for the minimum input voltage (Vinmin) is 1.31. With
15% margin, a peak gain of 1.51 is required. m has been
chosen as 5 in STEP-2 and Q is obtained as 0.38 from the
peak gain curves in Figure 19. By selecting the resonant
frequency as 100kHz, the resonant components are
determined as:
for VINmin
1.12
Mmin
(19)
(Design Example)
Peak Gain
(Available Maximum Gain)
Mmax
(18)
Lp  m  Lr
2
max
8n 2 (Vo  V F ) 2 8  1.93 2  115.9 2

 252
Po
2
 2  161
[STEP-5] Design the Resonant Network
The maximum voltage gain is given as:
M min 
(17)
(Design Example)
which would be the minimum gain because the nominal
PFC output voltage is the maximum input voltage (Vinmax).
M max 
8n 2 Vo 2
 2 Po
for
VINmax
( VO.PFC )
1
1

 16.64nF
2Q  f o  Rac 2  0.38  100  10 3  252
1
1
Lr 

 152uH
2
3 2
(2f o ) C r (2  100  10 )  16.64  10 9
L p  m  Lr  760uH
Cr 
m
 1.12
m 1
fo
fs
Figure 18. Maximum Gain / Minimum Gain
[STEP-3] Determine the Transformer Turns
Ratio (n=Np/Ns)
With the minimum gain (Mmin) obtained in STEP-2, the
transformer turns ratio is given as:
n
Np
Ns

Vin max
 M min
2(Vo  VF )
(16)
where VF is the secondary-side rectifier diode voltage drop.
(Design Example) assuming VF is 0.9V,
Np
Vin max
400
n

 M min 
1.12  1.93
Ns
2(VO  V F )
2(115  0.9)
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
Figure 19. Resonant Network Design Using the Peak Gain
(Attainable Maximum Gain)
Curve for m=5
www.fairchildsemi.com
9
AN-9730
APPLICATION NOTE
[STEP-6] Design the Transformer
The worst case for the transformer design is the minimum
switching frequency condition, which occurs at the
minimum input voltage and full-load condition. To obtain
the minimum switching frequency, plot the gain curve
using gain Equation 9 and read the minimum switching
frequency. The minimum number of turns for the
transformer primary-side is obtained as:
N p min 
n(Vo  VF )
2 f s  M V  B  Ae
(21)
min
where Ae is the cross-sectional area of the transformer
core in m2 and B is the maximum flux density swing in
Tesla, as shown in Figure 20. If there is no reference
data, use B =0.3~0.4 T.
n (Vo+VF)/MV
VRI 1/(2fs)
Figure 21. Gain Curve
[STEP-7] Transformer Construction
-n (Vo+VF)/MV
B
B
Figure 20. Flux Density Swing
Choose the proper number of turns for the secondary side
that results in primary-side turns larger than Npmin as:
N p  n  N s  N p min
Parameters Lp and Lr of the transformer were determined in
STEP-5. Lp and Lr can be measured in the primary side
with the secondary-side winding open circuited and short
circuited, respectively. Since LLC converter design
requires a relatively large Lr, a sectional bobbin is
typically used, as shown in Figure 22, to obtain the desired
Lr value. For a sectional bobbin, the number of turns and
winding configuration are the major factors determining
the value of Lr, while the gap length of the core does not
affect Lr much. Lp can be controlled by adjusting the gap
length. Table 2 shows measured Lp and Lr values with
different gap lengths. A gap length of 0.05mm obtains
values for Lp and Lr closest to the designed parameters.
(22)
Np
N s2
N s1
2
(Design Example) EER3542 core (Ae=107mm ) is
selected for the transformer. From the gain curve of
Figure 21, the minimum switching frequency is obtained
as 82KHz. The minimum primary-side turns of the
transformer is given as:
n(Vo  V F )
N p min 
min
2 f s B  1.11  Ae

1.93  115.9
2  82  10  0.4  1.11  107  10
3
6
Figure 22. Sectional Bobbin
 29 turns
Choose Ns so that the resultant Np is larger than Npmin:
Table 2. Measured Lp and Lr with Different Gap Lengths
N p  n  N s  1.93  14  27  N p min
Gap Length
Lp
Lr
N p  n  N s  1.93  15  29  N p
min
0.0mm
2,295μH
123μH
N p  n  N s  1.93  16  31  N p
min
0.05mm
943μH
122μH
0.10mm
630μH
118μH
N p  n  N s  1.93  17  33  N p min
0.15mm
488μH
117μH
N p  n  N s  1.93  18  35  N p min
0.20mm
419μH
115μH
min
0.25mm
366μH
114μH
N p  n  N s  1.93  19  37  N p
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
www.fairchildsemi.com
10
AN-9730
APPLICATION NOTE
The nominal voltage of the resonant capacitor in normal
operation is given as:
(Design Example)
Final Resonant Network Design
Even though the integrated transformer approach in LLC
resonant converter design can implement the magnetic
components in a single core and save one magnetic
component, the value of Lr is not easy to control in real
transformer design. Resonant network design sometimes
requires iteration with a resultant Lr value after the
transformer is built. The resonant capacitor value is also
changed since it should be selected among off-the-shelf
capacitors. The final resonant network design is
summarized in Table 3 and the new gain curves are shown
in Figure 23.
Table 3. Final Resonant Network Design Parameters
VCr nom 
Vin max
2  I Cr RMS

2
2    f o  Cr
(24)
However, the resonant capacitor voltage increases higher
than this at overload condition or load transient. Actual
capacitor selection should be based on the Over-Current
Protection (OCP) trip point. With the OCP level, IOCP,
the maximum resonant capacitor voltage is obtained as:
VCr nom 
Vin max
I OCP

2
2    f o  Cr
(25)
(Design Example)
Parameters
Initial Design
Final Design
Lp
Lr
Cr
fo
m
760µH
152H
16.64nF
100kHz
5
625µH
125µH
22nF
96kHz
5
Q
M@fo
Minimum
Frequency
0.38
1.12
0.3
1.12
75kHz
74.4kHz
I Cr RMS 

1
E ff
[
I O
2 2n
]2  [
n(Vo  VF )
4 2 f o M v ( L p  Lr )
]2
1.93(115  0.9)
  1.4 2
1
]2
[
] [
0.92 2 2  1.93
4 2  96  10 3  1.12  500  10  6
=1.18A
The peak current in the primary side in normal operation is:
I Cr peak  2  I Cr rms  1.67 A
OCP level is set to 2.5A with 50% margin on ICrpeak:
2.0
100% load
VCr nom 
80% load
60% load
1.8
40% load
20% load

1.6
f min
f normal
400
2  1.18
 326V

2
2    96  10 3  22  10 9
VCr max 
Gain
1.4
M max
1.2
M

min
1.0
RMS
2  I Cr
Vin max

2
2    f o  Cr
Vin max
I OCP

2
2    f o  Cr
400
2.5

 388.5V
2
2    96  10 3  22  10 9
A 630V rated low-ESR film capacitor is selected for the
resonant capacitor.
0.8
[STEP-9] Rectifier Network Design
0.6
40
60
50
70
80
90
100
110
120
130
When the center tap winding is used in the transformer
secondary side, the diode voltage stress is twice of the
output voltage expressed as:
140
Frequency (KHz)
Figure 23. Gain Curve of the Final Resonant
Network Design
VD  2(Vo  VF )
[STEP-8] Select the Resonant Capacitor
When choosing the resonant capacitor, the current rating
should be considered because a considerable amount of
current flows through the capacitor. The RMS current
through the resonant capacitor is given as:
I Cr RMS 
1
E ff
[
 Io
2 2n
]2  [
n(Vo  VF )
]2
4 2 f o M V ( Lp  Lr )
(23)
I D RMS 

4
Io
(27)
Meanwhile, the ripple current flowing through output
capacitor is given as:
I Co RMS  (
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
(26)
The RMS value of the current flowing through each
rectifier diode is given as:
 Io
2 2
)2  I o 2 
2 8
8
Io
(28)
www.fairchildsemi.com
11
AN-9730
APPLICATION NOTE
The voltage ripple of the output capacitor is:
Vo 

2
I o  RC
(29)
where RC is the effective series resistance (ESR) of the
output capacitor and the power dissipation is the output
capacitor is:
PLoss.Co  ( I Co RMS )2  RC
(30)
(Design Example) The voltage stress and current stress of
the rectifier diode are:
V D  2(Vo  V F )  2(115  0.9)  231.8V
I D RMS 

4
Figure 24. Typical Circuit Configuration for RT Pin
I o  1.1A
The 600V/8A Ultra fast recovery diode is selected for the
rectifier, considering the voltage overshoot caused by the
stray inductance.
The RMS current of the output capacitor is:
I Co RMS  (
I o
2 2
)2  Io2 
 2 8
8
I o  0.675 A
When two electrolytic capacitors with ESR of 100m are
used in parallel, the output voltage ripple is given as:
Vo 

2
I o  RC 

2
 1.4  (
0.1
)  0.1V
2
The loss in electrolytic capacitors is:
PLoss ,Co  ( I Co RMS ) 2  RC  0.675 2  0.05  0.02W
Soft-Start To prevent excessive inrush current and
overshoot of output voltage during startup, increase the
voltage gain of the resonant converter progressively. Since
the voltage gain of the resonant converter is reversely
proportional to the switching frequency, soft-start is
implemented by sweeping down the switching frequency
from an initial high frequency (f ISS) until the output
voltage is established, as illustrated in Figure 25. The softstart circuit is made by connecting RC series network on
the RT pin as shown in Figure 24. FLS-XS series also has
an internal soft-start for 3ms to reduce the current
overshoot during the initial cycles, which adds 40KHz to
the initial frequency of the external soft-start circuit, as
shown in Figure 25. The actual initial frequency of the
soft-start is given as:
5.2k  5.2k 

)  100  40 (kHz )
(33)
Rmin
RSS
It is typical to set the initial frequency of soft-start (f ISS) as
2~3 times of the resonant frequency (fo).
f ISS  (
[STEP-10] Control Circuit Configuration
Figure 24 shows the typical circuit configuration for the RT
pin of FLS-XS series, where the opto-coupler transistor is
connected to the RT pin to control the switching frequency.
The minimum switching frequency occurs when the optocoupler transistor is fully tuned off, which is given as:
The soft-start time is determined by the RC time constant:
TSS  3 ~ 4 times of RSS  CSS
5.2k 
f min 
 100(kHz )
(31)
Rmin
Assuming the saturation voltage of opto-coupler
transistor is 0.2V, the maximum switching frequency is
determined as:
f max  (
5.2k  4.68k 
)  100(kHz )

Rmin
Rmax
(34)
(32)
Figure 25. Frequency Sweep of the Soft-Start
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
www.fairchildsemi.com
12
AN-9730
APPLICATION NOTE
(Design Example) The minimum frequency is 75kHz in
STEP-6. Rmin is determined as:
Rmin 
100 KHz
 5.2 K  6.93K
f min
Considering the output voltage overshoot during transient
(10%) and the controllability of the feedback loop, the
maximum frequency is set as 140kHz. Rmax is determined as:
Rmax 

4.68K
f o  1.40 5.2 K
(
)

100 KHz
Rmin
4.68 K
 7.88K
96 KHz  1.40 5.2 K
(
)

100 KHz
6.93K
Setting the initial frequency of soft-start as 250kHz
(2.5 times of the resonant frequency), the soft-start resistor
RSS is given as:
RSS 

5.2 K
f ISS  40 KHz 5.2 K
(
)

100 KHz
Rmin
5.2 K
 3.85 K
250 KHz  40 KHz 5.2 K
(
)

100 KHz
6.93K
[STEP-11] Current Sensing and Protection
FLS-XS series senses low-side MOSFET drain current as
a negative voltage, as shown in Figure 26 and Figure 27.
Half-wave sensing allows low-power dissipation in the
sensing resistor, while full-wave sensing has less
switching noise in the sensing signal. Typically, RC lowpass filter is used to filter out the switching noise in the
sensing signal. The RC time constant of the low-pass filter
should be 1/100~1/20 of the switching period.
(Design Example) Since the OCP level is determined as
2.5A in STEP-8 and the OCP threshold voltage is -0.6V, a
sensing resistor of 0.24 is used. The RC time constant is
set to 100ns (1/100 of switching period) with 1kresistor
and 100pF capacitor.
[STEP-12] Voltage and Current Feedback
Power supplies for LED lighting must be controlled by
Constant Current (CC) Mode as well as a Constant
Voltage (CV) Mode. Because the forward-voltage drop of
LED varies with the junction temperature and the current
also increases greatly consequently, devices can be
damaged.
Figure 28 shows an example of a CC and CV Mode
feedback circuit for single output LED power supply.
During normal operation, CC Mode is dominant and CV
control circuit does not activate as long as the feedback
voltage is lower than reference voltage, which means that
CV control circuit only acts as OVP for abnormal modes.
(Design Example) The output voltage (VO) is 115V in
design target. VO is determined as:
Vo  2.5(1 
R FU
)
R FL
Set the upper-side feedback resistance (RFU) as 330K.
RFL is determined as:
R FL 
2.5  R FU 2.5  330 K

 7.33K
(Vo  2.5)
(115  2.5)
The output voltage of op-amp is given as:
Vsense V REF

 sC 201  VOC
0  R 201 R 203
1
1

 sC 201
R 201 R 203
V
V
1
VOC  
( sense  REF )
sC 201 R 201 R 203
Actually, the Vsense has a negative value and assume all
resistors have the same value for simplification;
VOC  
1
(Vsense  V REF )
sC 201  R
The output voltage of the op-amp for CC control keeps
zero voltage as long as the sensing voltages are lower than
the reference voltage.
VAUX
Figure 26. Half-Wave Sensing
VOUT
Rbias
C201 R202
R201
Current
Feedback
VREF=2.5V
VOC
R203
KA431
1N4148
1K
1N4148
C202 R205
R204
RFU
VOV
RFL
Figure 28. Example of CC and CV Feedback Circuit
Figure 27. Full-Wave Sensing
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
www.fairchildsemi.com
13
AN-9730
APPLICATION NOTE
Figure 29 shows another example of a CC and OverVoltage Regulation (OVR) Mode feedback circuit for
multi-output LED power supply. The FAN7346 is a LED
current-balance controller that controls four LED arrays to
maintain equal LED current. To prevent LED driving
voltage being over the withstanding voltage of component,
the FAN7346 controls LED driving voltage. The OVR
control circuit activates when the ENA pin is in HIGH
state. If OVR pin voltage is lower than 1.5V, the Feedback
Control (FB) pin voltage follows headroom control to
maintain minimum voltage of drain voltages as 1V. If
OVR pin voltage is higher than 1.5V, the FAN7346
controls FB (FB is pulled LOW) through FB regulation so
the OVR pin voltage is not over 1.5V.
signal to increase output power. This can cause SLP or
thermal stress problems in the other channel. OLP function
has auto-recovery: As soon as drain voltage is higher than
0.3V, OLP is finished and drain voltage feedback system
is restored.
LED current is controlled by FBx pin voltage. The
external current balance switch is operating in linear
region to control LED current. Sensed voltage at the FBx
pin is compared with internal reference voltage and
controller signals the gate (or base) for external current
balance switch. Internal reference voltage is made from
ADIM voltage. The LED current is determined as:
(Design Example) The output voltage (VO) is 115V in
I LED 
V ADIM
10  RSENSE
design target. VO is determined as:
To sense a short LED condition, the FAN7346 senses
drain voltage level. If LEDs are shorted, the LED forward
voltage is lower than other LED strings, so its drain
voltage of external balance switch is higher than other
drain voltage. The SLP condition detection threshold
voltage can be programmed by SLPR voltage. The internal
short LED protection reference is determined as:
R8
)
R10
Vo  1.5(1 
Set the upper-side feedback resistance (R8) as 1M. R10
is determined as:
R10 
(35)
ADIM voltage is clamped internally from 0.5V to 4V. The
protections; such as open LED Protection (OLP), Short
LED Protection (SLP), and Over-Current Protection
(OCP); which increase system reliability, are applied in
individual string protection method.
VSLP _ TH  10  VSLPR
To sense over-current condition, the FAN7346 monitors
FBx pin voltage. If FBx voltage is higher than 1V for
20µs, CHx is considered in over-current condition. After
sensing OCP condition, individual channel switch is
latched off. So, even if a channel is in OCP condition,
other channels keep operating. Any OCP channel is
restarted after UVLO is reset.
1.5  R8
1.5  1M

 13.2 K
(Vo  1.5) (115  1.5)
The output channel current (ILED) is 350mA in design target.
Setting the VADIM is above 4V, the current sense RSENSE is
determined as:
R SENSE 
V ADIM
4V

 1.14
10  I LED 10  350mA
Choose the sense resistor (R29,R30,R31, and R32) is
1.2  , the OCP level is determined as:
I OCP 
VOCP _ TH
R SENSE

1V
 833mA
1.5
(36)
Minimum SLP threshold voltage is 0V and maximum SLP
threshold voltage is 45V. If any string is in SLP condition,
SLP string is turned off and other string is operated
normally. If the sensed drain voltage (CHx voltage) is
higher than the programmed threshold voltage for 20µs,
CHx goes to short LED protection. As soon as
encountering SLP, the corresponding channel is forced off.
RS32
CS13
RS31
CS11
RS30
CS10
RS29
CS7
RS19
RS20
CS8
RS13 CS9
RS27
CS14
RS28
CS15
CS12
RS24
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
RS21
To sense an open LED condition, the FAN7346 senses
drain voltage level. If LED string is opened, its drain
voltage of external balance switch is grounded, so the
FAN7346 detects the open-LED condition. The detection
threshold voltage is 0.3V. If CHx voltage is lower than
0.3V for 20µs, its drain voltage feedback is pulled up to
5V. This means the opened LED string is eliminated from
drain feedback loop. Without OLP, minimum drain
voltage is 0V, so drain voltage feedback forces the FB
Figure 29. Example of CC and OVR Feedback Circuit
www.fairchildsemi.com
14
AN-9730
APPLICATION NOTE
Design Summary
Figure 30 and Figure 31 show the final schematic of the
LLC resonant half-bridge converter for LED lighting
design example. EER3543 core with sectional bobbin is
used for the transformer. Efficiency at full-load is around
94%.
Figure 30. Final Schematic of Half-Bridge LLC Resonant Converter for Single Channel
ADIM
SLPR
FAN7346
GND
FB4
OUT4
CH4
ENA
FB
FB3
CH3
VMIN
OUT3
FB2
REF
PWM1
PWM2
PWM3
PWM5
PWM4
OUT2
CH2
FB1
OUT1
FLS-XS
Series
RS32
CS13
RS25
RS31
CS11
RS23
RS30
CS10
RS16
RS29
CS7
RS11
CH1
VCC
OVR
RS22
RS18
RS17
RS15
RS14
Figure 31. Final Schematic of Half-Bridge LLC Resonant Converter for Multi Channel
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
www.fairchildsemi.com
15
AN-9730
APPLICATION NOTE
VCR [200V/div]
Experimental Verification
To show the validity of the design procedure presented in
this application note, the converter of the design example
was built and tested. All the circuit components are used as
designed in the design example.
IP [2A/div]
Figure 32 and Figure 33 show the operation waveforms at
full-load and no-load conditions for nominal input voltage.
As observed, the MOSFET drain-to-source voltage (VDS)
drops to zero by resonance before the MOSFET is turned
on and zero voltage switching is achieved.
VDS [200V/div]
Figure 34 shows the waveforms of the resonant capacitor
voltage and primary-side current at full-load condition.
The peak values of the resonant capacitor voltage and
primary-side current are 320V and 1.7A, respectively,
which are well matched with the calculated values in
STEP-8 of design procedure section.
320V
1.7A
Time (5µs/div)
Figure 34. Resonant Capacitor Voltage and PrimarySide Current Waveforms at Full-Load Condition
IP [1A/div]
Figure 35 shows the rectifier diode voltage and current
waveforms at full-load condition. Due to the voltage
overshoot caused by stray inductance, the voltage stress is
a little bit higher than the value calculated in STEP-9.
ID [1A/div]
Figure 36 shows the output load current and output voltage
of op-amp waveforms for constant-current control when
output load is step changed from 240mA to 1400mA at t0.
257V
VD [100V/div]
Figure 37 shows the operation waveform when LED string
is opened and restored condition
Time (5µs/div)
Figure 35. Rectifier Diode Voltage and Current
Waveforms at Full-Load Condition
IP [2A/div]
VOP_CC [2V/div]
IDS [1A/div]
1400mA
VDS [200V/div]
240mA
CC Control Mode
t0
Time (5µs/div)
ILOAD [0.5A/div]
Figure 32. Operation Waveforms at Full-Load Condition
t1
Time (50ms/div)
Figure 36. Constant-Current Control Waveforms
IP [2A/div]
VLED
[100V/div]
Open LED
Restore LED
IDS [1A/div]
VDS_NORMAL_LED
[500mV/div]
VDS [200V/div]
VDSD_OPEN_LED
[500mV/div]
Time (5µs/div)
Figure 37. Open LED Protection Operation
Figure 33. Operation Waveforms at No-Load Condition
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
www.fairchildsemi.com
16
AN-9730
APPLICATION NOTE
References
[1] Robert L. Steigerwald, “A Comparison of Half-bridge
resonant converter topologies,” IEEE Transactions on
Power Electronics, Vol. 3, No. 2, April 1988.
[2] A. F. Witulski and R. W. Erickson, “Design of the series
resonant converter for minimum stress,” IEEE Transactions
on Aerosp. Electron. Syst., Vol. AES-22, pp. 356-363,
July 1986.
[3] R. Oruganti, J. Yang, and F.C. Lee, “Implementation of
Optimal Trajectory Control of Series Resonant Converters,”
Proc. IEEE PESC ’87, 1987.
[4] V. Vorperian and S. Cuk, “A Complete DC Analysis of the
Series Resonant Converter,” Proc. IEEE PESC’82, 1982.
[5] Y. G. Kang, A. K. Upadhyay, D. L. Stephens, “Analysis and
design of a half-bridge parallel resonant converter operating
above resonance,” IEEE Transactions on Industry
Applications, Vol. 27, March-April 1991, pp. 386 – 395.
[6] R. Oruganti, J. Yang, and F.C. Lee, “State Plane Analysis of
Parallel Resonant Converters,” Proc. IEEE PESC ’85, 1985.
[7] M. Emsermann, “An Approximate Steady State and Small
Signal Analysis of the Parallel Resonant Converter Running
Above Resonance,” Proc. Power Electronics and Variable
Speed Drives ’91, 1991, pp. 9-14.
[8] Yan Liang, Wenduo Liu, Bing Lu, van Wyk, J.D, “Design of
integrated passive component for a 1MHz 1kW half-bridge
LLC resonant converter,” IAS 2005, pp. 2223-2228.
[9] B. Yang, F.C. Lee, M. Concannon, “Over-current protection
methods for LLC resonant converter” APEC 2003, pp. 605 - 609.
[10] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhaoming Qian,
Guisong Huang, “Three-level LLC series resonant DC/DC
converter,” IEEE Transactions on Power Electronics
Vol.20, July 2005, pp.781 – 789.
[11] Bo Yang, Lee, F.C, A.J Zhang, Guisong Huang, “LLC
resonant converter for front-end DC/DC conversion,” APEC
2002. pp.1108 – 1112.
[12] Bing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D.
Van Wyk, “Optimal design methodology for LLC Resonant
Converter,” APEC, 2006, pp.533-538.
This application note written based on Fairchild Semiconductor Application Note AN-4137.
Related Datasheets
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© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
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