CS1112 Quad Power Output Driver Features 4.0 MHz Serial Input Bus Parallel Input Control 1.0 Ω DMOS Drivers (typ) Power On Reset Internal Flyback Clamps Status Output Fault Protection – 46 V Peak Transient – Power Limiting – Undervoltage – Overvoltage • Fault Reporting – Open Load – Short Circuit • 8 Internally Fused Leads • • • • • • • Semiconductor Components Industries, LLC, 2000 October, 2000 – Rev. 10 http://onsemi.com SO–24L DW SUFFIX CASE 751E PIN CONNECTIONS AND MARKING DIAGRAM VDD VPWR OUT0 IN0 GND GND GND GND IN1 OUT1 SI CSB 24 1 A WL, L YY, Y WW, W CS1112 AWLYYWW The CS1112 is a Power Output Driver. The IC incorporates four protected DMOS low–side drivers designed to drive inductive and resistive loads in an automotive environment. The outputs are controlled by an 8–bit serial peripheral interface (SPI) or its associated parallel input. Each output contains overcurrent protection, open load detection, and inductive flyback clamps. The device is overvoltage protected. Overcurrent and open load faults are reported over the SPI port, and at the STATUS lead. I/O Control SPI communication is initiated by asserting CSB low. Data at the SI lead is transferred on the rising edge of SCLK. The MSB is transferred first. The outputs become active at the rising edge of CSB. Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK. The SO lead is high impedance while CSB is high. An open drain output, (STATUS) reports a fault (short to VPWR, GND, or open load) has occurred at one or more of the outputs. Protection Each output independently detects shorts to VPWR while the output is “on” and open load/short to ground while the output is “off”. The fault register will be set if a fault occurs at the output. The fault register will be reset if the fault condition is removed from the output. The fault data is latched when CSB is asserted low. If an overcurrent condition or short circuit to VBATT occurs, the output goes into a low duty cycle mode for the duration of the fault. The outputs are disabled during an overvoltage or undervoltage condition. ROSC STATUS OUT3 IN3 GND GND GND GND IN2 OUT2 SO SCLK = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device 1 Package Shipping CS1112YDWF24 SO–24L 31 Units/Rail CS1112YDWFR24 SO–24L 1000 Tape & Reel Publication Order Number: CS1112/D CS1112 APPLICATION DIAGRAM IN1 IN2 IN3 IN4 VDD VPWR QPOD CSB SI Micro Controller with Bus SCLK 4 CMOS Serial Shift Registers and Latches DMOS Low Side Switches and Protection Circuitry SO VDD 4 10 kΩ Fault Reporting 4 ROSC Status Bias ROSC 82 kΩ GND ABSOLUTE MAXIMUM RATINGS* Rating Value Unit –0.3 to 30 V 46 V –0.3 to +7.0 V 46 V –0.3 to VDD + 0.3 V 50 mJ Operating Junction Temperature, TJ –40 to 150 °C ESD Capability (Human Body Model) 1.5 kV 230 peak °C DC Supply (VPWR) Output DC Voltage (Out 0, 1, 2, 3) VDD Supply Voltage Peak Transient (1.0 ms rise time, 300 ms period, 32 V Load Dump @ 14 V VPWR) Digital Input Voltage Single Pulse Avalanche Energy (I = 450 mA)(Out 0, 1, 2, 3) Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1.) 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. http://onsemi.com 2 CS1112 ELECTRICAL CHARACTERISTICS (9.0 V < VPWR < 17 V, 4.5 V < VDD < 5.5 V, –40°C < TJ < 125°C, 5.5 V < VPWR < 25 V, (Outputs Functional); unless otherwise specified.) Test Conditions Min Typ Max Unit Outputs Latched Off By Event 2.5 3.0 3.5 V – 200 – mV Characteristic Supply Voltages and Currents VDD Power On Reset Threshold VDD Power On Reset Hysteresis – VPWR Undervoltage Outputs Latched Off By Event 4.0 4.5 5.0 V VPWR Overvoltage Lockout Outputs Latched Off By Event 30 35 45 V Digital Supply Current, IV(DD) All Outputs On (@ 350 mA) – – 5.0 mA Analog Supply Current, IV(PWR) All Outputs On (@ 350 mA) – – 5.0 mA Sleep Current, IV(PWR) VDD ≤ 0.5 V – – 10 µA VIN High SI, SCLK, CSB, IN0, IN1, IN2, IN3 70 – – %VDD VIN Low SI, SCLK, CSB, IN0, IN1, IN2, IN3 – – 30 %VDD – 230 – mV Digital Inputs and Outputs VIN Hysteresis – Input Pulldown Current SI, IN0, IN1, IN2, IN3, VIN = 30% VDD – – 25 µA Input Pullup Current CSB, VIN = 70% VDD – – –25 µA Status Low ISTATUS = 0.5 mA – 0.1 0.5 V Overcurrent Sense Time, tSS Overcurrent Sense Time, ROSC = 82 kΩ 25 62.5 100 µs Overcurrent Shutdown Time Overcurrent Shutdown Time, ROSC = 82 kΩ 1.60 3.94 6.3 ms Fault Duty Cycle After the first fault cycle, Note 1. 1.4 1.56 1.7 % Open Load Trip Point IN = Low 40 50 60 %VDD Open Load Sense Time Open Load Sense Time, ROSC = 82 kΩ 12.5 – 100 µs Fault Detection/Timing Power Outputs VDRAIN Clamp ID = 20 mA, tCLAMP = 100 µs 48 52 64 V Drain Leakage Current VDRAIN = 17 V – – 25 µA Drain Leakage Current VDRAIN = 46 V – – 400 µA RDS(ON) VPWR = 13 V, ID = 0.5 A – 1.0 2.0 Ω Current Limit Note 2. 3.0 4.5 6.0 A Reverse Diode Drop Reverse Diode Drop I = 350 mA – – 1.4 V Fall Time Delay, tphl VPWR = 13 V, RLOAD = 33 Ω, Note 3. (see Figure 2) – – 10 µs Rise Time Delay, tplh VPWR = 13 V, RLOAD = 33 Ω, Note 3. (see Figure 2) – – 15 µs Rise Time, tr VPWR = 13 V, RLOAD = 33 Ω 0.4 – 10 µs Fall Time, tf VPWR = 13 V, RLOAD = 33 Ω 0.4 – 10 µs 1. Guaranteed by design. 2. A duty cycle mode will initiate at a minimum of 1.0 A and before the current limit. 3. Output turn on delay and turn off delay from rising edge of CSB to the output reaching 50% of VPWR. http://onsemi.com 3 CS1112 ELECTRICAL CHARACTERISTICS (continued) (9.0 V < VPWR < 17 V, 4.5 V < VDD < 5.5 V, –40°C < TJ < 125°C, 5.5 V < VPWR < 25 V, (Outputs Functional); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit 250 – – ns Serial Peripheral Interface VPWR = 14 V SCLK Clock Period CO = 200 pF MAX Input Capacitance SI, SCLK, Note 1. – – 12 pF VOUT High SO, IOH = 1.0 mA VDD – 1.0 – – V VOUT Low SO, IOL = 1.0 mA – – 0.5 V SCLK High Time FSCLK = 4.0 MHz, SCLK = 2.0 V to 2.0 V (see Figure 1) 125 – – ns SCLK Low Time FSCLK = 4.0 MHz, SCLK = 0.8 V to 0.8 V (see Figure 1) 125 – – ns SI Setup Time SI = 0.8 V/2.0 V to SCLK = 2.0 V at 4.0 MHz; Note 1. (see Figure 1) 25 – – ns SI Hold Time SCLK = 2.0 V to SI = 0.8 V/2.0 V at 4.0 MHz; Note 1. (see Figure 1) 25 – – ns SO Rise Time CLD = 200 pF (0.1 VDD to 0.9 VDD); Note 1. – 25 50 ns SO Fall Time CLD = 200 pF (0.9 VDD to 0.1 VDD); Note 1. – – 50 ns CSB Setup Time CSB = 0.8 V to SCLK = 2.0 V (see Figure 1) Note 1. 60 – – ns CSB Hold Time SCLK = 0.8 V to CSB = 2.0 V (see Figure 1) Note 1. 75 – – ns SO Delay Time SCLK = 0.8 V to SO Data Valid, VDD = 5.0 V CLD = 200 pF at 4.0 MHz (see Figure 1); Note 1. – 65 125 ns Xfer Delay Time CSB rising edge to next falling edge. Note 1. 1.0 – – µs 1. Guaranteed by design. PACKAGE PIN DESCRIPTION PACKAGE PIN # 24 Lead SOIC PIN SYMBOL 1 VDD 2 VPWR Input voltage to bias gate drive circuitry. 3 OUT0 Open drain output one. 4 IN0 Parallel input one. 5, 6, 7, 8 17, 18, 19, 20 GND Ground Reference. 9 IN1 10 OUT1 11 SI 12 CSB SPI active low chip select. 13 SCLK SPI clock input. 14 SO FUNCTION Input voltage to bias logic and control circuitry. Parallel input two. Open drain output two. SPI serial input. SPI serial output. http://onsemi.com 4 CS1112 PACKAGE PIN DESCRIPTION (continued) PACKAGE PIN # 24 Lead SOIC PIN SYMBOL 15 OUT2 16 IN2 Parallel input three. 21 IN3 Parallel input four. 22 OUT3 23 STATUS Open drain output, which is asserted when an open load or overcurrent condition occurs at any of the outputs. 24 ROSC 82 kΩ resistor tied to ground to set up accurate internal current sources. FUNCTION Open drain output three. Open drain output four. CIRCUIT DESCRIPTION Typical Operation OUT3. Turning the output drivers on is an OR function with the SPI input and the parallel inputs. Note: To prevent damage to the IC or the output load, VDD must be above the Power on Reset threshold (3.5 V) before IN0, IN1, IN2, or IN3 are asserted high (< 70% VDD). Control of the CS1112 can be done using the Serial Peripheral Interface (SPI) port using the Data Input information in Table 1, or the outputs can be controlled via the parallel inputs (IN0, IN1, IN2, IN3). IN0 controls OUT0, IN1 controls OUT1, IN2 controls OUT2, and IN3 controls TIMING DIAGRAM CS SCLK Don’t Care OUT0 Turn ON OUT3 Turn ON OUT2 Turn ON OUT1 Turn OFF SI OUT0 OUT1 OUT2 OUT3 Time Table 1. SPI Inputs D7 D6 D5 D4 D3 D2 D1 D0 X X X X OUT3 OUT2 OUT1 OUT0 MSB LSB X = Don’t Care; MSB is Transferred first. http://onsemi.com 5 CS1112 SERIAL PERIPHERAL INTERFACE TIMING REQUIREMENTS CSB (Setup) CSB (Hold) CSB SI (Setup) 1 2 3 SCLK CSB SI (Hold) SI tf Xfer Delay MSB tphl OUTX SO tr 70% VDD MSB 30% VDD SO(Delay) tplh SO(Rise,Fall) Figure 2. Figure 1. BLOCK DIAGRAM IN0 IN1 IN2 IN3 VPWR VDD 10 µA Overvoltage/ Undervoltage Lockout 10 µA VREG OUT0 OUT1 OUT2 CSB Gate Drive Data 0 SI 10 µA Serial Peripheral Interface OUT3 ILIMIT Data 1 to 3 Fault 1 to 3 + – RS SCLK SO Serial D/O Line Driver VDD Power On Reset Fault 0 RESET RESET Open Load OUT – GND + ENABLE Data 0 1/2 VDD 4.0 ms Fault Timer ROSC Bias Data 0 Shorted Load http://onsemi.com 6 STATUS CS1112 APPLICATION INFORMATION CIRCUIT DESCRIPTION The CS1112 was developed for use in very noisy and very harsh environments such as seen in an automobile system. The device has four low–side switches all controlled through an 8–bit Serial Peripheral Interface (SPI) port. Control of the outputs is also OR’d with parallel inputs. This is a critical feature enhancement over similar devices because of the ease in which the parallel inputs can be used to control the outputs in a Pulse Width Modulation (PWM) mode. Creating a PWM mode using just the serial port input is not a practical application. This part uses ON Semiconductor’s POWERSENSE process technology. POWERSENSE combines the robustness of Bipolar with the dense logic capability of CMOS, and the power capabilities of DMOS. Power consumption is kept to a minimum using POWERSENSE in comparison to a bipolar technology. A bipolar process requires DC bias currents to power–up the integrated circuit. This is needed in many applications requiring analog circuitry, but is not needed here. Digital POWERSENSE logic dissipates power only when switching because that is when transient gate charging current flows. POWERSENSE logic requires little space, and is a good economical solution. The DMOS side of the process provides a robust user interface to the outside world on each of the outputs. Peak transient capability of each output is rated at a maximum of 46 V (typical of an automotive load dump transient). The CS1112 uses quasi–vertical DMOS transistors resulting in an output resistance (RDS(ON)) at each output of less than 1.0 Ω @ 13 V and 500 mA @ 25°C. The part can be put in a sleep mode where the part draws less than 2.0 µA of bias current from VPWR. The part enters this sleep mode when VDD ≤ 0.5 V. Maximum quiescent current for the device is 5.0 mA maximum for any combination of output drivers enabled. Fault reporting is controlled by the CS1112. Overcurrent and short to VBATT are detected when the output is on. Open load and short to ground are detected when the output is off. Faults are reported out of the serial output (SO) pin as a new 8–bit word is being fed into the serial input (SI) pin. Figure 3 highlights the SPI interface between the microprocessor and the CS1112. The SPI control inputs and all other logic inputs are compatible with 5.0 V CMOS logic levels. CS1112 µP SI SO Shift Register µP IN1 IN2 3 210 CSB IN0 X XX X 3 2 1 0 SCLK Receive Buffer Parallel Inputs Control STATUS Output Logic SPI Interface Fault Reporting Figure 3. The four communication lines which define the SPI interface are the SI, SO, CSB, and SCLK. The parallel inputs, which control the outputs can also connect to the same microprocessor, a separate microprocessor, or any other sensor or electrical device which meets the voltage requirements of the CS1112 (VIN(max) = VDD + 0.3 V). SPI communication is as follows (2 scenarios): 1. 8–Bit Normal Operation CSB pin is brought low activating the SPI port. Faults detected since the last CSB low to high transition are latched into the serial register when CSB goes low. 8 command bits are clocked into the SI pin. The four fault bits are clocked out of the SO pin. CSB pin is brought high translating the final 4 bits to the outputs turning them on or off. Faults are then detected and saved in the fault register when CSB goes low. 2. 16–Bit Operation For Command Verify CSB pin is brought low activating the SPI port. 16 bits are clocked into the SI pin (the last 4 are the 4 control pins for the four outputs). CSB pin is brought high translating the last 4 bits to the outputs turning them on or off. CSB pin is brought low activating the SPI port. 16 new bits are clocked into the SI pin. As the new bits are being clocked in, the first 8 bits being clocked out of the SO pin are the fault bits, followed by the first 8 bits which were clocked in (the verification bits). The verification bits should replicate the command bits. http://onsemi.com 7 CS1112 1 output with the SPI port, and 3 outputs being controlled with the parallel inputs allowing them to run in a PWM mode. Serial clock frequencies up to 4.0 MHz can be used by the CS1112. Internal pull–up circuitry is provided on the Chip Select Bar (CSB) pin. Internal active pulldowns are provided on the parallel input pins (IN0, IN1, IN2, IN3, and SI pin). A product highlight of this part is its ability to be daisy–chained with other parts which follow the SPI protocol as defined in Figure 1. Figure 4 displays this aspect. The serial output of each device is fed into the serial input of the next device. All data bits are clocked into their respective registers, while the CSB pin is low. The drivers are switched to the resulting command when the CSB pin is brought back high. SPI Controlled Outputs VBAT Z0 Z1 Z2 Z3 OUT0 OUT1 OUT2 OUT3 µP CSB µP CSB SCLK CS1112 CSB SCLK Any IC using SPI protocol CSB SCLK SI SCLK Any IC using SPI protocol SPI Port SI SO SI SO SI Figure 6. SO Parallel Controlled Outputs Figure 4. VBAT Multiple SPI port devices can also be connected in a parallel fashion (Figure 5) instead of the daisy–chained connection previously shown. The microprocessor controls the CS1112 in a multiplex fashion allowing the serial data input to be input to the device when the device is activated through the CSB pin. This creates a system whose number of outputs is a multiple of 4. Figure 5 displays a 12 output setup. ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Parallel Inputs Control µP IN0 OUT0 IN1 IN2 OUT1 Z0 Z1 Z2 Z3 OUT2 OUT3 CSB SCLK SI CS1112 µP SPI Controlled Outputs SI OUT0 SCLK OUT1 CSB OUT2 OUT3 SPI Port Figure 7. The CS1112 provides a very efficient way of controlling 4 output drivers by minimizing the number of I/O pins through use of the SPI port, and still provides the flexibility of pulse width modulating the output drivers where needed. The use of the SPI also allows the integrated circuit to communicate directly with the microprocessor. While designed for an automotive environment, the CS1112 can be used in other applications in the computer market, industrial market, telecommunications market, or any other instance where numerous drivers are needed. All parts are 100% tested and guaranteed to meet all parameters specified in the electrical characteristics. These specifications cover the entire voltage range for VPWR (9.0 V to 17 V), and VDD (4.5 V to 5.5 V). CS1112 OUT0 SI SCLK OUT1 OUT2 CSB OUT3 CS1112 SI OUT0 SCLK OUT1 CSB OUT2 OUT3 Figure 5. Figure 6 displays the device controlling 4 outputs with the use of its SPI port. Figure 7 displays the device controlling http://onsemi.com 8 CS1112 FAULT MODE OPERATION The signal on this pin is clocked from the falling edge of the SCLK pin. The serial output data provides fault information for each output and returns most significant bit (bit 7) first. Bits 0 through 3 are output fault bits for outputs 0 through 3, respectively. In 8–bit SPI mode, bits 0–3, under normal conditions return all zeros representing no faults. A 1 indicates a fault. The output from this pin conforms to CMOS logic levels. The CS1112 provides protection for a multitude of system faults and conditions. These include Overvoltage, Current Limit, Open Circuit, Output Short to Power, Output Short to Ground, and Flyback Clamp. Overvoltage The IC is constantly monitoring the voltage on the VPWR pin. If the voltage on this pin exceeds the Overvoltage Shutdown Threshold (typically 35 V), all outputs immediately turn off. The programmed outputs (via serial or parallel input) turn back on once the voltage is brought back down below this level. ROSC An 82 kΩ resistor tied to ground sets up an accurate internal current source. CSB The CSB (Chip Select Bar) is the select pin when the microprocessor wants to communicate with the CS1112. A low on this pin enables the SPI communication with the device and enables the SO pin. After the digital word is clocked into the IC, a transition from low to high on the CSB pin translates the last 4 bits of information turning the outputs on or off. An internal active pull–up is connected to this input. CMOS logic levels are required on this pin. Current Limit/Short to VBATT When the output current exceeds the Overcurrent (4.5 A typical) for the Short Circuit/Overcurrent Sense Time (typically 62.5 µs) as it would do during an output short to VBATT, its fault status bit will be latched to a logic one. The fault status bit remains latched until the rising edge of CSB. The output will go into a low duty cycle mode (typically 1.56%) as long as the overcurrent condition exists, and the channel is on. This protects the integrated circuit from damaging itself due to its thermal limits. SCLK The SCLK (Serial Clock) clocks the internal shift registers. This pin controls the data being shifted into the SI pin, and data being shifted out of the SO pin. CMOS logic levels are required on this pin. Open Circuit/Short to Ground Open circuit conditions are detected while the outputs are off. A fault bit is set when the Open Load “Off” Detection Voltage (typically 0.5 × VDD) is present for the Open Load “Off” Sense Time (typically 62.5 µs) as it would do during an output short to ground. IN0, IN1, IN2, IN3 These pins control their corresponding numbered output. These are the parallel input pins which may be used to PWM the outputs. They have 230 mV of hysteresis. These inputs are OR’d with their corresponding input bit in the serial control byte. An internal active pull–down is connected to these pins. CMOS logic levels are required on these pins. Flyback Clamp While the flyback clamp is not a fault mode, it is a protection feature of the CS1112. When driving inductive loads, it is normal to observe high voltage spikes on the output pin due to the stored energy in the windings when the device is turned off. On–chip clamps on the outputs limit the voltage amplitude on the pin to prevent damage to the device. Each output has an Output Clamp which limits the output voltage to 52 V (typical when measured at 20 mA for 100 µs). OUT0, OUT1, OUT2, OUT3 These pins are the output low–side driver pins. They all have typically 1.0 Ω RDS(ON) at VPWR = 13 V. Current limit on these pins has a minimum specification of 3.0 A. A low duty cycle mode (1.5% typ.) will initiate at a minimum of 1A and before the current limit. PIN FUNCTION DESCRIPTION SI VPWR The SI (Serial Input) receives serial 8–bit or 16–bit words sent most significant bit first. Data is clocked in on the rising edge of SCLK. An internal active pull–down is connected to this input. CMOS logic levels are required on this pin. VDD 14 V Battery voltage input. 5.0 mA (max) is needed. 5.0 V Supply input. 5.0 mA (max) is needed. STATUS SO Open drain output. This pin goes low when an open load or overcurrent condition occurs on any of the outputs. This provides immediate notification to the controller that a fault is present. The controller can subsequently query the device (serially) to determine its origin. The SO (Serial Output) can be connected to the serial data input pin of the microprocessor, or it can be daisy–chained to the serial input (SI) of another SPI compatible device. This pin is tri–stated unless a low CSB pin selects the device. http://onsemi.com 9 CS1112 PACKAGE DIMENSIONS SO–24L DW SUFFIX CASE 751E–04 ISSUE E –A– 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S DIM A B C D F G J K M P R F R X 45 C –T– SEATING PLANE M 22X G K MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0 8 10.05 10.55 0.25 0.75 PACKAGE THERMAL DATA Parameter SO–24L Unit RΘJC Typical 9 °C/W RΘJA Typical 55 °C/W http://onsemi.com 10 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029 CS1112 Notes http://onsemi.com 11 CS1112 POWERSENSE is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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