SAMSUNG K7A203600A

PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
Document Title
64Kx36-Bit Synchronous Pipelined Burst SRAM
Revision History
History
Draft Date
Remark
0.0
Initial draft
May. 19. 1998
Preliminary
0.1
Change t OH Min value from 1.3 to 1.0 at tCYC 5.0
Change t HZC Min value from 1.3 to 1.0 at tCYC 5.0
July. 13. 1998
Preliminary
0.2
Add tCYC 183MHz, 225MHz
Change DC Characteristics.
Icc value from 260mA to 280mA at -72
ISB1 value from 10mA to 20mA
ISB2 value from 10mA to 20mA
Aug. 31. 1998
Preliminary
1.0
Final spec release.
Nov. 16. 1998
Final
2.0
Add VDDQ Supply voltage( 2.5V )
Dec. 02. 1998
Final
Rev. No.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
64Kx36-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
The K7A203600A is a 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second
level cache of Pentium and Power PC based System.
It is organized as 64K words of 36bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed
and synchronous.
Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK.
The K7A203600A is fabricated using SAMSUNG′s high performance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to minimize ground bounce.
•
•
•
•
•
•
•
•
•
•
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
VDD= 3.3V+0.3V/-0.165V Power Supply.
VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a
linear burst.
Three Chip Enables for simple depth expansion with No Data
Contention ; 2 cycle Enable, 1 cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A
FAST ACCESS TIMES
Symbol
-22
-20
-18
-16
-15
-14
Unit
Cycle Time
PARAMETER
tCYC
4.4
5.0
5.4
6.0
6.7
7.2
ns
Clock Access Time
tCD
3.1
3.1
3.1
3.5
3.8
4.0
ns
Output Enable Access Time
tOE
3.1
3.1
3.1
3.5
3.8
4.0
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
BURST CONTROL
64Kx36
MEMORY
ARRAY
A′0~A′1
A0~A1
A0~A15
ADSP
ADDRESS
REGISTER
A2~A15
DATA-IN
REGISTER
CONTROL
REGISTER
CS1
CS2
CS2
GW
BW
WEa
WEb
WEc
WEd
OE
ZZ
BURST
ADDRESS
COUNTER
LOGIC
CONTROL
REGISTER
ADV
ADSC
OUTPUT
REGISTER
CONTROL
LOGIC
BUFFER
DQa0 ~ DQd7
DQPa ~ DQPd
-2-
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
A6
A7
CS1
CS2
WEd
WEc
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
A9
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100 Pin TQFP
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A4
A3
A2
A1
A0
N.C.
N.C.
VSS
VDD
N.C.
N.C.
A10
A11
A12
A13
A14
A15
N.C.
(20mm x 14mm)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
DQPc
DQc 0
DQc 1
VDDQ
VSSQ
DQc 2
DQc 3
DQc 4
DQc 5
VSSQ
VDDQ
DQc 6
DQc 7
N.C.
VDD
N.C.
VSS
DQd 0
DQd 1
VDDQ
VSSQ
DQd 2
DQd 3
DQd 4
DQd 5
VSSQ
VDDQ
DQd 6
DQd 7
DQPd
100
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
N.C.
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
PIN NAME
SYMBOL
PIN NAME
A0-A15
Address Inputs
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,
81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
SYMBOL
PIN NAME
TQFP PIN NO.
VDD
VSS
N.C.
Power Supply(+3.3V)
Ground
No Connect
15,41,65,91
17,40,67,90
14,16,38,39,42,43,50,66
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
VDDQ
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
VSSQ
-3-
Output Power Supply
(2.5V or 3.3V)
Output Ground
5,10,21,26,55,60,71,76
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A203600A is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC
based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration
of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2 cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
(Interleaved Burst)
Case 1
A1
0
0
1
1
Case 2
A0
0
1
0
1
A1
0
0
1
1
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
1
0
0
BURST SEQUENCE TABLE
LBO PIN
LOW
First Address
Fourth Address
A0
1
0
1
0
(Linear Burst)
Case 1
A1
0
0
1
1
Case 2
A0
0
1
0
1
A1
0
1
1
0
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
0
0
1
A0
1
0
1
0
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
-4-
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
CS2
CS2
ADSP
ADSC
ADV
WRITE
CLK
ADDRESS ACCESSED
OPERATION
H
X
X
X
L
X
X
↑
N/A
Not Selected
L
L
X
L
X
X
X
↑
N/A
Not Selected
L
X
H
L
X
X
X
↑
N/A
Not Selected
L
L
X
X
L
X
X
↑
N/A
Not Selected
L
X
H
X
L
X
X
↑
N/A
Not Selected
L
H
L
L
X
X
X
↑
External Address
Begin Burst Read Cycle
L
H
L
H
L
X
L
↑
External Address
Begin Burst Write Cycle
L
H
L
H
L
X
H
↑
External Address
Begin Burst Read Cycle
X
X
X
H
H
L
H
↑
Next Address
Continue Burst Read Cycle
H
X
X
X
H
L
H
↑
Next Address
Continue Burst Read Cycle
X
X
X
H
H
L
L
↑
Next Address
Continue Burst Write Cycle
H
X
X
X
H
L
L
↑
Next Address
Continue Burst Write Cycle
X
X
X
H
H
H
H
↑
Current Address
Suspend Burst Read Cycle
H
X
X
X
H
H
H
↑
Current Address
Suspend Burst Read Cycle
X
X
X
H
H
H
L
↑
Current Address
Suspend Burst Write Cycle
H
X
X
X
H
H
L
↑
Current Address
Suspend Burst Write Cycle
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
BW
WEa
WEb
WEc
WEd
OPERATION
H
H
X
X
X
X
READ
H
L
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
H
L
H
L
H
H
WRITE BYTE b
H
L
H
H
L
L
WRITE BYTE c and d
H
L
L
L
L
L
WRITE ALL BYTEs
L
X
X
X
X
X
WRITE ALL BYTEs
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
L
L
DQ
Read
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must
be disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
-5-
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE
OPERATION
PRESENT CYCLE
WRITE
OPERATION
NEXT CYCLE
CS1
WRITE
OE
Write Cycle, All bytes
Address=An-1, Data=Dn-1
All L
Initiate Read Cycle
Address=An
Data=Qn-1 for all bytes
L
H
L
Read Cycle
Data=Qn
Write Cycle, All bytes
Address=An-1, Data=Dn-1
All L
No new cycle
Data=Qn-1 for all bytes
H
H
L
No carryover from
previous cycle
Write Cycle, All bytes
Address=An-1, Data=Dn-1
All L
No new cycle
Data=High-Z
H
H
H
No carryover from
previous cycle
Write Cycle, One byte
Address=An-1, Data=Dn-1
One L
Initiate Read Cycle
Address=An
Data=Qn-1 for one byte
L
H
L
Read Cycle
Data=Qn
Write Cycle, One byte
Address=An-1, Data=Dn-1
One L
No new cycle
Data=Qn-1 for one byte
H
H
L
No carryover from
previous cycle
Note : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Voltage on VDD Supply Relative to VSS
VDD
-0.3 to 4.6
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
VDD
V
Voltage on Input Pin Relative to VSS
VIN
-0.3 to 6.0
V
Voltage on I/O Pin Relative to VSS
VIO
-0.3 to VDDQ+0.5
V
Power Dissipation
Storage Temperature
PD
1.2
W
TSTG
-65 to 150
°C
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature Range Under Bias
TBIAS
-10 to 85
°C
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C≤ T A≤70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.6
V
VDDQ
3.135
3.3
3.6
V
VSS
0
0
0
V
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.6
V
VDDQ
2.375
2.5
2.9
V
VSS
0
0
0
V
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
TEST CONDITION
MIN
MAX
UNIT
CIN
VIN=0V
-
5
pF
COUT
VOUT=0V
-
7
pF
*Note : Sampled not 100% tested.
-6-
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
Input Leakage Current(except ZZ)
IIL
VDD=Max ; VIN=VSS to VDD
-2
+2
µA
Output Leakage Current
IOL
Output Disabled, VOUT=VSS to VDDQ
-2
+2
µA
-22
-
440
-20
-
400
-18
-
380
-16
-
360
-15
-
320
-14
-
280
-22
-
110
-20
-
100
-18
-
100
-16
-
90
-15
-
80
-14
-
70
-
20
mA
-
20
mA
0.4
V
Operating Current
ICC
ISB
Device Selected, I OUT=0mA,
ZZ≤VIL, All Inputs=VIL or VIH
Cycle Time≥tCYC min
Device deselected, IOUT = 0mA,
ZZ≤VIL, f = Max,
All Inputs≤0.2V or≥VDD-0.2V
Standby Current
ISB1
ISB2
Device deselected, IOUT = 0mA, ZZ≤0.2V,
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA,
ZZ≥VDD-0.2V, f = Max, All Inputs≤VIL or≥VIH
mA
mA
Output Low Voltage(3.3V I/O)
VOL
IOL = 8.0mA
-
Output High Voltage(3.3V I/O)
VOH
IOH = -4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
VOL
IOL = 1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
VOH
IOH = -1.0mA
Input Low Voltage(3.3V I/O)
VIL
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
2.0
-
V
-0.5*
0.8
V
VIH
2.0
VDD+0.5**
V
VIL
-0.3*
0.7
V
VIH
1.7
VDD+0.5**
V
* VIL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH (Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ +0.5V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
1ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
1ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
-7-
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50Ω
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
30pF*
Z0=50Ω
319Ω / 1667Ω
Dout
353Ω / 1538Ω
* Capacitive Load consists of all components of
the test environment.
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS (TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
-22
PARAMETER
SYMBOL
-20
-18
-16
-15
-14
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Cycle Time
tCYC
4.4
-
5.0
-
5.4
-
6.0
-
6.7
-
7.2
-
ns
Clock Access Time
tCD
-
3.1
-
3.1
-
3.1
-
3.5
-
3.8
-
4.0
ns
Output Enable to Data Valid
tOE
-
3.1
-
3.1
-
3.1
-
3.5
-
3.8
-
4.0
ns
Clock High to Output Low-Z
tLZC
0
-
0
-
0
-
0
-
0
-
0
-
ns
Output Hold from Clock High
tOH
1.0
-
1.0
-
1.0
-
1.5
-
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
0
-
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
3.1
-
3.1
-
3.1
-
3.5
-
3.8
-
4.0
ns
Clock High to Output High-Z
tHZC
1.0
3.1
1.0
3.1
1.0
3.1
1.5
3.5
1.5
3.8
1.5
4.0
ns
Clock High Pulse Width
tCH
2.0
-
2.0
-
2.0
-
2.0
-
2.4
-
2.8
-
ns
Clock Low Pulse Width
tCL
2.0
-
2.0
-
2.0
-
2.0
-
2.4
-
2.8
-
ns
Address Setup to Clock High
tAS
1.4
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
Address Status Setup to Clock High
tSS
1.4
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
Data Setup to Clock High
t DS
1.4
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
tWS
1.4
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
Address Advance Setup to Clock High
tADVS
1.4
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
Chip Select Setup to Clock High
tCSS
1.4
-
1.4
-
1.4
-
1.5
-
1.5
-
1.5
-
ns
Address Hold from Clock High
t AH
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
ns
Address Status Hold from Clock High
t SH
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
ns
Write Hold from Clock High (GW, BW, WEX)
tWH
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
2
-
2
-
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
2
-
2
-
2
-
2
-
cycle
Write Setup to Clock High (GW, BW, WEX)
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
-8-
December 1998
Rev 2.0
-9-
Data Out
OE
ADV
tCSS
tAS
tSS
A1
tADVS
tCSH
tWS
tAH
tSH
Q1-1
A2
tHZOE
tSH
Q2-1
tCD
tOH
Q2-2
A3
Q2-3
(ADV INSERTS WAIT STATE)
BURST CONTINUED WITH
NEW BASE ADDRESS
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tLZOE
tOE
tADVH
tWH
tSS
tCYC
tCL
Q2-4
Q3-1
Q3-2
Q3-3
Undefined
Don′t Care
Q3-4
tHZC
K7A203600A
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCH
TIMING WAVEFORM OF READ CYCLE
PRELIMINARY
64Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 10 -
Data Out
Data In
OE
Q0-3
tCSS
tAS
tSS
Q0-4
A1
tHZOE
tCSH
tAH
tSH
D1-1
tCYC
tCL
A2
D2-1
D2-2
(ADV SUSPENDS BURST)
D2-2
D2-3
(ADSC EXTENDED BURST)
D2-4
D3-1
A3
tDS
tADVS
tWS
tSS
D3-2
tDH
tADVH
tWH
tSH
D3-3
Undefined
Don′t Care
D3-4
K7A203600A
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCH
TIMING WAVEFORM OF WRTE CYCLE
PRELIMINARY
64Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 11 -
Data Out
Data In
OE
tHZC
tSS
A1
tSH
tLZC
tCD
tAS
Q1-1
A2
tHZOE
tDS
tADVS
tWS
tAH
tCYC
tCL
D2-1
tDH
tADVH
tWH
A3
tLZOE
tOE
Q2-1
Q3-1
Q3-2
tOH
Q3-3
Undefined
Don′t Care
Q3-4
K7A203600A
ADV
CS
WRITE
ADDRESS
ADSP
CLOCK
tCH
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH)
PRELIMINARY
64Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 12 -
Data In
Data Out
OE
tCSS
tSS
A1
tCSH
tSH
tOE
tLZOE
A2
Q1-1
A3
Q2-1
A4
Q3-1
Q4-1
tHZOE
D5-1
A5
tDS
tWS
D6-1
A6
tDH
tWH
D7-1
A7
A8
tCD
tWS
tCYC
tCL
tWH
Q7-1
A9
Q8-1
Undefined
Don′t Care
Q9-1
tOH
K7A203600A
ADV
CS
WRITE
ADDRESS
ADSC
CLOCK
tCH
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH)
PRELIMINARY
64Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 13 -
ZZ
Data Out
Data In
OE
tCSS
tAS
tSS
A1
tCSH
tAH
tSH
tLZOE
tOE
Q1-1
ZZ Setup Cycle
tPDS
tHZC
Sleep State
tPUS
ZZ Recovery Cycle
tCYC
tCL
tWS
Normal Operation Mode
tHZOE
A2
D2-1
tWH
Undefined
Don′t Care
D2-2
K7A203600A
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCH
TIMING WAVEFORM OF POWER DOWN CYCLE
PRELIMINARY
64Kx36 Synchronous SRAM
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 64Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 64K depth to 128K depth without extra logic.
I/O[0:71]
Data
Address
A[0:16]
A[16]
A[0:15]
A[16]
Address
CLK
64-Bits
Microprocessor
CS2
CS2
CS2
64Kx36
SPB
SRAM
ADSC
CLK
Address
Data
CS2
CLK
Address
A[0:15]
CLK
ADSC
WEx
64Kx36
SPB
SRAM
WEx
(Bank 1)
(Bank 0)
Cache
Controller
Data
OE
OE
CS1
CS1
ADSP
ADV
ADV
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
ADDRESS
[0:n]
tAH
A2
A1
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS
Bank 0 is deselected by CS2 , and Bank 1 selected by CS2
tADVH
ADV
OE
tOE
Data Out
(Bank 0)
tHZC
tLZOE
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
- 14 -
Q2-2
Q2-3
Don′t Care
Q2-4
Undefined
December 1998
Rev 2.0
PRELIMINARY
K7A203600A
64Kx36 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units:millimeters/inches
0~8°
22.00 ±0.30
0.10
0.127 +- 0.05
20.00 ±0.20
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50
#1
0.65
±0.10
(0.58)
0.30 ±0.10
0.10 MAX
1.40
0.50 ±0.10
- 15 -
±0.10
1.60 MAX
0.05 MIN
December 1998
Rev 2.0