KM62256C Family CMOS SRAM Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Advance information February 12th 1993 Design target 0.1 Initial draft November 2nd 1993 Preliminary 1.0 Finalize September 24th 1994 Final 2.0 Revise - Add 45ns part with 30pF test load August 12th 1995 Final 3.0 Revise - Change specification format and merge : Commercial, Extended, Industrial product in same datasheets. April 15th 1996 Final 4.0 Revise - Change Speed bin Erase 45ns part from commercial product and 100ns from extended and industrial product. - Production change Erase Low power product from TSOP package December 19 1997 Final The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and product. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. 1 Revision 4.0 December 1997 KM62256C Family CMOS SRAM 32Kx8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology : 0.7µm CMOS • Organization : 32Kx8 • Power Supply Voltage : Single 5V±10% • Low Data Retention Voltage : 2V(Min) • Three state output and TTL Compatible • Package Type : 28-DIP-600, 28-SOP-450, 28-TSOP1 -0813.4F/R The KM62256C family is fabricated by SAMSUNG′s advanced CMOS process technology. The family supports various operating temperature ranges and has various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature. Speed(ns) Commercial (0~70°C) 55/70ns KM62256CL KM62256CL-L KM62256CLE Extended (-25~85°C) 70ns KM62256CLE-L KM62256CLI Industrial (-40~85°C) 70ns KM62256CLI-L 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A3 7 A2 8 28-DIP 22 28-SOP 21 A1 9 20 CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 VSS 14 15 I/O4 A11 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 28-TSOP Type I - Forward 100µA 28-SOP 28-TSOP I R/F 100µA 28-SOP 28-TSOP I R/F 100µA Operating (Icc2) 20µA 70mA 50µA 50µA 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 Clk gen. Precharge circuit. A3 A4 A5 A6 A7 Memory array 512 rows 64×8 columns Row select A8 28-TSOP Type I - Reverse NameName A0~A14 28-DIP, 28-SOP 28-TSOP I R/F OE A10 Standby (ISB1 , Max) FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION A14 PKG Type A12 A13 A14 Data cont I/O1 I/O8 I/O Circuit Column select Data cont Function A0 Address Inputs WE Write Enable Input CS Chip Select Input CS OE Output Enable Input WE I/O1~I/O8 Data Inputs/Outputs OE Vcc Power(5V) Vss Ground A1 A2 A9 A10 A11 Control Logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 4.0 December 1997 KM62256C Family CMOS SRAM PRODUCT LIST Commercial Temp Product (0~70°C) Part Name Extended Temp Products (-25~85°C) Function KM62256CLP-5 KM62256CLP-5L KM62256CLP-7 KM62256CLP-7L KM62256CLG-5 KM62256CLG-5L KM62256CLG-7 KM62256CLG-7L KM62256CLTG-5L KM62256CLTG-7L KM62256CLRG-5L KM62256CLRG-7L Part Name Industrial Temp Products (-40~85°C) Function KM62256CLGE-7 28-DIP, 55ns, L-pwr KM62256CLGE-7L 28-DIP, 55ns, LL-pwr KM62256CLTGE-7L 28-DIP, 70ns, L-pwr KM62256CLRGE-7L 28-DIP, 70ns, LL-pwr 28-SOP, 55ns, L-pwr 28-SOP, 55ns, LL-pwr 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP F, 55ns, LL-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP R, 55ns, LL-pwr 28-TSOP R, 70ns, LL-pwr Part Name 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP R, 70ns, LL-pwr KM62256CLGI-7 KM62256CLGI-7L KM62256CLTGI-7L KM62256CLRGI-7L Function 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP R, 70ns, LL-pwr Note : LL means Low Low standby current. FUNCTIONAL DESCRIPTION CS OE WE I/O Pin Mode Power H X X High-Z Deselected Standby L H H High-Z Output Disabled Active L L H Dout Read Active L X L Din Write Active 1. X means don′t care ABSOLUTE MAXIMUM RATINGS Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time 1) Symbol Ratings Unit Remark VIN,VOUT -0.5 to VCC+0.5 V - VCC -0.5 to 7.0 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C KM62256CL TA -25 to 85 °C KM62256CLE -40 to 85 °C KM62256CLI TSOLDER 260°C, 10sec(Lead Only) - - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 Revision 4.0 December 1997 KM62256C Family CMOS SRAM 1) RECOMMENDED DC OPERATING CONDITIONS Item Symbol Min Typ Max Unit Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 Input high voltage VIH 2.2 - Input low voltage VIL Vcc+0.5V - 3) -0.5 V V 2) 0.8 V Note 1. Commercial Product : TA=0 to 70°C, unless otherwise specified Extended Product : TA=-25 to 85°C, unless otherwise specified Industrial Product : TA=-40 to 85°C, unless otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot is sampled, not 100% tested CAPACITANCE 1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Min Typ Max Unit Input leakage current Item Symbol ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL - 7 ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V, VIN≤0.2V, VIN≥Vcc -0.2V - - ICC2 Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - Output low voltage VOL IOL=2.1mA - Output high voltage VOH IOH=-1.0mA Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL Average operating current Test Conditions KM62256CL KM62256CL-L Standby Current (CMOS) KM62256CLE KM62256CLE-L ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc KM62256CLI KM62256CLI-L 1) 15 mA 72) mA - 70 mA - 0.4 V 2.4 - - V - - 13) mA L(Low Power) LL(L Low Power) - 2 1 100 20 µA L(Low Power) LL(L Low Power) - - 100 50 µA L(Low Power) LL(L Low Power) - - 100 50 µA 1. 20mA for Extended and Industrial Products 2. 10mA for Extended and Industrial Products 3. 2mA for Extended and Industrial Products 4 Revision 4.0 December 1997 KM62256C Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falingl time : 5ns input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS(Vcc=4.5~5.5V, KM62256C Family : T A=0 to 70°C, KM62256CE Family : TA=-25 to 85°C, KM62256CI Family : T A=-40 to 85°C) Speed Bins Parameter List Symbol 55ns Min Read Write Units 70ns Max Min Max Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 30 ns Output disable to high-Z output tOHZ 0 20 0 30 ns Output hold from address change tOH 5 - 5 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol VDR KM62256CL KM62256CL-L Data retention current IDR KM62256CLE KM62256CLE-L Vcc=3.0V CS≥Vcc-0.2V KM62256CLI KM62256CLI-L Data retention set-up time tSDR Recovery time tRDR Min Typ Max Unit 2.0 - 5.5 V L-Ver LL-Ver - 1 0.5 50 10 L-Ver LL-Ver - - 50 25 L-Ver LL-Ver - - 50 25 Test Condition CS≥Vcc-0.2V See data retention waveform 5 0 - - 5 - - µA ms Revision 4.0 December 1997 KM62256C Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 4.0 December 1997 KM62256C Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS GND CS≥VCC - 0.2V 7 Revision 4.0 December 1997 KM62256C Family CMOS SRAM PACKAGE DIMENSIONS Units :millimeters(inches) 28 PIN DUAL INLINE PACKAGE(600mil) +0.10 -0.05 0.010+0.004 -0.002 0.25 #28 #15 15.24 0.600 13.60±0.20 0.535±0.008 #1 #14 0~15° 3.81±0.20 0.150±0.008 36.72 MAX 1.446 5.08 0.200 MAX 36.32±0.20 1.430±0.008 3.30±0.30 0.130±0.012 0.46±0.10 0.018±0.004 1.52±0.10 0.060±0.004 ( 1.65 ) 0.065 0.38 0.015 MIN 2.54 0.100 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) 0~8° #15 11.81±0.30 0.465±0.012 #1 8.38±0.20 0.330±0.008 #14 +0.10 -0.05 0.006+0.004 -0.002 0.15 2.59±0.20 0.102±0.008 18.69 0.736 MAX 11.43 0.450 #28 1.02±0.20 0.040±0.008 3.00 0.118MAX 18.29±0.20 0.720±0.008 0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.41±0.10 0.016±0.004 1.27 0.050 8 0.05 MIN 0.002 Revision 4.0 December 1997 KM62256C Family CMOS SRAM PACKAGE DIMENSIONS Units :millimeters(inches ) 0.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) +0.10 -0.05 +0.004 0.008-0.002 0.20 13.40±0.20 0.528±0.008 #1 #28 0.55 0.0217 #14 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #15 1.00±0.10 0.039±0.004 0.05 0.002 MIN 1.20 0.047MAX 0.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R) +0.10 -0.05 +0.004 0.008-0.002 0.20 13.40±0.20 0.528±0.008 #14 #15 0.55 0.0217 #1 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #28 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00±0.10 0.039±0.004 0.05 0.002 MIN 1.20 0.047 MAX 0~8° 0.45 ~0.75 0.018 ~0.030 ( 9 0.50 ) 0.020 Revision 4.0 December 1997