KM681000E Family CMOS SRAM Document Title 128Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Design target October 12, 1998 Preliminary 1.0 Finalize - Improve tWP form 55ns to 50ns for 70ns product. - Remove 55ns speed bin for industrial product. August 30, 1999 Final 1.01 Errata correction December 1, 1999 The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.01 December 1999 KM681000E Family CMOS SRAM 128Kx8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: TFT • Organization: 128Kx8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP1-0820F The KM681000E families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature KM681000EL Vcc Range Speed Industrial(-40~85°C) 50mA 50µA 70ns KM681000ELI-L PKG Type 32-DIP, 32-SOP 32-TSOP1-0820F 10µA 4.5~5.5V KM681000ELI Operating (ICC2, Max) 50µA 55 1)/70ns Commercial(0~70°C) KM681000EL-L Standby (ISB1, Max) 32-SOP -525 32-TSOP1-0820F 15µA 1. The parameters are tested with 50pF test load PIN DESCRIPTION N.C 1 32 VCC A16 2 31 A15 A14 3 30 CS2 A12 4 29 WE A7 5 28 A13 A6 6 27 A5 7 A4 8 A3 9 A2 10 23 A1 11 22 A0 12 21 I/O1 13 20 A11 A9 A8 A13 A8 WE A9 CS2 A15 A11 VCC OE NC A16 A10 A14 A12 CS1 A7 I/O8 A6 A5 I/O7 A4 I/O2 14 19 I/O6 I/O3 15 18 I/O5 VSS 16 17 I/O4 26 32-DIP 32-SOP 25 24 FUNCTIONAL BLOCK DIAGRAM Clk gen. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-TSOP Type1-Forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Raw Address I/O1 I/O8 Name CS 1, CS2 WE Write Enable Input Vcc I/O Circuit Column select Data cont Chip Select Input Output Enable Input A0~A16 Data cont Memory array 1024 rows 128×8 columns Function OE I/O1~I/O8 Row select Precharge circuit. Column Address Data Inputs/Outputs Address Inputs CS 1 Power CS 2 WE Vss Ground N.C. No Connection Control logic OE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.01 December 1999 KM681000E Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name Industrial Temperature Products(-40~85°C) Function Part Name KM681000ELP-5 KM681000ELP-7 KM681000ELP-5L KM681000ELP-7L 32-DIP, 55ns, Low Power 32-DIP, 70ns, Low Power 32-DIP, 55ns, Low Low Power 32-DIP, 70ns, Low Low Power KM681000ELG-5 KM681000ELG-7 KM681000ELG-5L KM681000ELG-7L 32-SOP, 55ns, Low Power 32-SOP, 70ns, Low Power 32-SOP, 55ns, Low Low Power 32-SOP, 70ns, Low Low Power KM681000ELT-5L KM681000ELT-7L 32-TSOP F, 55ns, Low Low Power 32-TSOP F, 70ns, Low Low Power Function KM681000ELGI-7 KM681000ELGI-7L 32-SOP, 70ns, Low Power 32-SOP, 70ns, Low Low Power KM681000ELTI-7L 32-TSOP F, 70ns, Low Low Power FUNCTIONAL DESCRIPTION CS1 CS2 OE WE I/O Mode Power 1) X 1) X High-Z Deselected Standby X1) X1) High-Z Deselected Standby H H H High-Z Output Disabled Active L H L H Dout Read Active L H L Din Write Active H X X1) L L 1) 1) X 1. X means don′t care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit Remark VIN,VOUT -0.5 to 7.0 V - VCC -0.5 to 7.0 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C KM681000EL -40 to 85 °C KM681000ELI TA 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.01 December 1999 KM681000E Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit V Supply voltage Vcc KM681000E Family 4.5 5.0 5.5 Ground Vss All Family 0 0 0 Input high voltage VIH KM681000E Family 2.2 - Input low voltage VIL KM681000E Family -0.5 3) V Vcc+0.5 - V 2) 0.8 V Note: 1. Commercial Product: TA=0 to 70°C, and Industrial Product: TA=-40 to 85°C, otherwise specified 2. Overshoot : Vcc+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current Average operating current ICC IIO=0mA, CS1=VIL, CS 2=VIH, VIN=VIH or VIL, Read - - 10 mA ICC1 Cycle time=1µs, 100%duty, I IO=0mA, CS1 ≤0.2V, CS2 ≥Vcc-0.2V, V IN≤0.2V - - 7 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1 =VIL, CS2=VIH, VIN=VIH or VIL - - 50 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs=VIH or VIL - - 3 mA Standby Current(CMOS) ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc - - 501) µA 1. 50µA for Low power product, in case of Low Low power products are comercial=10µA, industrial=15µA. 4 Revision 1.01 December 1999 KM681000E Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : C L=100pF+1TTL CL=50pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product : TA=0 to 70°C, Industrial Product : TA=-40 to 85°C) Speed Bins Parameter List Symbol 55ns Min Read Write Units 70ns Max Min Max Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO1, tCO2 - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 20 - 25 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Symbol VDR IDR Data retention set-up time tSDR Recovery time tRDR Test Condition CS1≥Vcc-0.2V1) Vcc=3.0V, CS1≥Vcc-0.2V1) See data retention waveform Min Typ Max Unit 2.0 - 5.5 V KM681000EL - - 20 KM681000EL-L - - 10 KM681000ELI - - 25 KM681000ELI-L - - 10 0 - - 5 - - µA ms 1. CS1 ≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled) 5 Revision 1.01 December 1999 KM681000E Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. 6 Revision 1.01 December 1999 KM681000E Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS 1 tAW CS 2 tCW(2) tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tCW(2) tAS(3) tWR(4) CS 1 tAW CS 2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z 7 Revision 1.01 December 1999 KM681000E Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS1 , a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS 2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. t WR1 applied in case a write ends as CS1 or WE going high tWR2 applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS≥VCC - 0.2V CS1 GND CS2 controlled Data Retention Mode VCC 4.5V CS 2 tSDR tRDR VDR CS2≤0.2V 0.4V GND 8 Revision 1.01 December 1999 KM681000E Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 32 DUAL INLINE PACKAGE (600mil) 0.25 +0.10 -0.05 +0.004 0.010-0.002 #17 15.24 0.600 #32 13.60±0.20 0.535±0.008 #1 #16 0~15° 3.81±0.20 0.150±0.008 42.31 1.666 MAX 5.08 0.200 MAX 41.91±0.20 1.650±0.008 3.30±0.30 0.130±0.012 0.46±0.10 0.018±0.004 1.52±0.10 0.060±0.004 ( 1.91 ) 0.075 2.54 0.100 0.38 MIN 0.015 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #17 14.12±0.30 0.556±0.012 #1 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX 20.87 MAX 0.822 20.47±0.20 0.806±0.008 11.43±0.20 0.450±0.008 0.20 +0.10 -0.05 0.008+0.004 -0.002 13.34 0.525 #32 0.80±0.20 0.031±0.008 0.10 MAX 0.004 MAX ( 0.71 ) 0.028 +0.100 -0.050 +0.004 0.016 -0.002 0.41 1.27 0.050 0.05 MIN 0.002 9 Revision 1.01 December 1999 KM681000E Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 0.008+0.004 -0.002 0.20 20.00±0.20 0.787±0.008 #1 #32 8.40 0.331 MAX 0.50 0.0197 #17 #16 0.25 0.010 TYP 0.25 ) 0.010 8.00 0.315 ( 1.00±0.10 0.039±0.004 1.20 0.047 MAX 18.40±0.10 0.724±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0~8° 0.45 ~0.75 0.018 ~0.030 ( 10 0.10 MAX 0.004 MAX 0.15 0.50 ) 0.020 Revision 1.01 December 1999