KS57C21408/C21418/P21408 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The KS57C21408/C21418/P21408 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers. The KS57P21408 is especially suited for use in data bank, telephone and LCD general purpose. It is built around the SAM47 core CPU and contains ROM, RAM, 39 I/O lines, programmable timer/counter, buzzer output, enough LCD dot matrix, and segment drive pins. The KS57C21408/C21418/P21408 can be used for dedicated control functions in a variety of applications, and is especially designed for multi data bank, telephone and LCD game. OTP The KS57C21408/C21418 microcontroller is also available in OTP (One Time Programmable) version, KS57P21408. KS57P21408 microcontroller has an on-chip 8 K-byte one-time-programable EPROM instead of masked ROM. The KS57P21408 is comparable to KS57C21408/C21418, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS57C21408/C21418/P21408 FEATURES SUMMARY Memory LCD Display • 8192 × 8 bit program memory • 12 characters dot matrix display (5 x 7) • 5120 × 4 bit data memory in KS57C21408 • 12 digit display (8 segments) • 2560 x 4 bit data memory in KS57C21418 • 60 segments and 9 common pins • 108 x 5 bit display memory Power-Down Modes 39 I/O Pins • Idle mode (only CPU clock stops) • Input: 6 pins • • I/O: 17 pins Stop mode (Main-System clock and CPU clock stops) • Output: maximum 16 pins for 1-bit level output (sharing with segment driver outputs) Oscillation Sources • Crystal, ceramic, or External RC for system clock 8-Bit Basic Timer • Main-system clock frequency: 0.4 MHz - 6MHz • • Sub-system clock frequency: 32,768kHz • CPU clock divider circuit (by 4,8, or 64) Four internal timer functions 8-Bit Timer/Counter 0 • Programmable 8-bit timer Instruction Execution Times • External event counter • 0.67, 1.33, 10.7 µs at 6MHz • Arbitrary clock frequency output • 0.95, 1.91, 15.3 µs at 4.19 MHz • External clock signal divider • 122 µs at 32.768 kHz Watch Timer Operating Temperature • Time interval generation: 0,5ms, 3,9ms at 32768Hz • • 4 frequency (2/4/8/16 kHz) outputs to BUZ pin Operating Voltage Range • -45 °C to 85 °C 1.8 V to 5.5 V Interrupts • Three external vectored interrupts: INT0, INT1, INTP0 • Two internal vectored interrupts: INTB, INTT0 • Two quasi-interrupts: INTW, INT2 Memory Mapped I/O Structure 1-2 Package Type • 100-pin QFP Package KS57C21408/C21418/P21408 PRODUCT OVERVIEW BLOCK DIAGRAM INTT0, INTB, INTW INT0, INT1, INTP0, INT2 8-Bit Timer/ Counter 0 Watch Timer Basic Timer COM0-COM8 SEG16-SEG59 SEG0-SEG15 /P8.0-P8.15 LCD Driver/ Controller RESET XIN XOUT XTIN XTOUT Interrupt Control Block Clock Internal Interrupts Instruction Decoder Arithmetic and Logic Unit Data and Display Memory Instruction Register Program Counter Program Status Word Stack Pointer 8 K Byte Program Memory Input Port 0 P0.0-P0.3/ K0-K3 Input Port 1 P1.0/INT0 P1.1/INT1 I/O Port 2 P2.0/BUZ P2.1/CLO I/O Port 4 P4.0/TCL0 P4.1/TCLO0 P4.2 I/O Port 5 P5.0-P5.3 I/O Port 6 P6.0-P6.3/ KS0-KS3 I/O Port 7 P7.0-P7.3/ KS4-KS7 Output Port 8 P8.0-P8.15/ SEG0-SEG15 NOTE: Data memory: 5120 x 4 bits in KS57C21408 2560 x 4 bits in KS57C21418 Display memory: 108 x 5 bits Figure 1-1. KS57C21408/C21418/P21408 Specified Block Diagram 1-3 PRODUCT OVERVIEW KS57C21408/C21418/P21408 PIN ASSIGNMENTS SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 Xout Xin TEST XTin XTout RESET P2.0/BUZ P2.1/CLO P5.0 P5.1 P5.2 P5.3 TCL0/P4.0 TCLO0/P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG59 COM4 COM5 COM6 COM7 COM8 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 VDD VSS KS57C21408/C21418 100-QFP 1420C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15/P8.15 SEG14/P8.14 SEG13/P8.13 SEG12/P8.12 SEG11/P8.11 SEG10/P8.10 SEG9/P8.9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG8/P8.8 SEG7/P8.7 SEG6/P8.6 SEG5/P8.5 SEG4/P8.4 SEG3/P8.3 SEG2/P8.2 SEG1/P8.1 SEG0/P8.0 COM3 COM2 COM1 COM0 INT0/P1.0 INT1/P1.1 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P4.2 Figure 1-2. KS57C21408/C21418 Pin Assignment Diagram 1-4 KS57C21408/C21418/P21408 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Name Pin Description Type I P0.0 - P0.3 4-bit input port. 1 and 4-bit read, and test are possible. Pull-up registers. 2-bit Input port. P1.0 I 1 and 4-bit read, and test are possible, 2-bit pull-up P1.1 resistors are assignable by software. P2.0 I/O 2-bit I/O port. 1 and 4-bit read/write, and test are possible. P2.1 Each individual pin can be specified as input or output. 2-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. P4.0 I/O 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. P4.1 4-pin unit can be specified as input or output. P4.2 4-bit pull-up resistors are assignable by software. P5.0 - P5.3 Pull-up resistors are automatically disabled for output pins. Individual pins are software configurable as opendrain or push-pull output. P6.0 - P6.3 I/O 4-bit I/O port. 1, 4,and 8-bit read/write, and test are possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. P7.0 - P7.3 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. 4-pin unit can be specified as input or output. 4-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. P8.0 - P8.15 O 4-bit controllable output. (Dual function as segment output pins) SEG16-SEG59 LCD segment display signal output. Circuit Pin Type Number A-1 35-32 K0-K3 A-3 37 36 INT0 INT1 D 23 24 BUZ CLO E E-1 E-1 E-1 29 30 31 25-28 TCL0 TCLO0 D-1 7-10 KS0 - KS3 11-14 KS4 - KS7 H-9 42-57 H-10 58-100 ,1 42-57 SEG0 SEG15 - SEG0 - SEG15 LCD segment display signal output. H-9 COM0 - COM8 LCD common signal output. H-11 INT0 - INT1 I KS0 - KS7 I/O K0 - K3 I External interrupts. The triggering edge for INT0, and INT1 is selectable Quasi-interrupt input for falling edge detection. Vector interrupt input K0 - K3: falling edge detection Share Pin P8.0 - P8.15 38-41 2-6 37-36 P1.0 -P1.1 7-14 P6.0 - P7.3 35-32 P0.0 - P0.3 1-5 PRODUCT OVERVIEW KS57C21408/C21418/P21408 Table 1-1. Pin Descriptions (Continued) Pin Name BUZ CLO Pin Description Type I/O 2,4,8 kHz or 16kHz frequency output for buzzer signal. Clock output Xin, Xout - XTin, XTout - Circuit Type - Pin Num. 23 Share Pin - 24 P2.1 Crystal, ceramic or RC oscillator pins for main system clock. Crystal oscillator pins for sub-system clock. - 18, 17 - - 20, 21 - P2.0 TCL0 I/O External clock input for Timer/Counter 0 - 29 P4.0 TCLO0 I/O Timer/Counter 0 clock output - 30 P4.1 RESET I Reset input (active low). B 22 - VDD - Power supply. - 15 - VSS - Ground. - 16 - TEST I Test input: it must be connected to VSS - 19 - 1-6 KS57C21408/C21418/P21408 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-up Resistor P-channel Pull-up Resistor Enable P-channel IN IN N-channel Schmitt Trigger Vss Figure 1-5. Pin Circuit Type A-3 Figure 1-3. Pin Circuit Type A VDD VDD Pull-up Pull-up Resistor Enable P-channel Pull-up Register IN Schmitt Trigger IN Figure 1-4. Pin Circuit Type A-1 Figure 1-6. Pin Circuit Type B 1-7 PRODUCT OVERVIEW KS57C21408/C21418/P21408 VDD VDD Pull-up Resistor P-channel Data OUT N-channel Pull-up Resistor Enable P-channel Data Output Disable IN/OUT Type C Output Disable VSS Schmitt Trigger Figure 1-9. Pin Circuit Type D-1 Figure 1-7. Pin Circuit Type C VDD VDD PNE Pull-Up Resistor Pull-Up Resistor Enable VDD P-channel Pull-up Resistor Enable P-channel I/O Data Output Disable Data Pull-up Resistor Type C In/Out Output Disable N-channel Schmitt Trigger Figure 1-8. Pin Circuit Type D 1-8 Figure 1-10. Pin Circuit Type E KS57C21408/C21418/P21408 PRODUCT OVERVIEW VDD PNE Data VDD Pull-up resistor Pull-up Resistor Enable P-channel I/O Output Disable VLC2 Segment Data OUT N-channel VLC0 Figure 1-11. Pin Circuit Type E-1 Figure 1-13. Pin Circuit Type H-10 VDD SEG Data/P8.0-P8.15 VLC1 VLC2 VLC0 OUT OUT COM Data Vss Key strobe Vss Polarity Vss Figure 1-12. Pin Circuit Type H-9 Figure 1-14. Pin Circuit Type H-11 1-9 PRODUCT OVERVIEW KS57C21408/C21418/P21408 NOTES 1-10 KS57C21408/C21418/P21408 13 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on KS57C21408/C21418/P21408 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: STANDARD ELECTRICAL CHARACTERISTICS — Absolute maximum ratings — D.C electrical characteristics — Main-system clock oscillator characteristics — Sub-system clock oscillator characteristics — I/O capacitance — A.C electrical characteristics — Operating voltage range MISCELLANEOUS TIMING WAVEFORMS — A.C timing measurement point — Clock timing measurement at Xin — Clock timing measurement at XTin — TCL0 timing — Input timing for RESET — Input timing for external interrupts STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 13–1 ELECTRICAL DATA KS57C21408/C21418/P21408 Table 13-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Symbol Conditions Rating Units VDD – – 0.3 to + 6.5 V – 0.3 to VDD + 0.3 V – 0.3 to VDD + 0.3 V One pin – 15 mA All output pins – 30 mA Peak value 30 mA RMS value (note) 15 mA Peak value 100 mA RMS value (note) 60 mA Input Voltage VI Output Voltage VO High Level IOH Ports 0, 1, 2, 4, 5, 6, 7 – Output current IOL Low Level One pin Output Current All pins Operating TA – – 40 to + 85 °C TSTG – – 65 to + 150 °C Temperature Storage Temperature NOTE : RMS value = Peak Value × Duty . Table 13-2. D.C Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min. Typ. Max. Units V Input High VIH1 Pins except below 0.7 VDD – VDD Voltage VIH2 Port0, 1, 6, 7, P4.0, RESET 0.8 VDD – VDD VIH3 XIN, XOUT and XTIN VDD – 0.1 – VDD Input Low VIL1 All input pins except below – – 0.3 VDD Voltage VIL2 Port0, 1, 6, 7, P4.0, RESET – 0.2 VDD VIL3 XIN,XOUT and XTIN – 0.1 VOH1 VDD = 4.5 V to 5.5 V Port2, 4, 5, 6, 7 IOH = – 1mA – – Output High Voltage 13–2 VDD – 1.0 KS57C21408/C21418/P21408 ELECTRICAL DATA Table 13-2. D.C Characteristics(continued) (TA = – 40 °C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Min. Typ. Max. VDD = 4.5 V to 5.5 V Port2, 4, 5, 6, 7 IOL= 15mA – – 2 VDD = 1.8 V to 5.5 V IOL=1.6mA – – 0.4 ILIH1 Vin = VDD All input pins except below – – 3 ILIH2 Vin = VDD XIN, XOUT, XTIN ILIL1 VIN = 0 V All input pins except XIN, XOUT, XTIN and RESET – – –3 ILIL2 VIN = 0 V XIN, XOUT, XTIN – – – 20 Output High Leakage Current ILOH1 VO = VDD Port2, 4, 5, 6, 7 – – 3 Output Low Leakage Current ILOL1 VO = 0 V Port2, 4, 5, 6, 7 – – –3 Pull-up Resistor RL1 VDD = 5 V, VIN = 0 V All pins except RESET VDD = 3 V 25 50 100 50 100 200 VDD = 5 V, VIN = 0 V 100 250 400 200 500 800 Output Low Voltage Input High Leakage Current Input Low Leakage Current Symbol VOL1 RL2 Conditions Units µA 20 KΩ RESET VDD = 3 V Medium Output VOM1 COM0-COM8 VM1 – 0.2 VM1 VM1 + 0.2 Voltage(1) VOM2 COM0-COM8 VM2 – 0.2 VM2 VM2 + 0.2 VOM3 SEG0-CSEG59 VM3 – 0.2 VM3 VM3 + 0.2 VOM4 SEG0-CSEG59 VM4 – 0.2 VM4 VM4 + 0.2 High Output ROH1 VO = VDD–0.5V SEG0-SEG59 – – 90 Impedance ROH2 COM0-COM8 – – 25 Low Output ROL1 SEG0-SEG59 – – 90 Resistor ROL2 SEG0-SEG15 (key strobe) – – 2 ROL3 COM0-COM8 – – 25 VO = 0.5V V KΩ kΩ 13–3 ELECTRICAL DATA KS57C21408/C21418/P21408 Table 13-2. D.C Characteristics (continued) (TA = – 40 °C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (2) (3) Symbol IDD1 IDD2 Conditions Typ. Max. Units – 5.1 8 mA Run mode : VDD = 5 V ± 10% 6MHz Crystal oscillator C1 = C2 = 22pF 4.19MHz 3.8 6 VDD = 3 V ± 10% 6MHz 2.5 4 4.19MHz 1.8 3 Idle mode : VDD = 5 V ± 10% 6MHz 1.3 2.5 Crystal oscillator C1 = C2 = 22pF 4.19MHz 1.1 1.8 VDD = 3 V ± 10% 6MHz 0.5 1.5 4.19MHz 0.4 1.0 – 30 45 – 17 30 6 15 2.4 5 0.6 3 IDD3 Run mode: VDD = 3 V ± 10% 32kHz crystal oscillator IDD4 Idle mode: VDD = 3 V ± 10% 32kHz crystal oscillator LCD ON (4) VDD = 3 V ± 10% 32kHz crystal oscillator LCD OFF IDD5 Min. Stop mode; VDD = 5 V ± 10%, XTIN = 0V Stop mode; VDD = 3 V ± 10%, XTIN = 0V – NOTES: 1. VM1=2.75/3.75 VDD, VM2=1/3.75 VDD, VM3=2/3.75 VDD, VM4=1.75/3.75 VDD 2. 3. 4. Supply current does not include current drawn through internal pull-down resistor and LCD driving resistors. For D.C. electrical voltages, PCON register must be set to 0011B. The mode of IDD4 (LCD ON) is normal. 13–4 µA KS57C21408/C21418/P21408 ELECTRICAL DATA Table 13-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Parameter Test Condition Min Typ Max Units – 0.4 – 6.0 MHz After VDD reaches the minimum level of its variable range – – 4 ms – 0.4 – 6 MHz VDD = 4.5 V to 5.5 V – – 10 ms VDD = 1.8 V to 5.5 V – – 60 Xin input frequency(fx) (1) – 0.4 – 6 MHz Xin input high and low level width (tXH, tXL) – 83.3 – 1250 ns VDD = 5 V – 2 – MHz VDD = 3 V – 1 – Oscillation frequency(fx) (1) C2 Stabilization time (2) Crystal Oscillator XOUT XIN C1 Oscillation frequency(fx) (1) C2 Stabilization time (2) External Clock RC Oscillator XIN XOUT XIN XOUT Frequency R NOTES: 1. Oscillation frequency and input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on or release of STOP mode. 13–5 ELECTRICAL DATA KS57C21408/C21418/P21408 Table 13-4. Recommended Oscillator Constants (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Manufacturer TDK Series Number (1) Frequency Range Oscillator Voltage Range (V) C1 C2 MIN MAX Remarks M5 3.58 MHz–6.0 MHz 33 33 2.0 5.5 Leaded Type FCR MC5 3.58 MHz–6.0 MHz (2) (2) 2.0 5.5 On-chip C Leaded Type CCR MC3 3.58 MHz–6.0 MHz (3) (3) 2.0 5.5 On-chip C SMD Type FCR NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. 13–6 Load Cap (pF) KS57C21408/C21418/P21408 ELECTRICAL DATA Table 13-5. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal Oscillator XTIN XTOUT Oscillation frequency (1) – 32 32.768 35 kHz VDD = 4.5 V to 5.5 V – 1.0 2 ms VDD = 1.8 V to 5.5 V – – 10 XTin input frequency (1) – 32 – 100 kHz XTin input high and low level width (tXTH, tXTL) – 5 – 15 µs C1 C2 Stabilization time (2) External Clock XTIN XTOUT NOTES: 1. Oscillation frequency and input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on or release of STOP mode. Table 13-6. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT – – 15 pF I/O Capacitance CIO – – 15 pF 13–7 ELECTRICAL DATA KS57C21408/C21418/P21408 Table 13-7. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (NOTE) TCL0 Input Frequency Symbol tCY f TI Conditions Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 With sub-system clock (fxt) 114 122 1952 0 – 1.5 MHz 1 kHz – – µs – – µs – – µs VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 Input High, Low Width External Interrupt Input High, Low Width RESET Low Level tTIH tTIL tINTH, tINTL tRSL VDD = 2.7 V to 5.5 V 0.48 VDD = 1.8 V to 5.5 V 1.8 INT0, INT1, KS0 - KS7 10 KS0 - KS3 10 – 10 Width NOTE: Unless otherwise specified, the values of instruction cycle time condition assume a main-system clock (fx) source. 13–8 KS57C21408/C21418/P21408 ELECTRICAL DATA Main Oscillator Frequency CPU Clock 1.5 MHz 6 MHz 0.75 MHz 3 MHz 400 kHz 15.625 kHz 1 2 1.8 V 3 4 5 6 7 Supply Voltage(V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) Figure 13-1. Standard Operating Voltage Range Table 13-8. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 1.8 – 5.5 V Data retention supply current IDDDR – 0.1 10 µA Release signal set time tSREL – – µs – ms Oscillator stabilization wait time (1) tWAIT VDDDR = 1.8 V – 0 Released by RESET – Released by interrupt – 17 2 / fx (2) – NOTES: 1. During oscillator stabilization time, all CPU operations are stopped to avoid unstable operation upon oscillation start. 2. The basic timer mode register (BMOD) interval timer delays execution of CPU instructions during the wait time. 13–9 ELECTRICAL DATA KS57C21408/C21418/P21408 TIMING WAVEFORMS INTERNAL RESET OPERATION IDLE MODE OPERATING MODE STOP MODE DATA RETENTION MODE VDD EXECUTION OF STOP INSTRUCTION VDDDR RESET tWAIT tSREL Figure 13-2. Stop Mode Release Timing When Initiated By RESET IDLE MODE NORMAL OPERATING MODE STOP MODE DATA RETENTION MODE VDD EXECUTION OF STOP INSTRUCTION VDDDR POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) tSREL t WAIT Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request 13–10 KS57C21408/C21418/P21408 ELECTRICAL DATA 0.8 VDD 0.2 VDD 0.8 VDD MEASUREMENT POINTS 0.2 VDD Figure 13-4. A.C. Timing Measurement Points (Except for Xin and XTin) 1 / fx (1 / fXT) tXL (t XTL) tXH ( t XTH) Xin (XTin) VDD – 0.5 V 0.4 V Figure 13-5. Clock Timing Measurement at Xin and XTin 13–11 ELECTRICAL DATA KS57C21408/C21418/P21408 1 / f TI t TIL tTIH 0.8 VDD TCL0 0.2 VDD Figure 13-6. TCL0 Timing tRSL RESET 0.2 VDD Figure 13-7. Input Timing for RESET Signal t INTL INT0, 1 INTP0 KS0 to KS7 t INTH 0.8 VDD 0.2 VDD Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts 13–12 KS57C21408/C21418/P21408 14 MECHANICAL DATA MECHANICAL DATA OVERVIEW This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram — Pad/pin coordinate data table 23.90 ± 0.3 0-8 14.00 ± 0.2 0.15 #1 0.65 0.80 ± 0.20 #100 0.3 ± 0.1 +0.10 -0.05 0.10 MAX 100-QFP-1420C (0.83) 17.90 ± 0.3 20.00 ± 0.2 (0.58) 0.05 MIN 0.10 MAX 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 14-1. 100-QFP-1420 Package Dimensions 14-1 MECHANICAL DATA KS57C21408/C21418/P21408 NOTES 14-2 KS57C21408/C21418/P21408 15 KS57P21408 OTP KS57P21408 OTP OVERVIEW The KS57P21408 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C21408/C21418 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS57P21408 is fully compatible with the KS57C21408/C21418, both in function and in pin configuration. Because of its simple programming requirements, the KS57P21408 is ideal for use as an evaluation chip for the KS57C21408/C21418. 15-1 KS57P21408 OTP KS57C21408/C21418/P21408 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG59 COM4 COM5 COM6 COM7 COM8 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 P7.0/KS4 P7.1/KS5 SDAT/P7.2/KS6 SCLK/P7.3/KS7 VDD /VDD VSS/VSS Xout Xin VPP/TEST XTin XTout RESET / RESET P2.0/BUZ P2.1/CLO P5.0 P5.1 P5.2 P5.3 TCL0/P4.0 TCLO0/P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 KS57P21408 100-QFP 1420C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG8/P8.8 SEG7/P8.7 SEG6/P8.6 SEG5/P8.5 SEG4/P8.4 SEG3/P8.3 SEG2/P8.2 SEG1/P8.1 SEG0/P8.0 COM3 COM2 COM1 COM0 INT0/P1.0 INT1/P1.1 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P4.2 Figure 15-1. KS57P21408 Pin Assignments (100-QFP Package) 15-2 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15/P8.15 SEG14/P8.14 SEG13/P8.13 SEG12/P8.12 SEG11/P8.11 SEG10/P8.10 SEG9/P8.9 KS57C21408/C21418/P21408 KS57P21408 OTP Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P3.1 SDAT 13 I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. P3.0 SCLK 14 I/O Serial clock pin. Input only pin. TEST VPP(TEST) 19 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 22 I Chip initialization VDD / VSS VDD / VSS 15/16 I Logic power supply pin. VDD should be tied to +5 V during programming. Table 15-2. Comparison of KS57P21408 and KS57C21408/C21418 Features Characteristic KS57P21408 KS57C21408 Program Memory 8 Kbyte EPROM 8 Kbyte mask ROM Operating Voltage (VDD) 1.8 V to 5.5 V 1.8 V to 5.5V OTP Programming Mode VDD = 5 V, VPP(TEST)=12.5V Pin Configuration 100 QFP 100 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the KS57P21408, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD 5V REG/ MEM ADDRESS (TEST) 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection VPP R/W MODE (A15-A0) NOTE: "0" means Low level; "1" means High level. 15-3 KS57P21408 OTP KS57C21408/C21418/P21408 Table 15-4. D.C Characteristics (TA = –40 °C to +85C, VDD = 1.8 V to 5.5V) Parameter Supply Current (2)(3) Symbol IDD1 IDD2 Conditions Typ. Max. Units – 5.1 8 mA Run mode : VDD=5V±10% 6MHz Crystal oscillator C1=C2=22pF 4.19MHz 3.8 6 VDD=3V±10% 6MHz 2.5 4 4.19MHz 1.8 3 Idle mode : VDD=5V±10% 6MHz 1.3 2.5 Crystal oscillator C1=C2=22pF 4.19MHz 1.1 1.8 VDD=3V±10% 6MHz 0.5 1.5 4.19MHz 0.4 1.0 – 30 45 – 17 30 6 15 2.4 5 0.6 3 IDD3 Run mode : VDD=3V±10% 32kHz crystal oscillator IDD4 Idle mode : VDD=3V±10% 32kHz crystal oscillator LCD ON(4) VDD=3V±10% 32kHz crystal oscillator LCD OFF IDD5 Min. Stop mode; VDD=5V±10% Stop mode; VDD=3V±10% – NOTES: 1. VM1=2.75/3.75 VDD, VM2=1/3.75 VDD, VM3=2/3.75 VDD, VM4=1.75/3.75 VDD 2. Supply current does not include current drawn through internal pull-down resistor and LCD driving resistors. 3. For D.C. electrical voltages, PCON register must be set to 0011B. 5. The mode of IDD4 (LCD ON) is normal. 15-4 µA KS57C21408/C21418/P21408 KS57P21408 OTP Main Oscillator Frequency CPU Clock 1.5 MHz 6 MHz 0.75 MHz 3 MHz 400 kHz 15.625 kHz 1 2 1.8 V 3 4 5 6 7 Supply Voltage(V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) Figure 15-2. Standard Operating Voltage Range 15-5 KS57P21408 OTP KS57C21408/C21418/P21408 NOTES 15-6