S3C72H8/P72H8 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsung's state-of-the-art 4-bit product development approach, SAM47 (Samsung Arrangeable Microcontrollers). Its main features are an up-to-13-digit LCD direct drive capability, 2-channel comparator inputs and outputs, and versatile 8-counter/ timers and 16-bit frequency counter. The S3C72H8 gives you an excellent design solution for a variety of LCD-related applications, specially thermostat control application. Up to 21 pins of the available 64-pin QFP packages can be dedicated to I/O. And six vectored interrupts provide fast response to internal and external events. In addition, the S3C72H8's advanced CMOS technology provides for low power consumption and a wide operating voltage range. 1-1 PRODUCT OVERVIEW S3C72H8/P72H8 FEATURES Architecture LCD Controller/Driver – – 26 segment and 4 common terminals – Maximum 13-digit LCD direct drive capability SAM47 4-bit CPU core Memory – Data Memory: 512 × 4 bits – Display modes: Static, 1/2, 1/3, 1/4 duty – Program Memory: 8196 × 8 bits (Including LCD display RAM) – Voltage regulator and booster (1/3 bias: 1, 2, or 3V, 1/2 bias: 1.5, 3V) Memory-Mapped I/O Structure – Data memory bank 15 Interrupts – Three internal vectored interrupts – Three external vectored interrupts – Two quasi-interrupts 8-Bit Timer/Counter (T0) – Programmable 8-bit timer – External event counter – Arbitrary clock frequency output – External clock signal divider 16-Bit Frequency Counter (FC) – a 16-bit binary up-counter – External event counter – Gate function control Analog Comparator – 2 Ch Comparator (Each CnP, CnN, CnOUT pins) Bit Sequential Carrier – Support 16-bit serial data transfer in arbitrary format I/O Ports – 21 pins for standard I/O – 26 pins for LCD segment output – 4 pins for LCD common output – Two input pins for external interrupts Oscillation Sources – Crystal, ceramic, or RC for main system clock – Crystal or external oscillator for subsystem clock – Main system clock frequency: 4.19 MHz (typical) – Subsystem clock frequency: 32.768 kHz – CPU clock divider circuit (by 4, 8, or 64 main, and by 4 for sub clock) Watch-Dog TIMER and Basic Timer – 8-bit counter + 3-bit counter Power Down Mode – Overflow signal of 8-bit counter makes a basic timer interrupt. And control the oscillation warmup time – Idle mode (only CPU clock stops) – Stop mode (main or sub-system oscillation stops) Overflow signal of 3-bit counter makes a system reset Voltage Level Detector – Watch Timer – Real-time and interval time measurement – Four frequency outputs to buzzer sound – Clock source generation for LCD – VDD level detection circuit (2.2, 2.4, 3, or 4.0V) – External pin level detect mode Operating Voltage Range – 1.8V to 5.5V at 3 MHz – 2.0V to 5.5V at 4.19 MHz Package Type – 1-2 64-pin QFP S3C72H8/P72H8 PRODUCT OVERVIEW BLOCK DIAGRAM SCLK VPP/ TEST XIN XTIN INT0, INT1 RESET XOUT XTOUT P0.0/ExtRef P0.1/SDAT P0.2/SCLK I/O Port 2 P3.0/TCLO0 P3.1/BTCO P3.2/CLO P3.3/BUZ I/O Port 3 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 Watch Timer I/O Port 0 P2.0/INT0 P2.1/INT1 P2.2/TCL0 P2.3/FCL P4.0/C0P P4.1/C0N P4.2/C0OUT P4.3/C1OUT P5.0/C1P P5.1/C1N SDAT Interrupt Control Block Clock OTP Block Internal Interrupts Instruction Decoder Instruction Register Basic Timer Program Counter 16-Bit FREQ Counter FCL C0OUT C1OUT Program Status Word 8-Bit Timer TCL0 I/O Port 4,5 LCD Driver/ Controller Arithmetic and Logic Unit Stack Pointer Voltage Booster I/O Port 6 512 x 4-Bit Data Memory 8 K Byte Program Memory Voltage Level Detector ExtRef Watchdog Timer TCLO0 COM0-COM3 SEG0-SEG25 CA, CB VLC0-VLC2 Two Analog Comparator CnP CnN CnOUT Figure 1-1. S3C72H8 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C72H8/P72H8 64 63 62 61 60 59 58 57 56 55 54 53 52 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 PIN ASSIGNMENTS CA CB S3C72H8 (TOP VIEW) 51 50 43 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P2.3/FCL P3.0/TCLO0 P3.1/BTCO P3.2/CLO P3.3/BUZ P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 P4.0/C0P P4.1/C0N P4.2/C0OUT P4.3PC1OUT 20 21 22 23 24 25 26 27 28 29 30 31 32 VLC0 VLC1 VLC2 P0.0/ExtRef SDAT/P0.1 SCLK/P0.2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P2.0/INT0 P2.1/INT1 P2.2/TCL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Figure 1-2. S3C72H8 Pin Assignment Diagram 1-4 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 P5.1/C1N P5.0/C1P S3C72H8/P72H8 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C72H8 Pin Descriptions Pin Name Pin Type Description Number (64-QFP) Share Pin Circuit Type P0.0 P0.1 P0.2 I/O 3-bit I/O port. 1-bit and 4-bit read/write and test is possible. Port 0 is software configurable as input or output. 3-bit pull-up resistors are software assignable. 6 7 8 ExtRef – – D-1 P2.0 P2.1 P2.2 P2.3 I/O 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable. 17 18 19 20 INT0 INT1 TCL0 FCL D-1 P3.0 P3.1 P3.2 P3.3 I/O Same as port 2. Ports 2 and 3 can be addressed by 1, 4, and 8-bit read/write and test instruction. 21 22 23 24 TCLO0 BTCO CLO BUZ D-1 P4.0-P4.3 I/O 4/2-bit I/O ports. N-channel open-drain or push-pull output. 1, 4, and 8-bit read/write and test is possible. Ports 4 and 5 can be paired to support 8-bit data transfer. Pull-up resistors are assignable to port unit by software control. 29-32 C0P/ C0N/ C0OUT/ C1OUT C1P/ C1N E-1 25-28 KS0-KS3 D-1 P5.0-P5.1 33-34 P6.0-P6.3 I/O 4-bit I/O ports. Port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. BTCO I/O Basic timer clock output 22 P3.1 D-1 CLO I/O CPU clock output 23 P3.2 D-1 BUZ I/O 2, 4, 8 or 16 kHz frequency output for buzzer sound with 4.19MHz main-system clock or 32.768 kHz sub-system clock. 24 P3.3 D-1 XOUT, XIN – Crystal, ceramic, or RC oscillator signal for mainsystem clock. (For external clock input, use XIN and input XIN’s reverse phase to XOUT) 11, 12 – – XTOUT, XTIN – Crystal oscillator signal for sub-system clock. (For external clock input, use XTIN and input XTIN’s reverse phase to XTOUT) 14, 15 – – I/O External interrupts. The triggering edge for INT0 and Int1 is selectable. Only INT0 is synchronized with the system clock. 17, 18 P2.0, P2.1 D-1 INT0, INT1 1-5 PRODUCT OVERVIEW S3C72H8/P72H8 Table 1-1. S3C72H8 Pin Descriptions (Continued) Pin Name Pin Type Description Number (64-QFP) Share Pin Circuit Type 25-28 P6.0-P6.3 D-1 KS0-KS3 I/O Quasi-interrupt input with falling edge detection ExtRef I/O External Reference input 6 P0.0 D-1 TCL0 I/O External clock input for timer/counter 0 19 P2.2 D-1 FCL I/O External clock input for frequency counter 20 P2.3 D-1 TCLO0 I/O Timer/counter 0 clock output 21 P3.0 D-1 COM0-COM3 O LCD common signal output 61-64 – H-16 SEG0-SEG25 O LCD segment output 35-60 – H-16 CA, CB – Voltage booster capacitor pins 1, 2 – – VLC0-VLC2 – Voltage booster output pins (VLC0 is the regulated output, VLC1 is the 2* VLC0 output, VLC2 is the 3* VLC0 output) 3-5 – – C0P, C0N, C0OUT I/O Comparator 0 non-inverting input, inverting input and output. C0Out can be configured as C-MOS push-pull or N-Ch open drain output 29-31 P4.0-P4.2 – C1P, C1N, C1OUT I/O I Comparator 1 non-inverting input, inverting input and output. C1Out can be configured as C-MOS push-pull or N-Ch open drain output 32-34 P4.3-P5.1 – RESET – Reset signal for chip initialization 16 – B VDD – Main power supply 9 – – VSS – Ground 10 – – TEST – Test signal input (must be connected to VSS) 13 VPP – SDAT I/O Serial data for OTP programming 7 P0.1 SCLK I/O Serial clock for OTP programming 8 P0.2 Power supply pin for EPROM cell writing 13 TEST VPP – NOTE: Pull-up resistors for ports 0, 2, 3, and 6 are automatically disabled if they are configured to output mode. But pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode. 1-6 S3C72H8/P72H8 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD P-Channel In N-Channel In Figure 1-4. Pin Circuit Type B (Reset) Figure 1-3. Pin Circuit Type A VDD VDD Data Pull-up Resistor P-Channel Out Output Disable N-Channel Resistor Enable Data Output Disable P-Cannel Circuit Type C I/O Input Disable Figure 1-5. Pin Circuit Type C Figure 1-6. Pin Circuit Type D-1 (P0, P2, P3, P6) 1-7 PRODUCT OVERVIEW S3C72H8/P72H8 VDD PNE VDD Pull-up Enable Data In/Out Output Disable Input Disable To Data Bus To Comparator Figure 1-7. Pin Circuit Type E-1 (P4, P5) VLC2 VLC1 SEG/COM DATA Out VLC0 Figure 1-8. Pin Circuit Type H-16 (COM/SEG) 1-8 S3C72H8/P72H8 16 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on S3C72H8 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics — Subsystem clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at XIN — Clock timing measurement at XTIN — TCL timing — Input timing for RESET — Input timing for external interrupts Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 16-1 ELECTRICAL DATA S3C72H8/P72H8 Table 16-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol VDD Conditions – – 0.3 to + 6.5 Input Voltage VIN – – 0.3 to VDD + 0.3 Output Voltage VO All I/O ports – 0.3 to VDD + 0.3 Output Current High I OH One I/O pin active –7 mA Output Current Low I OL All I/O ports active One I/O pin active – 40 + 15 mA Total pin circuit Operating Temperature TA – + 60 – 40 to + 85 °C TSTG – – 65 to + 150 Supply Voltage Storage Temperature Rating Units V Table 16-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input High VIH1 Conditions FOSC = 6 MHz (CPU clock = 1.25 MHz) FOSC = 4.19 MHz (Instruction clock = 1.04 MHz) FOSC = 3 MHz (CPU clock = 0.75 MHz) P0, P2, P3, P4, P5 and P6 voltage VIH2 RESET 0.85 VDD VDD VIH3 XIN VDD-0.1 VDD Input low VIL1 P0, P2, P3, P4, P5 and P6 voltage VIL2 RESET VIL3 XIN VOH1 VDD = 5.0V IOH = – 1 mA All output pins IOH = – 100 µA Operation voltage Output high voltage Output low voltage 16-2 Symbol VDD VOL1 VDD = 5.0 V, IOL = 2 mA All output pins except VOL2 VOL2 VDD = 5.0 V, IOL = 15 mA Ports 2,3, and 4 Min Typ Max Units 2.7 – 5.5 V 2.0 5.5 1.8 5.5 0.8 VDD – – VDD 0.2 VDD 0.3 VDD 0.1 VDD – 1.0 – – 0.4 0.5 0.4 1.0 VDD – 0.5 – V S3C72H8/P72H8 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high leakage current (note) Symbol ILIH1 Conditions Min Typ Max Units VIN = VDD All input pins – – 3 µA VIN = VDD; All input pins – – –3 Input low leakage current (note) ILIL1 Output high leakage current (note) ILOH VOUT = VDD All I/O pins and output pins – – 3 Output low leakage current (note) ILOL VOUT = 0 V All I/O pins and output pins – – –3 Pull-up resistors RL1 VIN = 0 V, VDD = 5 V 25 47 100 VDD = 3 V 50 90 150 VIN = 0 V; VDD = 5.0 V 150 250 350 except RESET KΩ TA = 25 °C, Ports 0-6 RL2 TA = 25 °C, RESET ROSC1 VDD = 5.0 V, TA = 25 °C XIN = VDD, XOUT = 0V 400 700 1200 ROSC2 VDD = 5.0 V, TA = 25 °C XTIN = VDD, XTOUT = 0V 1000 1500 3000 |VLC1-COMi| Voltage Drop (I = 0-3) VDC -15 uA per common pin – – 120 |VLC1-SEGi| Voltage Drop (I = 0-25) VDS -15 uA per segment pin – – 120 Oscillator feed back resistors mV NOTE: Except XIN, XOUT, XTIN, XTOUT 16-3 ELECTRICAL DATA S3C72H8/P72H8 Table 16-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (note) Symbol IDD1 IDD2 Conditions Min Typ Max Units – 3.5 8 mA VDD = 5 V ± 10%, 4.19 MHz 2.5 5.5 VDD = 3 V ± 10%, 6-MHz crystal 1.6 4 VDD = 3 V ± 10%, 4.19 MHz 1.2 3 1.8 3.5 VDD = 5 V ± 10%, 4.19 MHz 1.4 3.0 VDD = 3 V ± 10%, 6-MHz crystal 0.6 1.2 VDD = 3 V ± 10%, 4.19 MHz 0.5 1.1 Main operation mode: VDD = 5 V ± 10%, 6-MHz crystal Main Idle mode: VDD = 5 V ± 10%, 6-MHz crystal – IDD3 Sub operation mode: VDD = 3 V, 32768Hz Main OSC stop, except IVB, IVLD, Icomp, ILCD and external load. – 15 30 IDD4 Sub Idle mode; VDD = 3.0, 32768Hz Main OSC stop, except IVB, IVLD, Icomp, ILCD and external load. – 6 15 IDD5 Stop mode; Main & Sub SCMOD = OSC stop, VDD=5 V ± 10% 0100B except IVD, IVLD, Icomp and XTIN = 0Vexternal load. Stop & Sub OSC stop, VDD = 3 V, except IVD, IVLD, Lcomp and external load. – 0.3 3 0.1 1 uA uA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. ILCD is LCD controller/driver operating current, IVB is voltage booster current, Icomp is comparator current and IVLD is voltage level detector current. Table 16-3. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current 16-4 Symbol VDDDR IDDDR Conditions VDDDR = 1.0 V Stop mode; Main & Sub OSC stop. except IVB, IVLD, ILCD and external load. Min Typ Max Unit 1.0 - 5.5 V - - 1 uA S3C72H8/P72H8 ELECTRICAL DATA Table 16-4. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Parameter Oscillation frequency (1) XIN Oscillation frequency (1) XOUT C1 RC Oscillator XIN XIN Typ Max Units – 0.4 – 6.0 MHz Stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 4 ms – 0.4 – 6 MHz VDD = 4.5 V to 5.5 V – – 10 ms VDD = 2.0 V to 4.5 V – – 30 C2 Stabilization time (2) External Clock Min C2 Stabilization time (2) Crystal Oscillator Test Condition XOUT XOUT R XIN input frequency (1) – 0.4 – 6.0 MHz XIN input high and low level width (tXH, tXL) – 83.3 – – ns 0.4 – 2.0 1.0 2.5 MHz Frequency (1) VDD = 5 V R = 25 K, VDD = 5 V R = 50 K, VDD = 3 V NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 16-5 ELECTRICAL DATA S3C72H8/P72H8 Table 16-5. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Clock Configuration Crystal Oscillator XT IN XT OUT C1 Parameter Test Condition Min Typ Max Units Oscillation frequency (1) – 32 32.768 35 kHz VDD = 4.5 V to 5.5 V – 1.0 2 s VDD = 1.8 V to 4.5 V – – 10 XTIN input frequency (1) – 32 – 100 kHz XTIN input high and low level width (tXTL, tXTH) – 5 – 15 us C2 Stabilization time (2) External Clock XT IN XT OUT NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs. Table 16-6. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle Symbol tCY time (1) TCL0, FCL input fTI0, fTI0 Conditions Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 – 64 VDD = 2.7 V to 5.5 V 0 – 1.5 VDD = 1.8 V to 5.5V frequency 1 TCL0, FCL input tTIH0, tTIL0 VDD = 2.7 V to 5.5 V 150 high, low width tFCH, tFCL VDD = 1.8 V to 5.5 V 250 Interrupt input tINTH, INT0 (2) high, low width tINTL INT1, INT2 (KS0-KS3) 10 RESET Input Low tRSL Input 10 – – ns – – µs – – µs Width NOTES 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting. 16-6 MHz S3C72H8/P72H8 ELECTRICAL DATA CPU Clock Main OSC Frequency 1.5 MHz 6 MHz 1.05 MHz 4.19 MHz 750 kHz 3 MHz 15.625 kHz 1 2 1.8 V 3 4 5 2.7 V 6 7 5.5 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8, 64) Figure 16-1. Standard Operating Voltage Range 0.8 VDD 0.8 VDD Measurement Points 0.2 VDD 0.2 VDD Figure 16-2. A.C Timing Measure Pints (Except for XIN and XTIN) 16-7 ELECTRICAL DATA S3C72H8/P72H8 Internal RESET Operation ~ ~ Idle Mode Stop Mode Operationg Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction RESET tWAIT tSREL Figure 16-3. Stop Mode Release Timing When Initiated By RESET Idle Mode ~ ~ Normal Operating Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 16-4.Stop Release Timing When Initiated By Interrupt Request 1/fx tXL tXH XIN VDD - 0.5 V 0.4 V Figure 16-5. Clock Timing Measurement at XIN 16-8 S3C72H8/P72H8 ELECTRICAL DATA 1/fxt tXTL tXTH XTIN VDD - 0.5 V 0.4 V Figure 16-6. Clock Timing Measurement at XTIN tRSL RESET 0.2 VDD Figure 16-7. Input Timing for RESET Signal tINTL INT0, 1 KS0 to KS3 tINTH 0.8 VDD 0.2 VDD Figure 16-8. Input Timing External Interrupt 16-9 S3C72H8/P72H8 MECHANICAL DATA 17 MECHANICAL DATA OVERVIEW The S3C72H8/P72H8 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F) Package dimensions are shown in Figure 17-1 23.90 ± 0.3 0-8 14.00 ± 0.2 ± 0.2 0.15 64-QFP-1420F 0.80 ± 0.20 #64 #1 1.00 0.40+0.10 -0.05 +0.10 -0.05 0.10 MAX (1.00) 17.90 ± 0.3 20.00 (1.00) 0.05-0.25 0.15 MAX 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 17-1. 64-QFP-1420F Package Dimensions 17-1 S3C72H8/P72H8 18 S3P72H8 OTP S3P72H8 OTP OVERVIEW The S3P72H8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72H8 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The S3P72H8 is fully compatible with the S3C72H8, both in function and in pin configuration. Because of its simple programming requirements, the S3P72H8 is ideal for use as an evaluation chip for the S3C72H8. 18-1 S3C72H8/P72H8 64 63 62 61 60 59 58 57 56 55 54 53 52 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 S3P72H8 OTP CA CB S3P72H8 (TOP VIEW) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FCL/P2.3 TCLO0/P3.0 BTCO/P3.1 CLO/P3.2 BUZ/P3.3 KS0/P6.0 KS1/P6.1 KS2/P6.2 KS3/P6.3 C0P/P4.0 C0N/P4.1 C0OUT/P4.2 C1OUT/P4.3 20 21 22 23 24 25 26 27 28 29 30 31 32 VLC0 VLC1 VLC2 P0.0/ExtRef SDAT/P0.1 SCLK/P0.2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P2.0/INT0 P2.1/INT1 P2.2/TCL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Figure 18-1. S3P72H8 Pin Assignments 18-2 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 P5.1/C1N P5.0/C1P S3C72H8/P72H8 S3P72H8 OTP Table 18-1. Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P0.1 SDAT 7 I/O Serial data pin. Output port when reading and input port when writing can be assigned as Input/push-pull output port respectively. P0.2 SCLK 8 I/O Serial clock pin. Input only pin. TEST VPP (TEST) 13 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 16 I Chip initialization VDD / VSS VDD / VSS 9/10 I Logic power supply pin. VDD should be tied to + 5 V during programming. Table 18-2. Comparison of S3P72H8 and S3C72H8 Features Characteristic S3P72H8 S3C72H8 Program Memory 8 K-byte EPROM 8 K-byte mask ROM Operating Voltage (VDD) 1.8 V to 5.5 V 1.8 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 64 QFP 64 QFP EPROM Programmability User Program 1 time Programmed at the factory – OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P72H8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 18-3 below. Table 18-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/ MEM Address (A15-A0) R/W W 5V 5V 0 0000H 1 EPROM read 12.5V 0 0000H 0 EPROM program 12.5V 0 0000H 1 EPROM verify 12.5V 1 0E3FH 0 EPROM read protection Mode NOTE: "0" means low level; "1" means high level. 18-3 S3P72H8 OTP S3C72H8/P72H8 Table 18-4. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (note) Symbol IDD1 IDD2 Conditions Main operation mode: VDD = 5 V ± 10%, 6-MHz crystal VDD = 5 V ± 10%, 4.19 MHz Typ 3.5 Max 8 2.5 5.5 VDD = 3 V ± 10%, 6-MHz crystal 1.6 4 VDD = 3 V ± 10%, 4.19 MHz 1.2 3 1.8 3.5 1.4 3.0 VDD = 3 V ± 10%, 6-MHz crystal 0.6 1.2 VDD = 3 V ± 10%, 4.19 MHz 0.5 1.1 Main Idle mode: VDD = 5 V ± 10%, 6-MHz crystal VDD = 5 V ± 10%, 4.19 MHz Min – – IDD3 Sub operation mode: VDD = 3 V, 32768Hz Main OSC stop, except IVB, IVLD, Icomp, ILCD and external load. – 15 30 IDD4 Sub Idle mode; VDD = 3.0, 32768Hz Main OSC stop, except IVB, IVLD, Icomp, ILCD and external load. – 6 15 IDD5 Stop mode; Main & Sub SCMOD = OSC stop, VDD=5 V ± 10% 0100B except IVD, IVLD, Icomp and XTIN = 0Vexternal load. Stop & Sub OSC stop, VDD = 3 V, except IVD, IVLD, Lcomp and external load. – 0.3 3 0.1 1 Units mA uA uA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. ILCD is LCD controller/driver operating current, IVB is voltage booster current, Icomp is comparator current, and IVLD is voltage level detector current. 18-4 S3C72H8/P72H8 S3P72H8 OTP CPU Clock Main OSC Frequency 1.5 MHz 6 MHz 1.05 MHz 4.19 MHz 750 kHz 3 MHz 15.625 kHz 1 2 1.8 V 3 4 2.7 V 5 6 7 5.5 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8, 64) Figure 18-2. Standard Operating Voltage Range 18-5 S3P72H8 OTP S3C72H8/P72H8 START Address= First Location VDD =5V, V PP=12.5V x=0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte Last Address FAIL NO VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 18-3. OTP Programming Algorithm 18-6 Increment Address