SAMSUNG KS57C2504

KS57C2504
4-BIT CMOS Microcontroller
Product Specification
OVERVIEW
The S3C7254 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM4 (Samsung Arrangeable Microcontrollers).With a two-channel comparator, up-to320-dot LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7254 offers an excellent design
solution for a wide variety of applications which require LCD functions.
Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast response
to internal and external events. In addition, the S3C7254's advanced CMOS technology provides for low power
consumption and a wide operating voltage range.
FEATURES
Memory
8-Bit Timer/Counter
•
512 × 4-bit RAM
•
Programmable 8-bit timer
•
4096 × 8-bit ROM
•
External event counter
•
Arbitrary clock frequency
output
27 I/O Pins
•
I/O: 15 pins
•
External clock signal divider
•
Input only: 4 pins
•
•
Output only: 8 pins
Serial I/O interface clock
generator
Comparator
•
Two-channel mode: internal
reference (4-bit resolution)
•
One-channel mode: external
reference
Watch Timer
•
Time interval generation:
0.5 s, 3.9 ms at 32768 Hz
•
Four frequency outputs to
BUZ pin
•
Clock source generation for
LCD
LCD Controller/Driver
•
40 segments and 8 common
terminals
•
3, 4 and 8 common
selectable
8-Bit Serial I/O Interface
Four external vectored
interrupts
•
Two quasi-interrupts
Bit Sequential Carrier
•
Supports 16-bit serial data
transfer in arbitrary format
Memory-Mapped I/O Structure
•
Data memory bank 15
Two Power-Down Modes
•
Idle mode (only CPU clock
stops)
•
Stop mode (main system
oscillation stops)
Oscillation Sources
•
Crystal, ceramic, or RC for
main system clock
8-bit receive only mode
•
Crystal oscillator for
subsystem clock
•
Main system clock
frequency: 4.19 MHz
(typical)
•
Subsystem clock frequency:
32.768 kHz
•
CPU clock divider circuit (by
4, 8, or 64)
•
8-bit transmit/receive mode
•
•
Internal resistor circuit for
LCD bias
•
LSB-first or MSB-first
transmission selectable
•
All dot can be switched
on/off
•
Internal or external clock
source
8-Bit Basic Timer
Interrupts
•
•
4 interval timer functions
•
Three internal vectored
interrupts
4–1
PRODUCT SPECIFICATION
S3C7254
Instruction Execution Times
Operating Temperature
•
0.95, 1.91, 15.3 µs at 4.19
MHz
•
•
122 µs at 32.768 kHz
Operating Voltage Range
•
Package Type
– 40 °C to 85 °C
•
2.7 V to 6.0 V
RESET
XIN
XOUT
XTIN
XTOUT
BASIC
TIMER
WATCH
TIMER
INTERRUPT
CONTROL
BLOCK
CLOCK
SIO
P0.0 / SCK / K0
P0.1 / SO / K1
P0.2 / SI / K2
P0.3 / BUZ / K3
INTERNAL
INTERRUPTS
I/O PORT 0
COMPARATOR
P1.0 / INT0 / CIN0
P1.1 / INT1 / CIN1
P1.2 / INT2
P1.3 / INT4
INSTRUCTION DECODER
ARITHMETIC
LOGIC UNIT
STACK
POINTER
PROGRAM
COUNTER
LCD
DRIVER/
CONTROLLER
FLAGS
4-KB
PROGRAM
MEMORY
Figure 1. S3C7254 Simplified Block Diagram
VLC1–VLC5
COM0–COM7
SEG0–SEG31
P5.0/SEG32–
P5.7/SEG39
I/O PORT 2
P2.0–P2.3
I/O PORT 3
P3.0
P3.1
P3.2 / LCDSY
P3.3 / LCDCK
I/O PORT 4
P4.0/CLO
P4.1/TCL0
P4.2/TCLO0
PROGRAM
STATUS WORD
INPUT
PORT 1
512 x 4-BIT
DATA
MEMORY
4–2
80-pin QFP
8-BIT
TIMER/
COUNTER
PRODUCT SPECIFICATION
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
S3C7254
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3C7254
KS57C2504
(TOP VIEW)
(TOP VIEW)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
XTOUT
XTIN
XIN
XOUT
VDD
TEST
RESET
P4.2 / TCLO0
P4.1 / TCL0
P4.0 / CLO
P0.0 / SCK / K0
P0.1 / SO / K1
P0.2 / SI / K2
P0.3 / BUZ / K3
P1.0 / INT0 / CIN0
P1.1 / INT1 / CIN1
P1.2 / INT2
P1.3 / INT4
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
LCDSY / P3.2
LCDCK / P3.3
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG30
SEG31
P5.0 / SEG32
P5.1 / SEG33
P5.2 / SEG34
P5.3 / SEG35
P5.4 / SEG36
P5.5 / SEG37
P5.6 / SEG38
P5.7 / SEG39
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
VLC1
VLC2
VLC3
VLC4
VLC5
Figure 2. S3C7254 80–Pin QFP Assignment Diagram
4–3
PRODUCT SPECIFICATION
S3C7254
Table 1. S3C7254 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as opendrain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
25
26
27
28
K0/SCK
K1/SO
K2/SI
K3/BUZ
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit or 4-bit read and test are possible.
The 1-bit unit pull-up resistors are assigned to input
pins by software.
An interrupt is generated by digital input at P1.0,
P1.1.
29
30
31
32
INT0/CIN0
INT1/CIN1
INT2
INT4
33–36
–
37
38
39
40
–
–
LCDSY
LCDCK
41
42
43
CLO
TCL0
TCLO0
3–10
SEG32–
SEG39
P2.0–P2.3
I/O
Same as port 0 except that 8-bit read/write and test is
possible.
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
I/O
Same as port 0 except that port 4 is 3-bit I/O port.
P5.0–P5.7
O
Output port for 1-bit data
SCK
I/O
Serial I/O interface clock signal
25
P0.0/K0
SO
I/O
Serial data output
26
P0.1/K1
SI
I/O
Serial data input
27
P0.2/K2
BUZ
I/O
2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output for
buzzer sound
28
P0.3/K3
K0–K3
I/O
External interrupt. The triggering edge is selectable.
25–28
P0.0–P0.3
INT0
INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
29
30
P1.0/CIN0
P1.1/CIN1
INT2
I
Quasi-interrupt with detection of rising or falling
edges
31
P1.2
INT4
I
External interrupts with detection of rising and falling
edges
32
P1.3
4–4
S3C7254
PRODUCT SPECIFICATION
Table 1. S3C7254 Pin Descriptions (Continued)
Pin Name
CIN0
CIN1
Pin Type
I
Description
Number
Share Pin
2-channel comparator input.
CIN0: comparator input or external reference input
CIN1: comparator input only.
29
30
P1.0/INT0
P1.1/INT1
LCDSY
I/O
LCD synchronization clock output for display expansion
39
P3.2
LCDCK
I/O
LCD clock output for display expansion
40
P3.3
CLO
I/O
Clock output
41
P4.0
TCL0
I/O
External clock input for timer/counter 0
42
P4.1
TCLO0
I/O
Timer/counter 0 clock output
43
P4.2
SEG32–SEG39
O
LCD segment signal output
3–10
P5.0–P5.7
SEG0–SEG29
SEG30–SEG31
O
LCD segment signal output
51–80
1–2
–
COM0–COM7
O
LCD common signal output
12–19
–
VLC1–VLC5
–
LCD power supply. Voltage dividing resistors are
assignable by mask option.
20–24
–
XIN, XOUT
–
Crystal, ceramic or RC oscillator pins for system
clock.
48, 47
–
XTIN, XTOUT
–
Crystal oscillator pins for subsystem clock.
49, 50
–
VDD
–
Main power supply
46
–
VSS
–
Ground
11
–
RESET
I
Chip reset signal input
44
–
TEST
I
Chip test signal input (must be connected to VSS)
45
–
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
4–5
PRODUCT SPECIFICATION
S3C7254
Table 2. S3C7254 Pin Descriptions
Pin Name
Pin Type
Share Pin
Circuit Type
Reset Value
P0.0–P0.3
I/O
SCK/K0, SO/K1, SI/K2, BUZ/K3
6
Input
P1.0–P1.1
I
INT0/CIN0, INT1/CIN1
10
Comparator
P1.2–P1.3
I
INT2, INT4
3
Input
P2.0–P2.3
I/O
–
5
Input
P3.0–P3.1
I/O
–
5
Input
P3.2–P3.3
I/O
LCDSY, LCDCK
5
Input
P4.0, P4.2
I/O
CLO, TCLO0
5
Input
P4.1
I/O
TCL0
6
Input
P5.0–P5.7
O
SEG32–SEG39
7
High
COM0–COM7
O
–
8
High
SEG0–SEG31
O
–
8
High
VDD
–
–
–
–
VSS
–
–
–
–
RESET
I
–
2
–
VLC1–VLC5
–
–
–
–
XIN, XOUT
–
–
–
–
XTIN, XTOUT
–
–
–
–
TEST
I
–
–
–
4–6
S3C7254
PRODUCT SPECIFICATION
VDD
VDD
P-CHANNEL
PULL-UP
RESISTOR
IN
IN
N-CHANNEL
SCHMITT TRIGGER
Figure 3. Pin Circuit Type 1
Figure 4. Pin Circuit Type 2
VDD
VDD
PULL-UP
RESISTOR
P-CHANNEL
PULL-UP
RESISTOR
ENABLE
DATA
P-CHANNEL
OUT
N-CHANNEL
OUTPUT
DISABLE
IN
SCHMITT TRIGGER
Figure 5. Pin Circuit Type 3
Figure 6. Pin Circuit Type 4
4–7
PRODUCT SPECIFICATION
S3C7254
VDD
VDD
PNE
VDD
PULL-UP
RESISTOR
P-CH
DATA
VDD
PNE
P-CH
RESISTOR
ENABLE
I/O
PULL-UP
RESISTOR
RESISTOR
ENABLE
DATA
I/O
N- CH
N-CH
OUTPUT
DISABLE
OUTPUT
DISABLE
CIRCUIT TYPE 1
SCHMITT TRIGGER
Figure 7. Pin Circuit Type 5
Figure 8. Pin Circuit Type 6
V DD
SEG
V LC1
CIRCUIT
TYPE 9
OUTPUT
DISABLE
V LC2
P-CH
SEG/COM DATA
OUT
DATA
CIRCUIT
TYPE 4
N-CH
I/O
V LC3
V LC4
V LC5
Figure 9. Pin Circuit Type 7
4–8
Figure 10. Pin Circuit Type 8
S3C7254
PRODUCT SPECIFICATION
V DD
V LC1
V LC2
P-CHANNEL
SEG/COM DATA
OUT
OUTPUT DISABLE
N- CHANNEL
V LC3
V LC4
V LC5
Figure 11. Pin Circuit Type 9
VDD
PULL-UP
RESISTOR
RESISTOR
ENABLE
P–CH.
SCHMITT TRIGGER
(Digital)
IN
INT0/1
(Analog)
REF
(P1.0 ONLY)
IN
+
_
IN
COMPARATOR
REF
DIGITAL OR
ANALOG
SELECTABLE BY
SOFTWARE
Figure 12. Pin Circuit Type 10
4–9
PRODUCT SPECIFICATION
S3C7254
PROGRAM MEMORY (ROM)
ROM maps for S3C7254 devices are mask
programmable at the factory. In its standard
configuration, the device's 4,096 × 8-bit program
memory has three areas that are directly
addressable by the program counter (PC):
0000H
000FH
0010H
001FH
0020H
VECTOR
ADDRESS AREA
(16 Bytes)
GENERAL-PURPOSE
AREA
(16 Bytes)
INSTRUCTION
REFERENCE AREA
(96 Bytes)
007FH
0080H
GENERAL-PURPOSE
AREA
(3,968 Bytes)
— 16-byte area for vector addresses
— 96-byte instruction reference area
— 16-byte general-purpose area
— 3,968-byte general-purpose area
7
6
0000H
4
3
RESET
0002H
INTB/INT4
0004H
INT0
0006H
INT1
0008H
INTS
000AH
INTT0
000CH
INTK
FFFH
Figure 13. ROM Address Structure
4–10
5
2
1
0
S3C7254
PRODUCT SPECIFICATION
DATA MEMORY (RAM)
— 176 × 4-bit general-purpose area in bank 1
In its standard configuration, the 512 x 4-bit data
memory has five areas:
— 80 × 4-bit area for LCD data in bank 1
— 32 × 4-bit working register area in bank 0
— 128 × 4-bit area in bank 15 for memory-mapped
I/O addresses
— 224 × 4-bit general-purpose area in bank 0
which is also used as the stack area
000H
WORKING REGISTERS
(32 x 4 Bits)
01FH
020H
GENERAL -PURPOSE
REGISTERS
AND STACK AREA
(224 x 4 Bits)
0FFH
100H
1AFH
1B0H
1FFH
F8 0H
FFFH
BANK 0
GENERAL -PURPOSE
REGIS TERS
(176 x 4 Bits)
BANK 1
LCD DATA
REGISTERS
(80 x 4 Bits)
MEMORY-MAPPED I/O
ADDRESS
REGISTERS
(128 x 4 Bits)
BANK 15
Figure 14. Data Memory (RAM) Map
4–11
PRODUCT SPECIFICATION
S3C7254
ADDRESSING MODES
ADD RESSI NG
MOD E
RAM
AR EAS
DA
DA .b
EMB = 0
@H L
@H + DA. b
EMB = 1
000 H
01F H
020 H
07F H
080 H
EMB = 0
EMB = 1
@W X
@ WL
mem a.b
m emb. @L
X
X
X
WOR KIN G
REGI STE RS
BANK 0
(GENER AL
REGI STE RS
AN D STAC K)
SMB = 0
SMB = 0
SMB = 1
SMB = 1
SMB = 1
SMB = 1
0FF H
100 H
BAN K 1
(GEN ERAL
REGISTER S)
1AF H
1B0 H
BA NK 1
(D ISPLAY
RE G IST ERS)
1FF H
F80 H
FB0 H
BAN K 15
(PERIPHER AL
HAR DW ARE
REGISTER S)
SMB = 15
SMB = 15
FBF H
FC0 H
FF0 H
FF FH
NO T ES: 1. 'X' means don't c are.
2. Blank c olumns indic ate RAM areas that are not addres sable, giv en t he addres sing met hod
and enable m emory bank (EM B) f lag s ett ing s hown in t he c olumn headers.
Figure 15. RAM Address Structure
4–12
S3C7254
PRODUCT SPECIFICATION
Table 3. I/O Map for Memory Bank 15
Memory Bank 15
Addressing Mode
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
R/W
1-Bit
4-Bit
8-Bit
F80H
SP
.3
.2
.1
"0"
R/W
No
No
Yes
.7
.6
.5
.4
.3
.2
.1
.0
W
.3
Yes
No
R
No
No
Yes
W
.3 (1)
No
Yes
W
No
No
Yes
F81H
•
•
•
F85H
BMOD
F86H
BCNT
F87H
F88H
WMOD
.3
.2
.1
.0
.7
"0"
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
LCON
.3
.2
"1"
.0
W
No
Yes
No
TMOD0
.3
.2
"0"
"0"
W
.3
No
Yes
F91H
"0"
.6
.5
.4
F92H
"0"
TOE0
"0"
"0"
R/W
Yes
Yes
No
TCNT0
R
No
No
Yes
TREF0
W
No
No
Yes
W
No
Yes
No
F89H
F8AH
F8BH
F8CH
LMOD
F8DH
F8EH
F8FH
F90H
F93H
F94H
F95H
F96H
F97H
•
•
•
FA6H
PNE1
.3
.2
.1
.0
FA7H
4–13
PRODUCT SPECIFICATION
S3C7254
Table 3. I/O Map for Memory Bank 15 (Continued)
Memory Bank 15
Addressing Mode
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
R/W
1-Bit
4-Bit
8-Bit
FA8H
PNE2
.3
.2
.1
.0
W
No
No
Yes
.7
.6
.5
.4
PNE3
"0"
.2
.1
.0
Yes
No
PSW
IS1
IS0
EMB
ERB
R/W
Yes
Yes
Yes
C (2)
SC2
SC1
SC0
R
No
No
FA9H
FAAH
•
•
•
FB0H
FB1H
FB2H
IPR
IME
.2
.1
.0
W
IME
Yes
No
FB3H
PCON
.3
.2
.1
.0
W
No
Yes
No
FB4H
IMOD0
.3
"0"
.1
.0
W
No
Yes
No
FB5H
IMOD1
"0"
"0"
"0"
.0
W
No
Yes
No
FB6H
IMODK
"0"
.2
.1
.0
W
No
Yes
No
FB7H
SCMOD
.3
"0"
"0"
.0
W
Yes
No
No
IE4
IRQ4
IEB
IRQB
R/W
Yes
Yes
No
FBAH
"0"
"0"
IEW
IRQW
R/W
Yes
Yes
No
FBBH
"0"
"0"
IEK
IRQK
FBCH
"0"
"0"
IET0
IRQT0
FBDH
"0"
"0"
IES
IRQS
FBEH
IE1
IRQ1
IE0
IRQ0
FBFH
"0"
"0"
IE2
IRQ2
R/W
Yes
Yes
Yes
FB8H
FB9H
FC0H
BSC0
FC1H
BSC1
FC2H
BSC2
FC3H
BSC3
•
•
•
4–14
Yes
S3C7254
PRODUCT SPECIFICATION
Table 3. I/O Map for Memory Bank 15 (Continued)
Memory Bank 15
Addressing Mode
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
R/W
1-Bit
4-Bit
8-Bit
FD0H
CLMOD
.3
"0"
.1
.0
W
No
Yes
No
CMPREG
.3
.2
.1
.0
R
No
Yes
No
CMOD
.3
.2
.1
.0
R/W
No
No
Yes
.7
.6
.5
"0"
IMOD2
"0"
"0"
"0"
.0
W
No
Yes
No
PUMOD1
.3
.2
"0"
.0
W
No
No
Yes
"0"
"0"
"0"
.4
PUMOD2
.3
.2
.1
.0
W
No
Yes
No
SMOD
.3
.2
.1
.0
W
.3
No
Yes
.7
.6
.5
"0"
"0"
"0"
.1
.0
W
No
Yes
No
R/W
No
No
Yes
W
No
No
Yes
FD1H
FD2H
FD3H
FD4H
FD5H
FD6H
FD7H
FD8H
FD9H
FDAH
FDBH
FDCH
FDDH
FDEH
FDFH
FE0H
FE1H
FE2H
P1MOD
FE3H
FE4H
SBUF
FE5H
FE6H
PMG1
FE7H
FE8H
FE9H
PMG2
.3
.2
.1
.0
"0"
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
•
•
•
4–15
PRODUCT SPECIFICATION
S3C7254
Table 3. I/O Map for Memory Bank 15 (Concluded)
Memory Bank 15
Addressing Mode
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
R/W
1-Bit
4-Bit
8-Bit
FF0H
Port 0 (P0)
.3
.2
.1
.0
R/W
Yes
Yes
No
FF1H
Port 1 (P1)
.3
.2
.1
.0
R
FF2H
Port 2 (P2)
.3
.2
.1
.0
R/W
Yes
Yes
Yes
FF3H
Port 3 (P3)
.3 / .7
.2 / .6
.1 / .5
.0 / .4
R/W
FF4H
Port 4 (P4)
"0"
.2
.1
.0
R/W
Yes
Yes
No
•
•
•
FFFH
NOTES:
1.
2.
Bit 3 in the WMOD register is read only.
The carry flag can be read or written by specific bit manipulation instructions only.
4–16
S3C7254
PRODUCT SPECIFICATION
OSCILLATOR CIRCUITS
subsystem clock (fxt) as the CPU clock and to start
(or stop) main system clock oscillation.
The S3C7254 microcontroller have two oscillator
circuits: a main system clock circuit, and a
subsystem clock circuit. The main system clock
frequencies can be divided by 4, 8, or 64 by
manipulating PCON bits 1 and 0.
The watch timer, buzzer and LCD display operate
normally with a subsystem clock source, since they
operate at very slow speeds and with very low
power consumption (as low as 122 µs at 32.768
kHz).
The system clock mode control register, SCMOD,
lets you select a main system clock (fx) or a
MAIN SYSTEM
OSCILLATOR
CIRCUIT
fx
SUBSYSTEM
OSCILLATOR
CIRCUIT
fxt
WATCH
TIMER
LCD
CONTROLLER
SELECTOR
Xin
Xout
Xin
Xout
fxx
OSCILLATOR
STOP
LCD CONTROLLER
BASIC TIMER
TIMER/COUNTERS 0
SERIAL I/O INTERFACE
WATCH TIMER
CLOCK OUTPUT CIRCUIT
FREQUENCY
DIVIDING
CIRCUIT
1/2
1/16
SCMOD.3
SCMOD.0
SELECTOR
1/4
CPU
CLOCK
CPU STOP SIGNAL
(IDLE MODE)
PCON.0
PCON.1
IDLE
PCON.2
STOP
PCON.3
WAIT RELEASE SIGNAL
OSCILLATOR
CONTROL
CIRCUIT
INTERNAL RESET SIGNAL
POWER-DOWN RELEASE SIGNAL
PCON.3,2 CLEAR
Figure 16. Clock Circuit Diagram
4–17
PRODUCT SPECIFICATION
S3C7254
MAIN SYSTEM OSCILLATOR CIRCUITS
SUBSYSTEM OSCILLATOR CIRCUITS
Xin
XTin
Xout
XTout
32.768 kHz
Figure 17. Crystal/Ceramic Oscillator (fx)
Figure 20. Crystal/Ceramic Oscillator (fxt)
XTin
Xin
XTout
Xout
EXTERNAL
CLOCK
Figure 18. External Oscillator (fx)
Xin
R
Xout
Figure 19. RC Oscillator (fx)
4–18
Figure 21. External Oscillator (fxt)
S3C7254
PRODUCT SPECIFICATION
POWER CONTROL REGISTER (PCON)
The power control register, PCON, is a 4-bit register
that is used to select the CPU clock frequency and
to control CPU operating and power-down modes.
PCON bits 3 and 2 are addressed by the STOP and
IDLE instructions, respectively, to engage the idle
and stop power-down modes. Idle and stop modes
can be initiated by these instruction despite the
current value of the enable memory bank flag
(EMB). PCON bits 1 and 0 are used to select a
specific system clock frequency. There are two
basic choices:
— Main system clock (fx) or subsystem clock (fxt);
— Divided fx frequency of 4, 8, or 64.
PCON.1 and PCON.0 settings are also connected
with the system clock mode control register,
SCMOD. If SCMOD.0 = "0" the main system clock
is always selected by the PCON.1 and PCON.0
setting; if SCMOD.0 = "1" the subsystem clock is
selected.
Table 4. Power Control Register (PCON) Organization
PCON Bit Settings
Resulting CPU Operating Mode
PCON.3
PCON.2
0
0
Normal CPU operating mode
0
1
Idle power-down mode
1
0
Stop power-down mode
PCON Bit Settings
Resulting CPU Clock Frequency
PCON.1
PCON.0
If SCMOD.0 = "0"
If SCMOD.0 = "1"
0
0
fx/64
—
1
0
fx/8
—
1
1
fx/4
fxt/4
+ PROGRAMMING TIP — Setting the CPU Clock
To set the CPU clock to 0.95 µs at 4.19 MHz:
BITS
SMB
LD
LD
EMB
15
A,#3H
PCON,A
4–19
PRODUCT SPECIFICATION
S3C7254
(fx) or a subsystem clock (fxt) is used, and on how
the oscillator clock signal is divided (by 4, 8, or 64).
Table 5 shows corresponding cycle times in
microseconds.
INSTRUCTION CYCLE TIMES
The unit of time that equals one machine cycle
varies depending on whether the main system clock
Table 5. Instruction Cycle Times for CPU Clock Rates
Selected
CPU Clock
Resulting Frequency
Oscillation
Source
Cycle Time (µsec)
fx/64
65.5 kHz
fx = 4.19 MHz
15.3
fx/8
524.0 kHz
1.91
fx/4
1.05 MHz
0.95
fxt/4
8.19 kHz
fxt = 32.768 kHz
SYSTEM CLOCK MODE REGISTER (SCMOD)
122.0
Subsystem clock oscillation cannot, of course, be
stopped internally. Also, if you have selected fx as
the CPU clock, setting SCMOD.3 to "1" will not stop
main system clock oscillation. This can only be done
by a STOP instruction.
The system clock mode register, SCMOD, is a 4-bit
register that is used to select the CPU clock and to
control main system clock oscillation. Only its least
significant and most significant bits can be
manipulated by 1-bit write instructions.
Table 6. System Clock Mode Register (SCMOD) Organization
SCMOD Register Bit Settings
4–20
Resulting Clock Selection
SCMOD.3
SCMOD.0
CPU Clock
fx Oscillation
0
0
fx
On
0
1
fxt
On
1
1
fxt
Off
S3C7254
PRODUCT SPECIFICATION
SWITCHING THE CPU CLOCK
Together, bit settings in the power control register,
PCON, and the system clock mode register,
SCMOD, determine whether a main system or a
subsystem clock is selected as the CPU clock, and
also how this frequency is to be divided. This makes
it possible to switch dynamically between main and
subsystem clocks and to modify operating
frequencies.
SCMOD.3 and SCMOD.0 select the main system
clock (fx) or a subsystem clock (fxt) and start or stop
main system clock oscillation. PCON.1 and PCON.0
control the frequency divider circuit, and divide the
selected fx or fxt clock by 4, 8, or 64.
NOTE
A clock switch operation does not go into
effect immediately when you make the
SCMOD and PCON register modifications
— the previously selected clock continues to
run for a certain number of machine cycles.
For example, you are using the default CPU clock
(normal operating mode and a main system clock of
fx/64) and you want to switch from the fx clock to a
subsystem clock and to stop the main system clock.
To do this, you first need to set SCMOD.0 to "1".
This switches the clock from fx to fxt but allows
main system clock oscillation to continue. Before the
switch actually goes into effect, a certain number of
machine cycles must elapse. After this time interval,
you can then disable main system clock oscillation
by setting SCMOD.3 to "1".
This same 'stepped' approach must be taken to
switch from a subsystem clock to the main system
clock: first, clear SCMOD.3 to "0" to enable main
system clock oscillation. Then, after a certain
number of machine cycles has elapsed, select the
main system clock by clearing all SCMOD values to
logic zero.
Following a RESET, CPU operation starts with the
lowest main system clock frequency of 15.3 µsec at
4.19 MHz after the standard oscillation stabilization
interval of 31.3 ms has elapsed. Table 6–4 details
the number of machine cycles that must elapse
before a CPU clock switch modification goes into
effect.
Table 7. Elapsed Machine Cycles During CPU Clock Switch
AFTER
BEFORE
SCMOD.0 = 0
PCON.1 = 0
PCON.1 = 0
PCON.0 = 0
PCON.1 = 1
PCON.0 = 0
SCMOD.0 = 1
PCON.1 = 1
PCON.0 = 1
N/A
1 MACHINE CYCLE
1 MACHINE CYCLE
N/A
8 MACHINE CYCLES
N/A
8 MACHINE CYCLES
N/A
16 MACHINE CYCLES
16 MACHINE CYCLES
N/A
fx / 4fxt
N/A
N/A
fx / 4fxt (M/C)
N/A
PCON.0 = 0
SCMOD.0 = 0
PCON.1 = 1
PCON.0 = 0
PCON.1 = 1
PCON.0 = 1
SCMOD.0 = 1
NOTES:
1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered.
2. Since the Xin input is connected internally to VSS to avoid current leakage due to the crystal oscillator in stop mode, do
not set SCMOD.3 to "1" when an external clock is used as the main system clock.
3. When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur
during the time intervals shown in Table 6–4.
4. 'N/A' means 'not available'.
4–21
PRODUCT SPECIFICATION
S3C7254
+ PROGRAMMING TIP — Switching Between Main System and Subsystem Clock
1. Switch from the main system clock to the subsystem clock:
MA2SUB
DLY80
DEL1
BITS
CALL
BITS
RET
LD
NOP
NOP
DECS
JR
RET
SCMOD.0
DLY80
SCMOD.3
; Switches to subsystem clock
; Delay 80 machine cycles
; Stop the main system clock
A,#0FH
A
DEL1
2. Switch from the subsystem clock to the main system clock:
SUB2MA
4–22
BITR
CALL
BITR
RET
SCMOD.3
DLY80
SCMOD.0
; Start main system clock oscillation
; Delay 80 machine cycles
; Switch to main system clock
S3C7254
PRODUCT SPECIFICATION
source (without initiating clock oscillation), and
disables clock output.
CLOCK OUTPUT MODE REGISTER (CLMOD)
The clock output mode register, CLMOD, is a 4-bit
register that is used to enable or disable clock
output to the CLO pin and to select the CPU clock
source and frequency. CLMOD is addressable by 4bit write instructions only.
CLMOD.3 is the enable/disable clock output control
bit; CLMOD.1 and CLMOD.0 are used to select one
of four possible clock sources and frequencies:
normal CPU clock, fxx/8, fxx/16, or fxx/64. Table 6–
5. Clock Output Mode Register (CLMOD)
Organization
RESET clears CLMOD to logic zero, which
automatically selects the CPU clock as the clock
Table 8. Clock Output Mode Register (CLMOD) Organization
CLMOD Bit Settings
Resulting Clock Output
CLMOD.1
CLMOD.0
Clock Source
Frequency
0
0
CPU clock (fx/4, fx/8, fx/64, fxt/4)
1.05 MHz, 524 kHz, 65.5 kHz,
8.19 kHz
0
1
fxx/8
524 kHz, 4.096 kHz
1
0
fxx/16
262 kHz, 2.048 kHz
1
1
fxx/64
65.5 kHz, 0.512 kHz
CLMOD.3
Result of CLMOD.3 Setting
0
Clock output is disabled
1
Clock output is enabled
NOTE: Frequencies assume that fxx is 4.19 MHz and fxt is 32.768 kHz.
CLMOD.3
CLO
CLMOD.2
4
CLMOD.1
CLMOD.0
CLOCK
SELECTOR
P4.0 OUTPUT LATCH
PM4.0
CLOCKS
(fxx/8, fxx/16, fxx/64, CPU clock)
Figure 22. CLO Output Pin Circuit Diagram
4–23
PRODUCT SPECIFICATION
+
S3C7254
PROGRAMMING TIP — CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin:
BITS
SMB
LD
LD
BITR
LD
LD
4–24
EMB
15
EA,#10H
PMG1,EA
P4.0
A,#9H
CLMOD,A
; P4.0 ← Output mode
; Clear P4.0 output latch
S3C7254
PRODUCT SPECIFICATION
INTERRUPTS
The S3C7254 has four external, three internal and two quasi interrupts. Table 9 shows the conditions for each
interrupt generation. The request flags that allow the interrupts to be generated are cleared to logic zero by
hardware when the service routine is vectored. The quasi interrupt (INT2, IRQW) request flags must be cleared
by software.
IMOD1
IE2 IEW IEK
IMOD0
INTB
INT4
IE0
IE4
IEB
IRQB
IRQ0
@
#
IRQ1
@
INTS
IRQT0
INTT0
IRQS
IRQK
@
IRQW
INTW
IMODK
INT2
IE1
IRQ4
INT0
INT1
IET0 IES
IRQ2
@
IMOD2
*
POWER-DOWN
MODE
RELEASE SIGNAL
IME
IPR
INTERRUPT CONTROL UNIT
IS1 IS0
# = NOISE FILTERING CIRCUIT
@ = EDGE DETECTION CIRCUIT
VECTOR INTERRUPT
* When fxx/64 is selected as a sampling clock for INT0, idle mode can be released by INT0.
GENERATOR
Figure 23. Interrupt Control Circuit Diagram
4–25
PRODUCT SPECIFICATION
S3C7254
Table 9. Interrupt Request Flag Conditions and Priorities
Interrupt
Source
Internal /
External
Pre-condition for IRQx Flag Setting
Interrupt
Priority
IRQ Flag
Name
INTB
I
Reference time interval signal from basic
timer
1
IRQB
INT4
E
Both rising and falling edges detected at INT4
1
IRQ4
INT0
E
Rising or falling edge detected at INT0 pin
2
IRQ0
INT1
E
Rising or falling edge detected at INT1 pin
3
IRQ1
INTS
I
Completion signal for serial transmit-and-receive or receive-only operation
4
IRQS
INTT0
I
Signals for TCNT0 and TREF0 registers
match
5
IRQT0
INTK
E
When a rising or falling edge detected at any
one of the K0–K3 pins
6
IRQK
INT2 *
E
Rising or falling edge detected at INT2
—
IRQ2
INTW
I
Time interval of 0.5 second or 3.19 ms
—
IRQW
NOTE: The quasi-interrupt INT2 is only used for testing incoming signals.
3.
4.
INTERRUPT ENABLE FLAGS (IEX)
IEx flags, when set to logical one, enable specific
interrupt requests to be serviced. When the interrupt
request flag is set to logical one, an interrupt will not
be serviced until its corresponding IEx flag is also
enabled.
Interrupt enable flags can be read, written, or tested
directly by 1-bit instructions. IEx flags can be
addressed directly at their specific RAM addresses,
despite the current value of the enable memory
bank (EMB) flag.
Table 10. Interrupt Enable and Request Flag
Address
Bit 3
Bit 2
Bit 1
Bit 0
FB8H
IE4
IRQ4
IEB
IRQB
FBAH
0
0
IEW
IRQW
FBBH
0
0
IEK
IRQK
FBCH
0
0
IET0
IRQT0
FBDH
0
0
IES
IRQS
FBEH
IE1
IRQ1
IE0
IRQ0
FBFH
0
0
IE2
IRQ2
NOTES:
1. IEx refers generically to all interrupt enable flags.
2. IRQx refers generically to all interrupt request flags.
4–26
IEx = 0 is interrupt disable mode.
IEx = 1 is interrupt enable mode.
INTERRUPT PRIORITY REGISTER (IPR)
The 4-bit interrupt priority register (IPR) is used to
control multi-level interrupt handling. Its reset value
is logic zero. Before the IPR can be modified by 4bit write instructions, all interrupts must first be
disabled by a DI instruction.
By manipulating the IPR settings, you can choose to
process all interrupt requests with the same priority
level, or you can select one type of interrupt for
high-priority processing. A low-priority interrupt can
itself be interrupted by a high-priority interrupt, but
not by another low-priority interrupt. A high-priority
interrupt cannot be interrupted by any other interrupt
source.
S3C7254
PRODUCT SPECIFICATION
Table 11. Standard Interrupt Priorities
Interrupt
1
0
1
Process INTT0 interrupts
only
1
1
0
Process INTK interrupts
only
Default Priority
INTB, INT4
INT0
INT1
INTS
INTT0
1
2
3
4
5
INTK
6
The MSB of the IPR, the interrupt master enable
flag (IME), enables and disables all interrupt
processing. Even if an interrupt request flag and its
corresponding enable flag are set, a service routine
cannot be executed until the IME flag is set to logic
one. The IME flag can be directly manipulated by EI
and DI instructions, regardless of the current enable
memory bank (EMB) value.
Table 12. Interrupt Priority Register Settings
IPR.2
IPR.1
IPR.0
0
0
0
Result of IPR Bit Setting
Process all interrupt
requests at low priority
(NOTE)
0
0
1
Process INTB and INT4
interrupts only
0
1
0
Process INT0 interrupts
only
0
1
1
Process INT1 interrupts
only
1
0
0
Process INTS interrupts
only
NOTE: When all interrupts are low priority (the lower
three bits of the IPR register are logic zero), the
interrupt requested first will have high priority.
Therefore, the first- request interrupt cannot be
superceded by any other interrupt.
EXTERNAL INTERRUPT 0, 1 AND 2 MODE
REGISTERS (IMOD0, IMOD1 AND IMOD2)
The following components are used to process
external interrupts at the INT0, INT1 and INT2 pins:
— Noise filtering circuit for INT0
— Edge detection circuit
— Three mode registers, IMOD0, IMOD1 and
IMOD2
The mode registers are used to control the triggering
edge of the input signal. IMOD0, IMOD1 and IMOD2
settings let you choose either the rising or falling
edge of the incoming signal as the interrupt request
trigger. The INT4 interrupt is an exception since its
input signal generates an interrupt request on both
rising and falling edges. Since INT2 is a qusiinterrupt, the interrupt request flag (IRQ2) must be
cleared by software.
IMOD0, IMOD1 and IMOD2 are addressable by 4-bit
write instructions. RESET clears all IMOD values to
logic zero, selecting rising edges as the trigger for
incoming interrupt requests.
4–27
PRODUCT SPECIFICATION
S3C7254
Table 13. IMOD0, 1 and 2 Register Organization
IMOD0
IMOD1
IMOD2
IMOD0.3
0
IMOD0.1
IMOD0.0
Effect of IMOD0 Settings
0
Select CPU clock for sampling
1
Select fxx/64 sampling clock
0
0
0
0
Rising edge detection
0
1
Falling edge detection
1
0
Both rising and falling edge detection
1
1
IRQ0 flag cannot be set to "1"
0
IMOD1.0
IMOD2.0
Effect of IMOD1 and IMOD2 Settings
0
Rising edge detection
1
Falling edge detection
When a sampling clock rate of fxx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take
the following precautions when you use it:
— To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of
the clock selected by IMOD0. This is true even when the INT0 pin is used for general-purpose input.
— you can use INT0 to release idle mode, when fxx/64 is selected as a sampling clock.
4–28
S3C7254
PRODUCT SPECIFICATION
CPU CLOCK
fxx/64
IMOD0
CLOCK
SELECTOR
INT0
2
NOISE FILTER
EDGE DETECTION
IRQ0
INT1
EDGE DETECTION
IRQ1
INT2
EDGE DETECTION
IRQ2
IMOD2
P1.2
P1.1
IMOD1
P1.0
Figure 24. Circuit Diagram for INT0, INT1 and INT2 Pins
4–29
PRODUCT SPECIFICATION
S3C7254
EXTERNAL KEY INTERRUPT MODE REGISTER
(IMODK)
The mode register for external key interrupts at the
K0–K3 pins, IMODK, is addressable only by 4-bit
write instructions. RESET clears all IMODK bits to
logic zero.
Rising or falling edge can be detected by bit
IMODK.2 settings. If a rising or falling edge is
detected at any one of the selected K pin by the
IMODK register, the IRQK flag is set to logic one
and a release signal for power-down mode is
generated.
Table 14. IMODK Register Bit Settings
IMODK
IMODK.2
0
IMODK.2
IMODK.1
IMODK.0
0, 1
0
0
Disable key interrupt
0
1
Enable edge detection at the K0–K1 pins
1
0
Enable edge detection at the K0–K2 pins
1
1
Enable edge detection at the K0–K3 pins
0
Falling edge detection
1
Rising edge detection
Effect of IMODK Settings
NOTE:
1. To generate a key interrupt, the selected pins must be configured to input mode. If any one pin of the selected pins is
configured to output mode, only falling edge can be detected.
2. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select
edge detection and pins by setting IMODK register.
P0.3/ K3
P0.2/ K2
PIN
SELEC TOR
P0.1/ K1
P0.0/ K0
I MODK
Figure 25. Circuit Diagram for INTK
4–30
R ISING/
FALLLING
ED GE
SELEC TOR
IR Q K
S3C7254
PRODUCT SPECIFICATION
POWER-DOWN
The S3C7254 microcontroller has two power-down
modes to reduce power consumption: idle and stop.
Idle mode is initiated by the IDLE instruction and
stop mode by the instruction STOP. (Several NOP
instructions must always follow an IDLE or STOP
instruction in a program.) In idle mode, the CPU
clock stops while peripherals and the oscillation
source continue to operate normally.
In stop mode, main system clock oscillation is halted
(assuming it is currently operating), and peripheral
hardware components are powered-down. The
effect of stop mode on specific peripheral hardware
components — CPU, basic timer, serial I/O, timer/
counter 0, watch timer, and LCD controller — and
on external interrupt requests, is detailed in Table
15.
Table 15. Hardware Operation During Power-Down Modes
Operation
Stop Mode (STOP)
Idle Mode (IDLE)
System clock status
Can be changed only if the main system
clock is used
Can be changed if the main system clock
or subsystem clock is used
Clock oscillator
Main system clock oscillation stops
CPU clock oscillation stops (main and
subsystem clock oscillation continues)
Basic timer
Basic timer stops
Basic timer operates (with IRQB set at
each reference interval)
Serial I/O interface
Operates only if external SCK input is
selected as the serial I/O clock
Operates if a clock other than the CPU
clock is selected as the serial I/O clock
Timer/counter 0
Operates only if TCL0 is selected as the
counter clock
Timer/counter 0 operates
Watch timer
Operates only if subsystem clock (fxt) is
selected as the counter clock
Watch timer operates
LCD controller
Operates only if a subsystem clock is se- LCD controller operates
lected as LCDCK
External interrupts
INT1, INT2, INT4, and INTK are
acknowledged; INT0 is not serviced
INT1, INT2, INT4, INT0, and INTK are
acknowledged (NOTE)
CPU
All CPU operations are disabled
All CPU operations are disabled
Mode release signal
Interrupt request signals (except INT0)
Interrupt request signals are enabled by
are enabled by an interrupt enable flag or an interrupt enable flag or by RESET
by RESET input
input (NOTE)
NOTE: INT0 can be operated in idle mode only when fxx/64 is selected as a sampling clock.
4–31
PRODUCT SPECIFICATION
S3C7254
+ PROGRAMMING TIP — Reducing Power Consumption for Key Input Interrupt Processing
The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption.
In this example, the system clock source is switched from the main system clock to a subsystem clock and the
LCD display is turned on:
KEYCLK
CLKS1
CIDLE
4–32
DI
CALL
MA2SUB
SMB
LD
LD
LD
LD
SMB
BITR
BITR
BITS
BITS
CALL
BTSTZ
JR
CALL
15
EA,#00H
P2,EA
A,#3H
IMODK,A
0
IRQW
IRQK
IEW
IEK
WATDIS
IRQK
CIDLE
SUB2MA
EI
RET
IDLE
NOP
NOP
JPS
; Main system clock → subsystem clock switch
subroutine
; All key strobe outputs to low level
; Select K0–K3 enable
; Execute clock and display changing subroutine
; Subsystem clock → main system clock switch
subroutine
; Engage idle mode
CLKS1
S3C7254
PRODUCT SPECIFICATION
RECOMMENDED CONNECTIONS FOR UNUSED PINS
To reduce overall power consumption, please configure unused pins according to the guidelines described in
Table 16.
Table 16. Unused Pin Connections for Reduced Power Consumption
Pin/Share Pin Names
Recommended Connection
P0.0 / SCK / K0
P0.1 / SO / K1
P0.2 / SI / K2
P0.3 / BUZ / K3
Input mode: Connect to VDD
Output mode: No connection
P1.0 / CIN0 / INT0
P1.1 / CIN1 /INT1
P1.2 / INT2
P1.3 / INT4
Connect to VDD (1)
P2.0–P2.3
Input mode: Connect to VDD
Output mode: No connection
P3.0–P3.1
P3.2 / LCDSY
P3.0 / LCDCK
P4.0 / CLO
P4.1 / TCL0
P4.2 / TCLO0
Input mode: Connect to VDD
Output mode: No connection
P5.0 / SEG32–P5.7 / SEG39
No connection (2)
SEG0–SEG29
SEG30–SEG31
COM0–COM7
No connection
VLC1–VLC5
No connection
XTin
Connect XTin to VSS or VDD
XTout
No connection
TEST
Connect to VSS
NOTES
1. Digital mode at P1.0 and P1.1
2. Used as segment
4–33
PRODUCT SPECIFICATION
S3C7254
RESET
Table 17 provides detailed information about hardware register values after a RESET occurs during power-down
mode or during normal operation.
Table 17. Hardware Register Values After RESET
Hardware Component
or Subcomponent
Program counter (PC)
Bank selection registers (SMB, SRB)
BSC register (BSC0–BSC3)
If RESET Occurs During
Power-Down Mode
Lower six bits of address 0000H
are transferred to PC11–8, and
the contents of 0001H to PC7–0.
0, 0
If RESET Occurs During
Normal Operation
Lower six bits of address 0000H
are transferred to PC11–8, and
the contents of 0001H to PC7–0.
0, 0
0
0
Retained
Undefined
Skip flag (SC0–SC2)
0
0
Interrupt status flags (IS0, IS1)
0
0
Bank enable flags (EMB, ERB)
Bit 6 of address 0000H in program
memory is transferred to the ERB
flag, and bit 7 of the address to
the EMB flag.
Undefined
Bit 6 of address 0000H in
program memory is transferred to
the ERB flag, and bit 7 of the
address to the EMB flag.
Undefined
Values retained
Undefined
Values retained (note)
Undefined
Power control register (PCON)
0
0
Clock output mode register (CLMOD)
0
0
System clock mode register (SCMOD)
0
0
Interrupt request flags (IRQx)
0
0
Interrupt enable flags (IEx)
0
0
Interrupt priority flag (IPR)
0
0
Interrupt master enable flag (IME)
0
0
INT0 mode register (IMOD0)
0
0
INT1 mode register (IMOD1)
0
0
INT2 mode register (IMOD2)
0
0
INTK mode register (IMODK)
0
0
Program Status Word (PSW):
Carry flag (C)
Stack pointer (SP)
Data Memory (RAM):
Working registers E, A, L, H, X, W, Z,
Y
General-purpose registers
Clocks:
Interrupts:
NOTE: The values of the 0F8H-0FDH are not retained when a RESET signal is input.
4–34
S3C7254
PRODUCT SPECIFICATION
Table 17. Hardware Register Values After RESET (Continued)
If RESET Occurs During
Power-Down Mode
If RESET Occurs During
Normal Operation
Output buffers
Off
Off
Output latches
0
0
Port mode flags (PM)
0
0
Pull-up resistor mode reg
(PUMOD1/2)
0
0
Count register (BCNT)
Undefined
Undefined
Mode register (BMOD)
0
0
0
0
FFH
FFH
Mode registers (TMOD0)
0
0
Output enable flags (TOE0)
0
0
0
0
LCD mode register (LMOD)
0
0
LCD control register (LCON)
0
0
Values retained
Undefined
Off
Off
SIO mode register (SMOD)
0
0
SIO interface buffer (SBUF)
Values retained
Undefined
0
0
0
0
Undefined
Undefined
Hardware Component
or Subcomponent
I/O Ports:
Basic Timer:
Timer/Counters 0 and 1:
Count registers (TCNT0)
Reference registers (TREF0)
Watch Timer:
Watch timer mode register (WMOD)
LCD Driver/Controller:
Display data memory
Output buffers
Serial I/O Interface:
N-Channel Open-Drain Mode Register
PNE1/2/3
Comparator
Comparator mode register (CMOD)
Comparison result register
4–35
PRODUCT SPECIFICATION
S3C7254
I/O PORTS
The S3C7254 has 6 ports. There are total of 4 input
pins, 8 output pin and 15 configurable I/O pins, for
a maximum number of 27 pins.
PORT MODE FLAGS (PM FLAGS)
When a PM flag is "0", the port is set to input mode;
when it is "1", the port is enabled for output. RESET
clears all port mode flags to logical zero,
automatically configuring the corresponding I/O
ports to input mode.
Port mode flags (PM) are used to configure I/O
ports to input or output mode by setting or clearing
the corresponding I/O buffer.
Table 18. Port Mode Group Flags
PM Group ID
Address
Bit 3
Bit 2
Bit 1
Bit 0
PMG1
FE6H
PM0.3
PM0.2
PM0.1
PM0.0
FE7H
"0"
PM4.2
PM4.1
PM4.0
FE8H
PM2.3
PM2.2
PM2.1
PM2.0
FE9H
PM3.3
PM3.2
PM3.1
PM3.0
PMG2
NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit ="1", the pin is set to output mode: PM0.0 for
P0.0, PM0.1 for P0.1, etc,. All flags are cleared to logic zero following RESET.
+ PROGRAMMING TIP — Configuring I/O Ports to Input or Output
Configure ports 0 and 2 as an output port:
BITS
SMB
LD
LD
4–36
EMB
15
EA,#7FH
PMG1,EA
; P0 and P4 ← Output
S3C7254
PRODUCT SPECIFICATION
the input mode from digital to analog using
P1MOD settings, IRQ0 and IRQ1 will be set.
When you use analog input, you must
clear the corresponding interrupt enable
flag (IEx). That is, clear IE0 when P1.0 is
an analog input and clear IE1 when P1.1 is
an analog input.
PORT 1 MODE REGISTER (P1MOD)
P1MOD register settings determine if port 1 is used
for digital input or for analog input. The P1MOD
register is a 4-bit write only register. P1MOD is
mapped to address FE2H. A reset operation
initializes all P1MOD values to logic zero,
configuring port 1 as an analog input port.
PULL-UP RESISTOR MODE REGISTER (PUMOD)
When a P1MOD bit is "0", the corresponding pin
is configured as a analog input pin. When set to
"1", it is configured as an digital input pin:
P1MOD.0 corresponds to P1.0, and P1MOD.1
to P1.1.
The pull-up resistor mode registers (PUMOD1 and
PUMOD2) are used to assign internal pull-up
resistors by software to specific ports. When a
configurable I/O port pin is used as an output pin, its
assigned pull-up resistor is automatically disabled,
even though the pin's pull-up is enabled by a
corresponding PUMOD bit setting.
NOTE
INT0 and INT1 can occur only when the port
is configured to digital input. If you change
Table 19. Pull-Up Resistor Mode Register (PUMOD) Organization
PUMOD ID
Address
Bit 3
Bit 2
Bit 1
Bit 0
PUMOD1
FDCH
PUR3
PUR2
“0”
PUR0
FDDH
0
0
0
PUR4
FDEH
PUR1.3
PUR1.2
PUR1.1
PUR1.0
PUMOD2
NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2,
and so on.
+ PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
P6 and P7 enable pull-up resistors.
BITS
SMB
LD
LD
EMB
15
EA,#0CH
PUMOD1,EA
N-CHANNEL OPEN-DRAIN MODE REGISTER
The n-channel open-drain mode register (PNE) is
used to configure ports 0, 2, 3 and 4 to n-channel
open-drain or as push-pull outputs. When a bit in the
PNE register is set to "1", the corresponding output
pin is configured to n-channel, open-drain; when set
to "0", the output pin is configured to push-pull. The
PNE register consists of an 8-bit register and a 4-bit
register; PNE1 and PNE3 can be addressed by 4-bit
; P2 and P3 enable
write instructions only and PNE2 by 8-bit write
instructions only.
PNE ID
ADDRESS
Bit 3
Bit 2
Bit 1
Bit 0
PNE1
FA6H
P0.3
P0.2
P0.1
P0.0
PNE2
FA8H
P2.3
P2.2
P2.1
P2.0
FA9H
P3.3
P3.2
P3.1
P3.0
FAAH
0
P4.2
P4.1
P4.0
PNE3
4–37
PRODUCT SPECIFICATION
S3C7254
PORT 0 CIRCUIT DIAGRAM
PNE1.3
VDD
PUR0
PNE1.2
PNE1.1
PNE1.0
PM0.3
PM0.2
PM0.1
PM0.0
P0.0 / SCK /K0
P0.1 /SO /K1
OUTPUT
LATCH
P0.2 /SI /K2
1, 4
P0.3 /BUZ /K3
CMOS PUSH- PULL
or N-CHANNEL
OPEN-DRAIN
M
U
X
NOTE:
When a port pin serves as an output, its pull-up resistor is automatically disabled, even
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode
register (PUMOD).
Figure 26. Port 0 Circuit Diagram
4–38
1, 4
S3C7254
PRODUCT SPECIFICATION
PORT 1 CIRCUIT DIAGRAM
V DD VDD V DD V DD
INT0
INT1
INT2
INT4
PUR1.0
PUR1.1
PUR1.2
IMOD0
PUR1.3
P1.0 /INT0 /CIN0
N/R
CIRCUIT
Digital Input
Analog Input
External
Reference
P1.1 /INT1 /CIN1
Digital Input
Analog Input
P1.2 / INT2
Digital Input
P1.3 / INT4
Digital Input
N/R = NOISE REDUCTION
Figure 27. Input Port 1 Circuit Diagram
4–39
PRODUCT SPECIFICATION
S3C7254
PORTS 2 AND 3 CIRCUIT DIAGRAM
VDD
x = 2, 3
b = 0, 1, 2, 3
PNE2
PURx
PMx.b
OUTPUT
LATCH
Px.b
M
U
X
NOTE:
1, 4, 8
When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's
pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 28. Ports 2 and 3 Circuit Diagram
4–40
1, 4, 8
S3C7254
PRODUCT SPECIFICATION
PORT 4 CIRCUIT DIAGRAM
VDD
PNE3.2
PUR3
PNE3.1
PNE3.0
PM4.2
PM4.1
PM4.0
P4.0 /CLO
P4.1 /TCL0
OUTPUT
LATCH
1, 4
P4.2 /TCLO0
CMOS PUSH-PULL or
N-CHANNEL
OPEN-DRAIN
M
U
1, 4
X
NOTE:
When a port pin serves as an output, its pull-up resistor is automatically disabled, even
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register
(PUMOD).
Figure 29. Port 4 Circuit Diagram
4–41
PRODUCT SPECIFICATION
S3C7254
BASIC TIMER (BT)
The basic timer generates interrupt requests at
precise intervals, based on the frequency of the
system clock.
corresponds to the frequency selected by BMOD.
BCNT continues incrementing as it counts BT clocks
until an overflow occurs.
You can use the basic timer as a "watchdog" timer
for monitoring system events or use BT output to
stabilize clock oscillation when stop mode is
released by an interrupt and following RESET.
An overflow causes the BT interrupt request flag
(IRQB) to be set to logic one to signal that the
designated time interval has elapsed. An interrupt
request is then generated, BCNT is cleared to logic
zero, and counting continues from 00H.
Interval Timer Function
The measurement of elapsed time intervals is the
basic timer's primary function. The standard interval
is 256 BT clock pulses.
To restart the basic timer, set bit 3 of the mode
register BMOD to logic one. The input clock
frequency and the interrupt and stabilization interval
are selected by loading the appropriate bit values to
BMOD.2–BMOD.0.
The 8-bit counter register, BCNT, is incremented
each time a clock signal is detected that
Oscillation Stabilization Interval Control
Bits 2–0 of the BMOD register are used to select the
input clock frequency for the basic timer. This
setting also determines the time interval (also
referred to as 'wait time') required to stabilize clock
signal oscillation when power-down mode is
released by an interrupt. When a RESET signal is
generated, the standard stabilization interval for
system clock oscillation following a RESET is 31.3
ms at 4.19 MHz.
"CLEAR" SIGNAL
BITS
INSTRUCTION
CLEAR
BCNT
BMOD.3
BMOD.2
BCNT
BMOD.1
BMOD.0
INTERRUPT
REQUEST
OVERFLOW
CLOCK
4
IRQB
1-BIT R/W
SELECTOR
8
CLOCK INPUT
(fxx/212, fxx/29, fxx/27, fxx/25)
CPU CLOCK
START SIGNAL
(POWER-DOWN RELEASE)
Figure 30. Basic Timer Circuit Diagram
4–42
CLEAR
IRQB
S3C7254
PRODUCT SPECIFICATION
instruction, the contents of the BT counter register
(BCNT) and the BT interrupt request flag (IRQB) are
both cleared to logic zero, and timer operation is
restarted.
BASIC TIMER MODE REGISTER (BMOD)
The basic timer mode register, BMOD, is used to
select the input frequency and the oscillation
stabilization time.
The most significant bit of the BMOD register,
BMOD.3, is used to restart the basic timer. When
BMOD.3 is set to logic one (enabled) by a 1-bit write
Table 20. Basic Timer Mode Register (BMOD) Organization
BMOD.3
1
Basic Timer Restart Bit
Restart basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
BMOD.2
BMOD.1
BMOD.0
Basic Timer Input Clock
Oscillation Stabilization
0
0
0
fxx/212 (1.02 kHz)
220/fxx (250 ms)
0
1
1
fxx/29 (8.18 kHz)
217/fxx (31.3 ms)
1
0
1
fxx/27 (32.7 kHz)
215/fxx (7.82 ms)
1
1
1
fxx/25 (131 kHz)
213/fxx (1.95 ms)
NOTES:
1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fxx) of 4.19 MHz.
2. fxx = selected system clock frequency.
3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. The
data in the table column 'Oscillation Stabilization' can also be interpreted as "Interrupt Interval Time."
4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
BASIC TIMER COUNTER (BCNT)
BCNT is an 8-bit counter for the basic timer. It can
be addressed by 8-bit read instructions.
When BCNT has incremented to hexadecimal 'FFH'
(255 clock pulses), it is cleared to '00H' and an
overflow is generated. The overflow causes the
interrupt request flag, IRQB, to be set to logic one.
When the interrupt request is generated, BCNT
immediately resumes counting incoming clock
signals.
NOTE
Always execute a BCNT read operation
twice to eliminate the possibility of reading
unstable data while the counter is
incrementing. If, after two consecutive
reads, the BCNT values match, you can
select the latter value as valid data. Until
the results of the consecutive reads match,
however, the read operation must be
repeated until the validation condition is
met.
4–43
PRODUCT SPECIFICATION
S3C7254
+ PROGRAMMING TIP — Using the Basic Timer
1. To read the basic timer count register (BCNT):
BITS
EMB
SMB
15
BCNTR
LD
EA,BCNT
LD
YZ,EA
LD
EA,BCNT
CPSE
EA,YZ
JR
BCNTR
2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms:
BITS
SMB
LD
LD
STOP
NOP
NOP
CPU
OPERATION
EMB
15
A,#0BH
BMOD,A
; Wait time is 31.3 ms
; Set stop power-down mode
NORMAL
OPERATING MODE
STOP MODE
IDLE MODE
NORMAL
OPERATING MODE
(31.3 ms)
STOP
INSTRUCTION
STOP MODE IS
RELEASED BY
INTERRUPT
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):
BITS
SMB
LD
LD
EI
BITS
EMB
15
A,#0FH
BMOD,A
IEB
; Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer:
BITS
SMB
BITS
4–44
EMB
15
BMOD.3
S3C7254
PRODUCT SPECIFICATION
8-BIT TIMER/COUNTER 0 (TC0)
An 8-bit mode register, TMOD0, is used to activate
the timer/counter and to select the basic clock
frequency to be used for timer/counter operations.
To dynamically modify the basic frequency, new
values can be loaded into the TMOD0 register
during program execution.
OVERVIEW
Timer/counter 0 (TC0) is used to count system
'events' by identifying the transition (high-to-low or
low-to-high) of incoming square wave signals. To
indicate that an event has occurred, or that a
specified time interval has elapsed, TC0 generates
an interrupt request. By counting signal transitions
and comparing the current counter value with the
reference register value, TC0 can be used to
measure specific time intervals.
TC0 has a reloadable counter that consists of two
parts: an 8-bit reference register (TREF0) into which
you write the counter reference value, and an 8-bit
counter register (TCNT0) whose value is
automatically incremented by counter logic.
Timer/counter 0 can supply a clock signal to the
clock selector circuit of the serial I/O interface for
data shifter and clock counter operations. (These
internal SIO operations are controlled in turn by the
SIO mode register, SMOD). This clock generation
function enables you to adjust data transmission
rates across the serial interface.
CLOCKS
10
(fxx/2 , fxx/2 6, fxx/2 4, fxx)
TCL0
8
8
TMOD0.7
8
TMOD0.6
TCNT0
8-BIT
COMPARATOR
CLOCK
SELECTOR
TMOD0.5
TREF0
TMOD0.4
CLEAR
TMOD0.3
TMOD0.2
TMOD0.1
TMOD0.0
CLEAR
INVERTED
SET
CLEAR
IRQT0
TOL0
SERIAL
I/O
TCLO0
PM4.2
P4.2 LATCH
TOE0
Figure 31. TC0 Circuit Diagram
4–45
PRODUCT SPECIFICATION
S3C7254
TC0 PROGRAMMABLE TIMER/COUNTER
FUNCTION
mechanism for TC0 includes an interrupt enable flag
(IET0) and an interrupt request flag (IRQT0).
Timer/counter 0 can be programmed to generate
interrupt requests at various intervals based on the
selected system clock frequency. Its 8-bit TC0 mode
register TMOD0 is used to activate the timer/counter
and to select the clock frequency.
TC0 EVENT COUNTER FUNCTION
Timer/counter 0 can monitor or detect system
'events' by using the external clock input at the
TCL0 pin as the counter source. The TC0 mode
register selects rising or falling edge detection for
incoming clock signals. The counter register TCNT0
is incremented each time the selected state
transition of the external clock signal occurs.
The reference register TREF0 stores the value for
the number of clock pulses to be generated between
interrupt requests. The counter register, TCNT0,
counts the incoming clock pulses, which are
compared to the TREF0 value as TCNT0 is
incremented. When there is a match (TREF0 =
TCNT0), an interrupt request is generated.
With the exception of the different TMOD0.4–
TMOD0.6 settings, the operation sequence for TC0's
event counter function is identical to its
programmable timer/counter function. To activate
the TC0 event counter function, P4.1/TCL0 must be
set to input mode.
To generate an interrupt request, the TC0 interrupt
request flag (IRQT0) is set to logic one, the status of
TOL0 is inverted, and the interrupt is generated. The
content of TCNT0 is then cleared to 00H and TC0
continues counting. The interrupt request
.
Table 20-1. TMOD0 Settings for TCL0 Edge Detection
TMOD0.5
TMOD0.4
TCL0 Edge Detection
0
0
Rising edges
0
1
Falling edges
TC0 CLOCK FREQUENCY OUTPUT
Using timer/counter 0, a modifiable clock frequency
can be output to the TC0 clock output pin, TCLO0.
To select the clock frequency, load the appropriate
values to the TC0 mode register, TMOD0. The clock
interval is selected by loading the desired reference
value into the reference register TREF0. To enable
the output to the TCLO0 pin, the following conditions
must be met:
— TC0 output enable flag TOE0 must be set to "1"
— I/O mode flag for P4.2 must be set to output
mode ("1")
— Output latch value for P4.2 must be set to "0"
+ PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin:
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
4–46
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
EA,#40H
PMG1,EA
P4.2
TOE0
; P4.2 ← output mode
; P4.2 clear
S3C7254
PRODUCT SPECIFICATION
counting starts from 00H, and TMOD0.3 is
automatically reset to "0" for normal TC0 operation.
When TC0 operation stops (TMOD0.2 = "0"), the
contents of the TC0 counter register TCNT0 are
retained until TC0 is re-enabled.
TC0 MODE REGISTER (TMOD0)
TMOD0 is the 8-bit mode control register for
timer/counter 0. TMOD0.2 is the enable/disable bit
for timer/counter 0. When TMOD0.3 is set to "1", the
contents of TCNT0, IRQT0, and TOL0 are cleared,
Table 21. TC0 Mode Register (TMOD0) Organization
Bit Name
Setting
TMOD0.7
0
Resulting TC0 Function
Address
Always logic zero
TMOD0.6
F91H
TMOD0.5
0,1
Specify input clock edge and internal frequency
TMOD0.4
TMOD0.3
1
Clear TCNT0, IRQT0, and TOL0 and resume counting
immediately (This bit is automatically cleared to logic zero
immediately after counting resumes.)
TMOD0.2
0
Disable timer/counter 0; retain TCNT0 contents
1
Enable timer/counter 0
TMOD0.1
0
Always logic zero
TMOD0.0
0
Always logic zero
F90H
Table 22. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings
TMOD0.6
TMOD0.5
TMOD0.4
Resulting Counter Source and Clock Frequency
0
0
0
External clock input (TCL0) on rising edges
0
0
1
External clock input (TCL0) on falling edges
1
0
0
fxx/210 (4.09 kHz)
1
0
1
fxx /26 (65.5 kHz)
1
1
0
fxx/24 (262 kHz)
1
1
1
fxx = 4.19 MHz
NOTE: 'fxx' = selected system clock of 4.19 MHz.
+ PROGRAMMING TIP — Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz:
BITS
SMB
LD
LD
EI
BITS
EMB
15
EA,#4CH
TMOD0,EA
IET0
2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:
BITS
SMB
BITS
EMB
15
TMOD0.3
4–47
PRODUCT SPECIFICATION
S3C7254
TC0 REFERENCE REGISTER (TREF0)
TREF0 is used to store a reference value to be
compared to the incrementing TCNT0 register in
order to identify an elapsed time interval. Use the
following formula to calculate the correct value to
load to the TREF0 reference register:
1
TC0 timer interval = (TREF0 value + 1) × TMOD0 frequency setting
(TREF0 value≠0)
TC0 OUTPUT ENABLE FLAG (TOE0)
The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin.
(MSB)
F92H
“0”
(LSB)
TOE0
"0"
"0"
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin.
+ PROGRAMMING TIP — Setting a TC0 Timer Interval
To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps.
1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter
clock = fxx/210, and TREF0 is set to FFH):
2. Calculate the TREF0 value:
30 ms =
TREF0 value + 1
4.09 kHz
TREF0 + 1 =
30 ms
244 µs
= 122.9 = 7AH
TREF0 value = 7AH – 1 = 79H
3. Load the value 79H to the TREF0 register:
BITS
SMB
LD
LD
LD
LD
4–48
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
S3C7254
PRODUCT SPECIFICATION
WATCH TIMER
Watch timer functions include real-time and watchtime measurement and interval timing for the main
and subsystem clock. It is also used as a clock
source for the LCD controller and for generating
buzzer (BUZ) output.
the subsystem clock as the oscillation source during
stop mode, the watch timer can set the interrupt
request flag IRQW to "1", thereby releasing stop
mode.
Clock Source Generation for LCD Controller
Real-Time and Watch-Time Measurement
To start watch timer operation, set bit 2 of the watch
timer mode register (WMOD.2) to logic one. The
watch timer starts, the interrupt request flag IRQW is
automatically set to logic one, and interrupt requests
commence in 0.5-second intervals.
The watch timer supplies the clock frequency for the
LCD controller (fLCD). Therefore, if the watch timer
is disabled, the LCD controller does not operate.
Buzzer Output Frequency Generator
Since the watch timer functions as a quasi-interrupt
instead of a vectored interrupt, the IRQW flag
should be cleared to logic zero by program software
as soon as a requested interrupt service routine has
been executed.
The watch timer can generate a steady 2 kHz, 4
kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To
select the desired BUZ frequency , load the
appropriate value to the WMOD register. This output
can then be used to actuate an external buzzer
sound. To generate a BUZ signal, three conditions
must be met:
Using a Main System or Subsystem Clock
Source
— The WMOD.7 register bit is set to "1"
The watch timer can generate interrupts based on
the main system clock frequency or on the
subsystem clock. When the zero bit of the WMOD
register is set to "1", the watch timer uses the
subsystem clock signal (fxt) as its source; if
WMOD.0 = "0", the main system clock (fx) is used
as the signal source, according to the following formula:
Main system clock (fx)
128
= 32.768 kHz (fx = 4.19 MHz)
Watch timer clock (fw) =
This feature is useful for controlling timer-related
operations during stop mode. When stop mode is
engaged, the main system clock (fx) is halted, but
the subsystem clock continues to oscillate. By using
— The output latch for I/O port 0.3 is cleared to "0"
— The port 0.3 output mode flag (PM0.3) set to
'output' mode
Timing Tests in High-Speed Mode
By setting WMOD.1 to "1", the watch timer will
function in high-speed mode, generating an interrupt
every 3.91 ms. At its normal speed (WMOD.1 = '0'),
the watch timer generates an interrupt request every
0.5 seconds. High-speed mode is useful for timing
events for program debugging sequences.
Check Subsystem Clock Level Feature
The watch timer can also check the input level of
the subsystem clock by testing WMOD.3. If
WMOD.3 is "1", the input level at the XTin pin is
high; if WMOD.3 is "0", the input level at the XTin
pin is low.
4–49
PRODUCT SPECIFICATION
S3C7254
P0.3 LATCH
PM0.3
WMOD.7
WMOD.6
BUZ
WMOD.5
MUX
WMOD.4
8
fw/16 (2 kHz)
WMOD.3
fw/8 (4 kHz)
fw/4 (8 kHz)
ENABLE / DISABLE
fw/2 (16 kHz)
WMOD.2
SELECTOR
CIRCUIT
WMOD.1
IRQW
WMOD.0
fw/2 7
CLOCK
SELECTOR
fw
32.768 kHz
fw/214 (2 Hz)
FREQUE NCY
DIVIDING
CIRCUIT
f LCD
fxt
fx/128
fx = MAIN SYSTEM CLOCK (4.19 MHz)
fxt = SUBSYSTEM CLOCK (32.768 KHz)
fw = WATCH TIMER FREQUENCY
Figure 32. Watch Timer Circuit Diagram
4–50
S3C7254
PRODUCT SPECIFICATION
WATCH TIMER MODE REGISTER (WMOD)
The watch timer mode register WMOD is used to select specific watch timer operations.
Table 23. Watch Timer Mode Register (WMOD) Organization
Bit Name
Values
WMOD.7
WMOD.6
WMOD.5 – .4
Function
0
Disable buzzer (BUZ) signal output
1
Enable buzzer (BUZ) signal output
0
Always logic zero
0
0
2 kHz buzzer (BUZ) signal output
0
1
4 kHz buzzer (BUZ) signal output
1
0
8 kHz buzzer (BUZ) signal output
1
1
16 kHz buzzer (BUZ) signal output
WMOD.3
WMOD.2
WMOD.1
WMOD.0
0
Input level to XTin pin is low
1
Input level to XTin pin is high
0
Disable watch timer; clear frequency dividing circuits
1
Enable watch timer
0
Normal mode; sets IRQW to 0.5 seconds
1
High-speed mode; sets IRQW to 3.91 ms
0
Select (fx/128 ) as the watch timer clock (fw)
1
Select subsystem clock as watch timer clock (fw)
Address
F89H
F88H
NOTE: Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock (fxt) is assumed to be 32.768 kHz.
+ PROGRAMMING TIP — Using the Watch Timer
1. Select a subsystem clock as the LCD display clock, a 0.5 second interrupt, and 2 kHz buzzer enable:
BITS
SMB
LD
LD
BITR
LD
LD
BITS
EMB
15
EA,#8H
PMG1,EA
P0.3
EA,#85H
WMOD,EA
IEW
; P0.3 ← output mode
2. Sample real-time clock processing method:
CLOCK
BTSTZ
RET
•
•
•
IRQW
; 0.5 second check
; No, return
; Yes, 0.5 second interrupt generation
; Increment HOUR, MINUTE, SECOND
4–51
PRODUCT SPECIFICATION
S3C7254
LCD CONTROLLER/DRIVER
The S3C7254 microcontroller can directly drive an
up-to-320–dot (40 segments x 8 commons) LCD
panel.
Data written to the LCD display RAM can be
transferred to the segment signal pins automatically
without program control.
When a subsystem clock is selected as the LCD
clock source, the LCD display is enabled even
during main clock stop and idle modes.
COM0
b0
COM1
b1
COM2
b2
COM3
b3
COM4
b0
COM5
b1
COM6
b2
COM7
b3
S
E
G
0
S
E
G
1
1B0H
1B2H
LCD RAM ADDRESS AREA
RAM addresses of bank 1 are used as LCD data
memory. These locations can be addressed by 1-bit,
4-bit, or 8-bit instructions. When the bit value of a
display segment is "1", the LCD display is turned on;
when the bit value is "0", the display is turned off.
Display RAM data are sent out through segment
pins SEG0–SEG40 using a direct memory access
(DMA) method that is synchronized with the fLCD
signal. RAM addresses in this location that are not
used for LCD display can be allocated to generalpurpose use.
S
E
G
2
S
E
G
3
8
1B4H
S
E
G
3
9
1FCH
1FEH
1FDH
1FFH
......
1B1H
1B3H
1B5H
Figure 33. LCD Display Data RAM Organization
Table 24. Common and Segment Pins per Duty Cycle
Duty
Common Pins
Segment Pins
Dot Number
1/8
COM0–COM7
32–40 pins
256 dots–320 dots
1/4
COM0–COM3
128 dots–160 dots
1/3
COM0–COM2
96 dots–120 dots
1-BIT OUTPUT
The eight output pins (P5.0-P5.7) of the 40-segment output pins can be set in 4 bits for 1-bit level output by
LMOD.6 and LMOD.7. At this time, the bit 0 of the even addressed display RAM is used as the output latch of 1bit output pins. The 1F0H.0 in LCD display RAM is used as the output latch for P5.0, 1F2H.0 is for P5.1,…… and
1FEH.0 is for P5.7. These 1-bit output pins cannot be used as 4 bits and 8 bits.
4–52
S3C7254
PRODUCT SPECIFICATION
LCD CIRCUIT DIAGRAM
SEG39 / P5.7
SEG32 / P5.0
DISPLAY
RAM
(BANK"1")
80
40
MUX
SELECTOR
SEG31
SEG0
DATA BUS
f LCD
COM7
LMOD
TIMING
CONTROLLER
COM
CONTROL
COM0
LCD
VOLTAGE
CONTROL
LCON
VLC5
VLC1
L CDSY
L CDCK
P3.3 LATCH
P3.2 LATCH
PM3.3
PM3.2
Figure 34. LCD Circuit Diagram
4–53
PRODUCT SPECIFICATION
S3C7254
LCD CONTROL REGISTER (LCON)
The LCD control register (LCON) is used to turn the
LCD display on and off, to output LCD clock
(LCDCK) and synchronizing signal (LCDSY) for LCD
display expansion, and to control the flow of current
to dividing resistors in the LCD circuit. The effect of
the LCON.0 setting is dependent upon the current
setting of bits LMOD.0 and LMOD.1.
Table 25. LCD Control Register (LCON) Organization
LCON Bit
Setting
LCON.3
0
1/4 bias select
1
1/3 bias select
0
Disable LCDCK and LCDSY signal outputs.
1
Enable LCDCK and LCDSY signal outputs.
LCON.2
LCON.1, LCON.0
Description
0,0
LCD display off
1,0
LCD display on when using an external resistor for contrast control.
1,1
LCD display on when not using an external resistor for contrast control.
NOTES:
1. In case of LCON.0, you should turn on/off ‘LCD display’ using internal resistor. If you want to turn on/off LCD or to
control ‘LCD contrast’’ internally, you should set the LCON.0 to “0”.
2. To select LCD bias, you must use both the LCON.3 setting and an external LCD bias circuit connection.
3. If you turn the LCD display off (LCON.0 = "0"), you reduce the current flowing through the LCD dividing resistorrs.
Table 26. LMOD.1–0 Bits Settings
LMOD.1–LMOD.0
4–54
COM0–COM 7
SEG0–SEG39
0, 0
All of the LCD dots off
0, 1
All of the LCD dots on
1, 0
Common and segment signal
output corresponds to display data
(normal display mode)
SEG32/P5.0–SEG39/P5.7
Power Supply to the
Dividing Resistor
1-bit output function
On
S3C7254
PRODUCT SPECIFICATION
the watch timer clock (fw), the watch timer must
be enabled when the LCD display is turned on.
LCD MODE REGISTER (LMOD)
The LCD mode control register LMOD is used to
control display mode; LCD clock, segment or port
output, and display on/off. LMOD can be
manipulated using 8-bit write instructions.
The LCD display can continue to operate during idle
and stop modes if a subsystem clock is used as the
watch timer source. The LCD mode register LMOD
controls the output mode of the 8 pins used for
normal outputs (P5.0–P5.7). Bits LMOD.7–5 define
the segment output and normal bit output
configuration.
The LCD clock signal, LCDCK, determines the
frequency of COM signal scanning of each segment
output. This is also referred to as the 'frame
frequency. Since LCDCK is generated by dividing
Table 27. LCD Clock Signal (LCDCK) Frame Frequency
LCDCK
128 Hz
256 Hz
512 Hz
1024 Hz
2048 Hz
4096 Hz
1/8
–
–
64 Hz
128 Hz
256 Hz
512 Hz
1/4
–
64 Hz
128 Hz
256 Hz
512 Hz
–
1/3
42.7 Hz
85.3 Hz
170.7 Hz
341.3 Hz
–
–
Display Duty Cycle
NOTE: fw = 32.768 kHz
COM0
1 FRAME
4–55
PRODUCT SPECIFICATION
S3C7254
Table 28. LCD Mode Register (LMOD) Organization
Segment /Output Port Selection Bits
LMOD.7
LMOD.6
SEG39–36
SEG35–32
Total Number
of Segment
0
0
SEG port
SEG port
40
0
1
SEG port
Output port
36
1
0
Output port
SEG port
36
1
1
Output port
Output port
32
LCD Clock Selection Bits
LMOD.5
LMOD.4
LCD Clock (LCDCK)
1/8 duty (COM0–COM7)
1/4 duty (COM0–COM3)
1/3 duty (COM0–COM2)
0
0
fw/ 26 (512 Hz)
fw/ 27 (256 Hz)
fw/ 28 (128 Hz)
0
1
fw/ 25 (1024 Hz)
fw/ 26 (512 Hz)
fw/ 27 (256 Hz)
1
0
fw/ 24 (2048 Hz)
fw/ 25 (1024 Hz)
fw/ 26 (512 Hz)
1
1
fw/ 23 (4096 Hz)
fw/ 24 (2048 Hz)
fw/ 25 (1024 Hz)
NOTE: LCDCK is supplied only when the watch timer operates. To use the LCD controller, bit 2 in the watch mode register
WMOD should be set to 1.
Duty Selection Bits
LMOD.3
LMOD.2
Duty
0
0
1/8 duty (COM0–COM7 select)
1
0
1/4 duty (COM0–COM3 select)
1
1
1/3 duty (COM0–COM2 select)
Display Mode Selection Bits
LMOD.1
LMOD.0
0
0
All LCD dots off
0
1
All LCD dots on
1
0
Normal display
4–56
Function
S3C7254
PRODUCT SPECIFICATION
LCD VOLTAGE DIVIDING RESISTORS
On-chip voltage dividing resistors for the LCD drive
power supply can be configured by mask option to
1/4 Bias
S3C7254
KS57C2504
the VLC1–VLC5 pins. Power can be supplied without
an external dividing resistor. Figure 12–4 shows the
bias connections for the S3C7254 LCD drive power
supply.
1/3 Bias
VLC1
S3C7254
KS57C2504
VLC1
VLC2
VLC2
VLC3
VLC3
VLC4
VLC4
VLC5
VLC5
Figure 35. LCD Bias Circuit Connection
4–57
PRODUCT SPECIFICATION
S3C7254
APPLICATION WITHOUT CONTRAST CONTROL
peripheral circuits are simple. But in that case, you
can't control LCD contrast.
If you use an internal transistor (LCON.0) to turn
on/off 'LCD display', you can get a merit that
Application With Internal Resistor
S3C7254
KS57C2504
Application With External resistor
S3C7254
KS57C2504
VDD
VDD
VDD
MASK
OPTION
VLC1
VLC1
VLC2
VLC2
VLC3
VLC3
VLC4
VLC4
VLC5
VLC5
VLCD
LCON.0(3)
LCON.0 (3)
VSS
VSS
VDD or VLCN
VDD or VLCN
N: 1, 2, 3, 4, 5
N: 1, 2, 3, 4, 5
LCON.1
LCON.1
COM & SEG LCD DATA OUT
LCD DATA OUT
VSS or VLCN
COM & SEG
VSS or VLCN
Figure 36. Connection For LCD On/Off Using Internal Transistor
NOTES:
1. A 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for Figure 35.
2. When you turn off the LCD display using LCON settings, the amount of current flowing through the dividing resistors
is reduced more than when you use LMOD to turn off the display.
3. When LCON.0–.1 = #00B, LCD display is turned off. When LCON.0–.1 = #11B, LCD display is turned on.
4–58
S3C7254
PRODUCT SPECIFICATION
APPLICATION WITH CONTRAST CONTROL
If you turn on/off 'LCD display' using external output pin, you can control LCD contrast using variable resistor.
Application With Internal Resistor
S3C7254
KS57C2504
Application With External resistor
S3C7254
KS57C2504
V DD
VDD
VDD
MASK
OPTION
VLC1
VLC1
VLC2
VLC2
VLC3
VLC3
VLC4
VLC4
VLC5
VLC5
VLCD
LCON.0
(Always "0")
VR
LCON.0
(Always "0")
Px.b (3)
VR
Px.b (3)
VSS
VSS
VDD or V LCN
V DD or VLCN
N: 1, 2, 3, 4, 5
N: 1, 2, 3, 4, 5
LCON. 1
LCON. 1
COM & SEG
LCD DATA OUT
V SS or V LCN
LCD DATA OUT
COM & SEG
VSS or VLCN
Figure 37. Connection For LCD On/Off Using External Output Pin
NOTES:
1. A 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for Figure 35.
2. When you turn off the LCD display using LCON settings, the amount of current flowing through the dividing resistors
is reduced more than when you use LMOD to turn off the display.
3. When LCON.0–.1 = #00B and Px.b = #1B, LCD display is turned off.
When LCON.0–.1 = #10B and Px.b = #0B, LCD display is turned on.
4–59
PRODUCT SPECIFICATION
S3C7254
COMMON (COM) SIGNALS
The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
— In 1/8 duty mode, COM0–COM7 pins are selected
— In 1/4 duty mode, COM0–COM3 pins are selected
— In 1/3 duty mode, COM0–COM2 pins are selected
SEGMENT (SEG) SIGNALS
The 40 LCD segment signal pins are connected to corresponding display RAM locations at bank 1. Bits of the
display RAM are synchronized with the common signal output pins.
When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.
When the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.
4–60
S3C7254
PRODUCT SPECIFICATION
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
V DD
V SS
FR
1 FRAME
V DD
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
V LC1
COM0
V LC2 (V LC3)
V LC4
V LC5
V DD
V LC1
COM1
V LC2 (V LC3)
V LC4
V LC5
V DD
V LC1
COM2
V LC2 (V LC3)
V LC4
V LC5
V DD
V LC1
SEG0
V LC2 (V LC3)
V LC4
V LC5
+ VLCD
+ 1/4 VLCD
SEG0–COM0
0V
- 1 /4 VLCD
- V LCD
Figure 38. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
4–61
PRODUCT SPECIFICATION
S3C7254
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FR
VDD
VSS
1 FRAME
V DD
SEG1
V LC1
V LC2 (V LC3 )
V LC4
V LC5
+ V LCD
SEG1–COM0
+1/4 V LCD
0V
-1/4 V LCD
–V LCD
Figure 39. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)
4–62
S3C7254
PRODUCT SPECIFICATION
SEG0
SEG1
CO M0
CO M1
CO M2
0
1
2
3
0
1
2
CO M3
3
VDD
1 FRAME
VSS
COM0
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
COM1
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
COM2
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
COM3
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
SEG0
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
SEG1
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
+ VLCD
+1/3 VLCD
0V
-1/3 VLCD
COM0–SEG0
- V LCD
Figure 40. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
4–63
PRODUCT SPECIFICATION
S3C7254
SEG2 SEG1 SEG0
COM0
COM1
COM2
0
1
2
0
1
2
VDD
1 FRAME
VSS
COM0
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
COM1
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
COM2
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
SEG0
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
SEG1
VDD
VLC1 (VLC2 )
VLC3 (VLC4 )
VLC5
+ V LCD
+1/3 VLCD
COM0–SEG0
0V
-1/3 V LCD
- V LCD
Figure 41. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
4–64
S3C7254
PRODUCT SPECIFICATION
COMPARATOR
P1.0 and P1.1 can be used as a analog input port
for a comparator. The reference voltage for the 2channel comparator can be supplied either internally
or externally at P1.0. When an internal reference
voltage is used, two channels (P1.0–P1.1) are used
for analog inputs and the internal reference voltage
is varied in 16 levels. If an external reference
voltage is input at P1.0, the other P1.1 pins are used
for analog input.
When a conversion is completed, the result is saved
in the comparison result register CMPREG. The
initial values of the CMPREG are undefined and the
comparator operation is disabled by a RESET. The
comparator module has the following components:
P1.0 /CIN0 /INT0
M
P1.1 /CIN1 /INT1
+
U
–
X
VREF
(EXTERNAL)
COMPARISON
RESULT
REGISTER
(CMPREG)
4
M
INTERNAL BUS
U
X
VDD
CMOD.7
CMOD.6
1/2R
CMOD.5
M
R
VREF
(INTERNAL)
U
R
0
8
CMOD.3
CMOD.2
X
CMOD.1
1/2R
CMOD.0
Note: INT occures only for digital input selecting: for analog input, any INT doesn't.
Figure 42. Comparator Circuit Diagram
4–65
PRODUCT SPECIFICATION
S3C7254
COMPARATOR MODE REGISTER (CMOD)
The comparator mode register CMOD is an 8-bit register that is used to select the operation mode of the
comparator.
CMOD.7 CMOD.6 CMOD.5
"0"
CMOD.3 CMOD.2 CMOD.1 CMOD.0
FD6H–FD7H
Reference voltage (V REF ) selection:
VDD x (n + 0.7)/16, n = 0 to 15
1: CIN0; external reference, CIN1; analog input
0: Internal reference, CIN0–1; analog input
1: Conversion time(4 x 24 /fx, 15.6 µs @4.19MHz)
0: Conversion time(4 x 27 /fx, 122.2 µs @4.19MHz)
1: Comparator operation enable
0: Comparator operation disable
Figure 43. Comparator Mode Register (CMOD) Organization
4–66
S3C7254
PRODUCT SPECIFICATION
PORT 1 MODE REGISTER (P1MOD)
P1MOD register settings determine if P1.0 and P1.1
are used for analog or digital input. The P1MOD
register is 4-bit write-only register. P1MOD is
mapped to address FE2H. A reset operation
initializes all P1MOD register values to zero,
configuring P1.0 and P1.1 as a analog input port.
COMPARATOR OPERATION
The comparator compares analog voltage input at
CIN0-CIN1 with an external or internal reference
voltage (VREF) that is selected by the CMOD
register. The result is written to the comparison
result register CMPREG at address FD4H. The
comparison result at internal reference is calculated
as follows:
If "1"
Analog input voltage >=VREF + 150 mV
If "0"
Analog input voltage <= VREF – 150 mV
To obtain a comparison result, the data must be
read out from the CMPREG register after VREF is
updated by changing the CMOD value after a
conversion time has elapsed.
ANALOG INPUT
VOLTAGE (CIN0–1)
REFERENCE
VOLTAGE (V REF )
COMPARISON TIME
(CMPCLK x 4)
COMPARATOR CLOCK
(CMPCLK, fx/16, fx/128)
COMPARISON
START
COMPARISON
END
COMPARISON
RESULT (CMPREG)
UNKNOWN
1
1
0
Figure 44. Conversion Characteristics
+ PROGRAMMING TIP — Programming the Comparator
The following code converts the analog voltage input at the CIN0–CIN1 pins into 4-bit digital code.
WAIT
BITR
LD
LD
LD
EMB
A,#3H
P1MOD,A
EA,#0CXH
LD
LD
INCS
JR
LD
LD
CMOD,EA
A,#0H
A
WAIT
A,CMPREG
P2,A
; Analog input selection (CIN0–CIN1)
; x = 0–F, comparator enable
; Internal reference, conversion time (15.6 µs at 4.19 MHz)
; Read the result
; Output the result from port 2
4–67
PRODUCT SPECIFICATION
S3C7254
SERIAL I/O INTERFACE
The serial interface can run off an internal or an
external clock source, or the TOL0 signal that is
generated by the 8-bit timer/counter, TC0. If the
TOL0 clock signal is used, you can modify its
frequency to adjust the serial data transmission rate.
Using the serial I/O interface, 8-bit data can be
exchanged with an external device. The
transmission frequency is controlled by making the
appropriate bit settings to the SMOD register.
INTERNAL BUS
8
LSB or MSB first
SO
SI
SBUF (8-BIT)
R
Q
IRQS
D
CK
OVERFLOW
P0.0 /SCK
TOL0
CPU CLK
fxx/210
Q0
CLOCK
SELECTOR
Q1
Q2
3-BIT COUNTER
R
Q
S
CLEAR
fxx/24
SMOD.7
SMOD.6
SMOD.5
—
SMOD.3
SMOD.2
SMOD.1
8
BITS *
INTERNAL BUS
* INSTRUCTION EXCUTION
Figure 45. Serial I/O Interface Circuit Diagram
4–68
SMOD.0
S3C7254
PRODUCT SPECIFICATION
SERIAL I/O MODE REGISTER (SMOD)
The serial I/O mode register, SMOD, is an 8-bit
register that specifies the operation mode of the
serial interface. Its reset value is logical zero.
SMOD is organized in two 4-bit registers, as follows:
SMOD register settings enable you to select either
MSB-first or LSB-first serial transmission, and to
operate in transmit-and-receive mode or receive-
only mode. SMOD is a write-only register and can
be addressed only by 8-bit RAM control instructions.
One exception to this is SMOD.3, which can be
written by a 1-bit RAM control instruction. When
SMOD.3 is set to 1, the contents of the serial
interface interrupt request flag, IRQS, and the 3-bit
serial clock counter are cleared, and SIO operations
are initiated. When the SIO transmission starts,
SMOD.3 is cleared to logical zero.
Table 29. SIO Mode Register (SMOD) Organization
0
Most significant bit (MSB) is transmitted first
1
Least significant bit (LSB) is transmitted first
0
Receive-only mode
1
Transmit-and-receive mode
0
Disable the data shifter and clock counter; retain contents of IRQS flag when serial
transmission is halted
1
Enable the data shifter and clock counter; set IRQS flag to "1" when serial
transmission is halted
SMOD.3
1
Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset
this bit to logic zero
SMOD.4
0
Bit not used; value is always "0"
SMOD.7
SMOD.6
SMOD.5
0
0
0
External clock at SCK pin
0
0
1
Use TOL0 clock from TC0
0
1
x
CPU clock: fxx/4, fxx/8, fxx/64
Enable SBUF read/write
1
0
0
4.09 kHz clock: fxx/210
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
1
1
1
262 kHz clock: fxx/24
SMOD.0
SMOD.1
SMOD.2
Clock Selection
R/W Status of SBUF
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
NOTES:
1. 'fxx' = system clock; 'x' means 'don't care.'
2. kHz frequency ratings assume a system clock (fxx) running at 4.19 MHz.
3. The SIO clock selector circuit cannot select a fxx/24 clock if the CPU clock is fxx/64.
4–69
PRODUCT SPECIFICATION
S3C7254
SERIAL I/O TIMING DIAGRAMS
SCK
SI
SO
DI7
DO7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 46. SIO Timing in Transmit/Receive Mode
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI0
HIGH IMPEDANCE
SO
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 47. SIO Timing in Receive-Only Mode
4–70
DI1
S3C7254
PRODUCT SPECIFICATION
+ PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O
1.
Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fxx/24
and in MSB-first mode:
BITS
SMB
LD
LD
LD
LD
LD
LD
EMB
15
EA,#03H
PMG1,EA
EA,#48H
SBUF,EA
EA,#0EEH
SMOD,EA
; P0.0 / SCK and P0.1 / SO ← Output
;
;
; SIO data transfer
SCK / P0.0
EXTERNAL
DEVICE
SO / P0.1
S3C7254
2. Use CPU clock to transfer and receive serial data at high speed:
STEST
BITR
LD
LD
LD
LD
LD
LD
BITR
BTSTZ
JR
LD
LD
EMB
EA,#03H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#4FH
SMOD,EA
IES
IRQS
STEST
EA,SBUF
RDATA,EA
; P0.0 / SCK and P0.1 / SO ← Output, P0.2 / SI ← Input
; TDATA address = BANK0 (20H–7FH)
; SIO start
; RDATA address = BANK0 (20H–7FH)
4–71
PRODUCT SPECIFICATION
S3C7254
+ PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode:
INTS
BITR
LD
LD
LD
LD
LD
LD
EI
BITS
.
.
PUSH
PUSH
BITR
LD
EMB
EA,#03H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#8FH
SMOD,EA
XCH
LD
BITS
POP
POP
IRET
EA,SBUF
RDATA,EA
SMOD.3
EA
SB
; P0.0 / SCK and P0.1 / SO ← Output, P0.2/SI ← Input
; TDATA address = BANK0 (20H–7FH)
; SIO start
IES
SB
EA
EMB
EA,TDATA
; Store SMB, SRB
; Store EA
;
;
;
;
;
EA ← Transmit data,
TDATA address = BANK0 (20H–7FH)
Transmit data ↔ Receive data
RDATA address = BANK0 (20H–7FH)
SIO start
SCK / P0.0
SO / P0.1
SI / P0.2
S3C7254
4–72
EXTERNAL
DEVICE
S3C7254
PRODUCT SPECIFICATION
+ PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
4. Transmit and receive an external clock in LSB-first mode:
INTS
BITR
LD
LD
LD
LD
LD
LD
EI
BITS
.
.
PUSH
PUSH
BITR
LD
EMB
EA,#02H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#0FH
SMOD,EA
XCH
LD
BITS
POP
POP
IRET
EA,SBUF
RDATA,EA
SMOD.3
EA
SB
; P0.1 / SO ← Output, P0.0 / SCK and P0.2 / SI ← Input
; TDATA address = BANK0 (20H–7FH)
; SIO start
IES
SB
EA
EMB
EA,TDATA
; Store SMB, SRB
; Store EA
;
;
;
;
;
EA ← Transmit data,
TDATA address = BANK0 (20H–7FH)
Transmit data ← Receive data
RDATA address = BANK0 (20H–7FH)
SIO start
SCK / P0.0
SO / P0.1
EXTERNAL
DEVICE
SI / P0.2
S3C7254
High Speed SIO Transmission
4–73
PRODUCT SPECIFICATION
S3C7254
ELECTRICAL DATA
Table 30. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
VDD
–
– 0.3 to + 7.0
V
Input Voltage
VI1
– 0.3 to VDD + 0.3
V
Output Voltage
VO
– 0.3 to VDD + 0.3
V
Output Current High
IOH
One I/O port active
– 15
mA
All I/O ports active
– 30
One I/O port active
+ 30 (Peak value)
Output Current Low
IOL
All I/O ports
–
mA
+ 15 note
All I/O port, total
+ 100 (Peak value)
+ 60 note
Operating Temperature
Storage Temperature
TA
–
– 40 to + 85
°C
Tstg
–
– 65 to + 150
°C
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ×
4–74
Duty .
S3C7254
PRODUCT SPECIFICATION
Table 31. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Input High
Voltage
Input Low
Voltage
Output High
Voltage
Output Low
Voltage
Symbol
Conditions
Min
Typ
Max
Units
V
VIH1
Ports 2, 3, P4.0 and P4.2
0.7 VDD
–
VDD
VIH2
Ports 0, 1, P4.1 and RESET
0.8 VDD
–
VDD
VIH3
XIN, XOUT and XTIN
VDD – 0.5
–
VDD
VIL1
Ports 2, 3, P4.0 and P4.2
–
–
0.3 VDD
VIL2
Ports 0, 1, P4.1 and RESET
–
–
0.2 VDD
VIL3
XIN, XOUT and XTIN
–
–
0.4
VOH1
VDD = 4.5 V to 6.0 V
IOH = – 3 mA
Ports 0, 2, 3 and 4
VDD – 2.0
VDD – 0.4
–
VOH2
VDD = 4.5 V to 6.0 V
IOH = – 100 µA
Port 5
VDD – 2.0
–
–
VOL1
VDD = 4.5 V to 6.0 V
IOL = 15 mA
Ports 0, 2, 3 and 4
–
0.4
2
VOL2
VDD = 4.5 V to 6.0 V
IOL = 100 µA
Port 5
–
–
1
V
V
V
4–75
PRODUCT SPECIFICATION
S3C7254
Table 31. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Symbol
Input High
Leakage Current
ILIH1
Input Low
Leakage Current
Conditions
Min
Typ
Max
Units
VIN = VDD
All input pins except those
specified below for ILIH2
–
–
3
µA
ILIH2
VIN = VDD
XIN, XOUT and XTIN
–
–
20
µA
ILIL1
VIN = 0 V
All input pins except XIN, XOUT,
–
–
–3
XTIN and RESET
ILIL2
VIN = 0 V
XIN, XOUT, and XTIN
–
–
– 20
Output High
Leakage Current
ILOH
VO = VDD
All output pins
–
–
3
Output Low
Leakage Current
ILOL
VO = 0 V
All output pins
–
–
–3
Pull-Up Resistor
RL1
VIN = 0 V; VDD = 5 V ± 10%
Ports 0–4
15
40
80
VDD = 3 V ± 10%
30
80
200
VIN = 0 V; VDD = 5 V ± 10%
150
220
350
300
400
800
40
55
90
ΚΩ
mV
RL2
µA
ΚΩ
ΚΩ
RESET
VDD = 3 V ± 10%
LCD Voltage
Dividing Resistor
RLCD
IVDD-COMi I
VDC
VDD = 2.7 V to 6.0 V
– 15 µA per common pin
–
–
120
VDS
VDD = 2.7 V to 6.0 V
– 15 µA per segment pin
–
–
120
VLC1 output
voltage
VLC1
VDD = 3.5 V to 6.0 V (1)
LCD clock = 0 Hz, VLC5 = 0 V
0.8 VDD –
0.15
0.8 VDD
0.8 VDD +
0.15
VLC2 output
voltage
VLC2
0.6 VDD –
0.15
0.6 VDD
0.6 VDD+
0.15
VLC3 output
voltage
VLC3
0.4 VDD –
0.15
0.4 VDD
0.4 VDD+
0.15
VLC4 output
voltage
VLC4
0.2 VDD –
0.15
0.2 VDD
0.2 VDD +
0.15
voltage drop
(i = 0–7)
IVDD-SEGx I
voltage drop (x =
0–39)
4–76
–
V
S3C7254
PRODUCT SPECIFICATION
Table 31. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Supply (6)
Current
Symbol
IDD1 (2)
Conditions
VDD = 5 V ± 10% (3)
4.19 MHz crystal oscillator
Min
Typ
Max
Units
–
2.7
8
mA
0.27
1.2
1.2
1.8
0.26
1.0
VDD = 3 V ± 10% (4)
IDD2 (2)
Idle mode; VDD = 5 V ± 10%
4.19 MHz crystal oscillator
–
VDD = 3 V ± 10%
IDD3 (5)
VDD = 3 V ± 10%
32 kHz crystal oscillator
–
17
90
µA
IDD4 (5)
VDD = 3 V ± 10%
32 kHz crystal oscillator
–
6
15
µA
Stop mode; VDD = 5 V ± 10%
–
0.5
5
0.2
3
IDD5
VDD = 3 V ± 10%
NOTES:
1. 1/5 bias for test only. In 1/4 bias LCD operation mode, VDD condition is 2.7 V to 6.0 V.
2. Data includes power consumption for subsystem clock oscillation.
3. For high-speed controller operation, the power control register (PCON) must be set to 0011B.
4. For low-speed controller operation, the power control register (PCON) must be set to 0000B.
5. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
6. Currents in the following circuits are not included; on-chip pull-up resistors, output port drive currents, internal LCD voltage
dividing resistors, comparator.
4–77
PRODUCT SPECIFICATION
S3C7254
Table 32. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 2.7 V to 6.0 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Crystal
Oscillator
XIN
Parameter
Test Condition
Min
Typ
Max
Units
–
0.4
–
4.5
MHz
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum
oscillator voltage
range.
–
–
4
ms
Oscillation frequency
–
0.4
4.19
4.5
MHz
VDD = 4.5 V to 6.0 V
–
–
10
ms
VDD = 2.7 V to 4.5 V
–
–
30
XIN input frequency (1)
–
0.4
–
4.5
MHz
XIN input high and low
level width (tXH, tXL)
–
111
–
1250
ns
VDD = 5 V
0.4
—
2
MHz
VDD = 3 V
0.4
—
1
Oscillation frequency
(1)
C2
XOUT
C1
(1)
C2
Stabilization time (2)
External
Clock
RC
Oscillator
XIN
XIN
XOUT
XOUT
Frequency
R
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval time required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
4–78
S3C7254
PRODUCT SPECIFICATION
Table 33. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 2.7 V to 6.0 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XT IN
Parameter
Min
Typ
Max
Units
–
32
32.768
35
kHz
VDD = 4.5 V to 6.0
V
–
1.0
2
s
VDD = 2.7 V to 4.5
V
–
–
10
–
32
–
100
kHz
–
5
–
15
µs
Oscillation frequency
XT OUT
(1)
C1
C2
Stabilization time (2)
External
Clock
Test Condition
XT IN XT OUT
XTIN input frequency
(1)
XTIN input high and
low level width (tXTL,
tXTH)
NOTES:
1. Oscillation frequency and XTin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
RECOMMENDED OSCILLATOR CONSTANTS
Main System Clock: Ceramic Resonator (Ta = –40 °C – 85 °C)
Manufacturer
TDK
Product Name
FCR4.19MC5
Load Cap (pF)
Oscillator Voltage
Range (V)
C1
C2
MIN
MAX
–
–
2.7
6.0
Remarks
On-chip Capacitor:
30 pF±20%, Leaded Type
FCR4.19M5
33
33
2.7
6.0
Leaded Type
CCR4.19MC3
–
–
2.7
6.0
On-chip Capacitor:
30 pF±20%, Leaded Type
100
100
2.7
6.0
SMD Type
CCR1000K2
4–79
PRODUCT SPECIFICATION
S3C7254
Table 34. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
—
—
15
pF
Output
Capacitance
COUT
—
—
15
pF
CIO
—
—
15
pF
I/O Capacitance
Table 35. Comparator Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 6.0 V)
Parameter
Input Voltage Range
Symbol
Condition
Min
Typ
Max
Units
–
–
0
–
VDD
V
Reference Voltage Range
VREF
0
VDD
Input Voltage Accuracy
VCIN
–
± 150
mV
ICIN, IREF
-3
3
µA
Input leakage Current
4–80
S3C7254
PRODUCT SPECIFICATION
Table 36. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Instruction Cycle
Time (NOTE)
TCL0 Input
Frequency
Symbol
tCY
f TI0, f TI1
Conditions
Min
Typ
Max
Units
VDD = 4.5 V to 6.0 V
0.95
–
64
µs
VDD = 2.7 V to 4.5 V
3.8
With subsystem clock (fxt)
114
122
125
0
–
1
MHz
275
kHz
–
–
µs
–
–
ns
–
–
ns
–
–
ns
–
–
ns
VDD = 4.5 V to 6.0 V
64
VDD = 2.7 V to 4.5V
TCL0 Input High,
Low Width
SCK Cycle Time
tTIH0, tTIL0 VDD = 4.5 V to 6.0 V
tTIH1, tTIL1
0.48
VDD = 2.7 V to 4.5 V
1.8
VDD = 4.5 V to 6.0 V
800
tKCY
External SCK source
Internal SCK source
950
VDD = 2.7 V to 4.5 V
3200
External SCK source
SCK High, Low
Width
tKH, tKL
Internal SCK source
3800
VDD = 4.5 V to 6.0 V
400
External SCK source
Internal SCK source
VDD = 2.7 V to 4.5 V
tKCY/2 –
50
1600
External SCK source
SI Setup Time to
SCK High
SI Hold Time to
SCK High
tSIK
tKSI
Internal SCK source
tKCY/2 –
150
External SCK source
100
Internal SCK source
150
External SCK source
400
Internal SCK source
400
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
4–81
PRODUCT SPECIFICATION
S3C7254
Table 36. A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Output Delay for
SCK to SO
Symbol
tKSO
Conditions
Min
Typ
Max
Units
–
–
300
ns
VDD = 4.5 V to 6.0 V
External SCK source
Internal SCK source
250
VDD = 2.7 V to 4.5 V
1000
External SCK source
Internal SCK source
Interrupt Input
High, Low Width
RESET Input Low
Width
1000
(See Note)
tINTH, tINTL INT0
tRSL
INT1, INT2, INT4, K0–K3
10
Input
10
–
–
µs
–
–
µs
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
CPU CLOCK
1.0475 MHz
1.00 MHz
750 kHz
500 kHz
250 kHz
8 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 48. Standard Operating Voltage Range
4–82
S3C7254
PRODUCT SPECIFICATION
Table 37. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
2.0
–
6.0
V
Data retention supply current
IDDDR
–
0.1
10
µA
Release signal set time
tSREL
–
–
µs
–
ms
Oscillator stabilization wait
time (1)
tWAIT
VDDDR = 2.0 V
–
0
Released by RESET
–
Released by interrupt
–
17
2
/ fx
(2)
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
4–83
PRODUCT SPECIFICATION
S3C7254
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 49. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
tSREL
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 50. Stop Mode Release Timing When Initiated By Interrupt Request
4–84
S3C7254
PRODUCT SPECIFICATION
0.8 VDD
0.2 VDD
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
Figure 51. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / fx
tXL
tXH
Xin
VDD
0.4 V
Figure 52. Clock Timing Measurement at Xin
1 / fxt
tXTL
tXTH
XTin
VDD – 0.5 V
0.4 V
Figure 53. Clock Timing Measurement at XTin
4–85
PRODUCT SPECIFICATION
S3C7254
1 / fTI
tTIL
tTIH
0.8 VDD
0.2 VDD
TCL0
Figure 54. TCL Timing
tRSL
RESET
0.2 VDD
Figure 55. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4
K0 to K3
tINTH
0.8 VDD
0.2 VDD
Figure 56. Input Timing for External Interrupts and Quasi-Interrupts
4–86
S3C7254
PRODUCT SPECIFICATION
tKCY
tKL
tKH
0.8 VDD
0.2 VDD
SCK
tSIK
tKSI
0.8 VDD
SI
INPUT DATA
0.2 VDD
tKSO
SO
OUTPUT DATA
Figure 57. Serial Data Transfer Timing
4–87
PRODUCT SPECIFICATION
S3C7254
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements. They do
not, however, represent guaranteed operating values.
50
VDD = 6.0 V
45
40
I OL (mA)
35
30
VDD = 4.5 V
25
20
15
10
5
0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
VOL (V)
Figure 58. IOL VS. VOL (Ports 0,2,3,4)
4–88
4.8
5.4
6.0
S3C7254
PRODUCT SPECIFICATION
14.67
VDD = 6.0 V
13.20
11.74
10.27
I OL (mA)
8.80
VDD = 4.5 V
7.34
5.87
4.40
2.93
1.467
0
0.45
0.9
1.35
1.8
2.25
2.7
3.15
3.6
4.05
4.5
4.8
5.4
6.0
VOL (V)
Figure 59. IOL VS. VOL (Port 5)
– 22
– 20
– 18
VDD = 6.0 V
– 16
I OH (mA)
– 14
– 12
– 10
VDD = 4.5 V
–8
–6
–4
–2
0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
V OH (V)
Figure 60. IOH VS. VOH (Ports 0,2,3,4)
4–89
PRODUCT SPECIFICATION
S3C7254
– 22
– 20
– 18
VDD = 6.0 V
– 16
IOH (mA)
– 14
– 12
– 10
VDD = 4.5 V
–8
–6
–4
–2
0
0.6
1.2
1.8
2.4
3.0
3.6
V OH (V)
Figure 61. IOH VS. VOH (Port 5)
4–90
4.2
4.8
5.4
6.0
S3C7254
PRODUCT SPECIFICATION
4000
3500
IDD (µA)
3000
2500
IDD1, fx/4
2000
1500
I DD1, fx/64
1000
I DD2, fx/64
500
0
1
2
3
4
5
6
7
8
V DD (V)
Figure 62. IDD VS. VDD
3000
2500
IDD1 (µA)
2000
5.5 V, fx/ 4
1500
5.5 V, fx/ 64
1000
500
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Frequency (MHz)
Figure 63. IDD1 VS. Frequency
4–91
PRODUCT SPECIFICATION
S3C7254
3000
2500
IDD1 (µA)
2000
VDD = 6 V
VDD = 5 V
1500
VDD = 4 V
1000
500
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Frequency (MHz)
Figure 64. IDD1 VS. Frequency VS. VDD
1600
1400
IDD2 (µA)
1200
1000
VDD = 6 V
800
VDD = 5 V
600
VDD = 4 V
400
200
0
0.5
1
1.5
2
2.5
3
Frequency (MHz)
Figure 65. IDD2 VS. Frequency VS. VDD
4–92
3.5
4
4.5
S3C7254
PRODUCT SPECIFICATION
300
250
IDD (µA)
200
150
100
IDD3
50
IDD4
0
2
3
4
5
6
7
VDD (V)
Figure 66. IDD3, IDD4 VS. VDD
4–93
PRODUCT SPECIFICATION
Frequency (MHz)
S3C7254
(VDD = 5 V)
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0
50
100
150
200
Resistor (kΩ)
Figure 68. Frequency (fx) VS. Resistor
4–94
250
300