S5N8952X ADSL Transceiver for NIC Preliminary Information (Revision 2.0) September. 2000 SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY Copyright ©1999-2000 Samsung Electronics, Inc. All Rights Reserved S5N8952X ADSL Transceiver for NIC Contents 1. 2. 3. 4. 5. 6. 7. 8. 9. Features.......................................................................................................... 5 General Description........................................................................................... 5 Logical Symbol Diagram .................................................................................... 6 Pin Configuration.............................................................................................. 7 Pin Description ................................................................................................. 8 Functional Description..................................................................................... 13 I/O Timing Description..................................................................................... 14 Electrical Characteristics.................................................................................. 16 Package Description........................................................................................ 17 2 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC List of Figures Figure Figure Figure Figure Figure Figure Figure Figure 1: 2: 3: 4: 5: 6: 7: 8: General Block Diagram......................................................................... 5 Logical Symbol Diagram of the S5N8952X............................................. 6 Pin Configuration of the S5N8952X ...................................................... 7 Functional Block Diagram of the S5N8952X ......................................... 13 AFE Data I/F Timing Diagram.............................................................. 14 AFE Control I/F Timing Diagram .......................................................... 14 PCI I/F Timing Diagram ...................................................................... 15 208-LQFP Package Diagram ............................................................... 17 3 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC List of Tables Table Table Table Table Table 1: 2: 3: 4: 5: Pin Description of the S5N8952X .......................................................... 8 Absolute Maximum Ratings................................................................. 16 Recommended Operating Conditions .................................................... 16 Power Dissipation .............................................................................. 16 DC Characteristics ............................................................................. 16 4 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 1. Features • • • • • • • • • • • • • • • • • • Full Compliance with T1.413 Issue-2, ITU-T G.992.1 (G.dmt) and G.992.2 (G.lite). FDM and EC-based DMT Line Coding Data Rate: over 8Mbps for Downstream and 640 Kbps for Upstream. Reach: 6.7 Km (22Kft) with 24 AWG and 5.5 Km (18 Kft) with 26 AWG Supports Rate Adaptive Mode (steps of 32kbps) Reed-Solomon Forward Error Correction with(or without) Interleaver Adaptive Frequency and Time Domain Equalizer. Trellis Coding and Echo Cancellation. Supports Normal or Reduced Overhead Framing Modes Supports Analog and Digital PLL. Compatible to PCI V2.2 Handle ATM Cells (On-Chip SAR and Connection Memory) Supports Fast Retraining Function in G.lite Mode Supports Network Management Function Supports Power Management Function 0.18µm, 1.8V CMOS Technology Operating Temperature: -40 °C to 85 °C Package Type: 208-LQFP 2. General Description The S5N8952X is a complete ATM-based ADSL modem solution with associated F/W and an Analog Front-End (S5N8951). The S5N8952X provides all the digital functions such as PCI I/F, SAR, ATM framing, channel codec, DMT modulation, and DSP control. There are two interfaces for external communications; PCI bus interface for NIC applications and AD/DA interface. The S5N8952X is optimized for providing NIC solution for CPE, and uses 17.664MHz Xtal oscillator as a master clock. S5N8952 S5N8951 ATM Framer PCI_BUS DMT Processor Analog FrontEnd PCI & SAR Hybrid Phone Line Line Driver ROM ROM DSP Figure 1: General Block Diagram 5 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 3. Logical Symbol Diagram S5N8952X RESET_N XTAL_IN XTAL_OUT EXT_CLK PLL_FILT TEST_MODE[3:0] TEST_SCN_EN TEST_IN TEST_OUT TX_SHOW RX_SHOW GP_OUT[1:0] BT_MODE[1:0] NTR LD_TX_PWDN LD_RX_PWDN AFE_RESET_N AFE_SDI AFE_SDO AFE_SCK AFE_SEN_N AFE_BUSY AFE_PME AFE_NOISE AFE_DA_REF AFE_DA_CLK AFE_DA_DAT[6:0] AFE_AD_REF AFE_AD_CLK AFE_AD_DAT[6:0] PCI_AD[31:0] PCI_CBE_N[3:0] PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N PCI_STOP_N PCI_PERR_N PCI_PAR PCI_GNT_N PCI_PME_N PCI_REQ_N PCI_SERR_N PCI_INTA_N PCI_RST_N PCI_CLK PCI_IDSEL TL_TMS TL_TCK TL_TDI TL_TDO TL_TINTP EPROM_CS_N EPROM_SI EPROM_SO EPROM_CK PWR_ON AUX_PWR_ON Figure 2: Logical Symbol Diagram of the S5N8952X 6 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 4. Pin Configuration GP_OUT_0 GP_OUT_1 VDD34 GND38 NTR VDD35 GND39 BT_MODE_0 BT_MODE_1 VDD36 GND40 XTAL_IN XTAL_OUT VDDA37 GNDA41 PLL_FILT GNDA42 VDDA38 GNDA43 VDDA39 GNDA44 RESET_N GND45 VDD40 GND46 TX_SHOW RX_SHOW VDD41 GND47 PCI_INTA_N PCI_RST_N VDD42 GND48 PCI_CLK PCI_GNT_N GND49 VDD43 GND50 PCI_REQ_N PCI_PME_N GND51 VDD44 GND52 PCI_AD_31 PCI_AD_30 VDD45 PCI_AD_29 PCI_AD_28 VDD46 GND53 PCI_AD_27 PCI_AD_26 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 PCI_AD_25 PCI_AD_24 VDD1 GND1 PCI_CBE_N_3 PCI_IDSEL VDD2 GND2 PCI_AD_23 PCI_AD_22 VDD3 PCI_AD_21 PCI_AD_20 VDD4 GND3 PCI_AD_19 PCI_AD_18 VDD5 GND4 PCI_AD_17 PCI_AD_16 VDD6 PCI_CBE_N_2 GND5 VDD7 GND6 PCI_FRAME_N VDD8 GND7 PCI_IRDY_N VDD9 PCI_TRDY_N PCI_DEVSEL_N VDD10 GND8 PCI_STOP_N PCI_PERR_N VDD11 GND9 PCI_SERR_N PCI_PAR VDD12 PCI_CBE_N_1 PCI_AD_15 VDD13 GND10 PCI_AD_14 PCI_AD_13 VDD14 GND11 PCI_AD_12 PCI_AD_11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 S5N8952X ADSL Transceiver for NIC (208-LQFP) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 EXT_CLK AFE_DA_CLK VDD33 GND37 TEST_MODE_3 AFE_DA_REF TEST_MODE_2 GND36 VDD32 GND35 TEST_MODE_1 AFE_DA_DAT_6 TEST_MODE_0 GND34 VDD31 GND33 AFE_DA_DAT_5 TEST_SCN_EN VDD30 GND32 AFE_DA_DAT_4 AFE_AD_CLK AFE_DA_DAT_3 VDD29 GND31 AFE_AD_REF AFE_DA_DAT_2 AFE_AD_DAT_6 AFE_DA_DAT_1 VDD28 GND30 AFE_AD_DAT_5 AFE_AD_DAT_3 AFE_AD_DAT_4 GND29 VDD27 GND28 AFE_AD_DAT_1 AFE_DA_DAT_0 AFE_SDI AFE_SDO AFE_AD_DAT_2 AFE_RESET_N AFE_AD_DAT_0 AFE_SCK GND27 VDD26 GND26 AFE_BUSY AFE_SEN_N AFE_PME AFE_NOISE 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 TL_TMS TL_TCK VDD25 GND25 TL_TDI TL_TDO TL_TINTP VDD24 GND24 LD_TX_PWDN LD_RX_PWDN TEST_IN TEST_OUT GND23 VDD23 GND22 PWR_ON AUX_PWR_ON GND21 VDD22 GND20 EPROM_CS_N EPROM_SI VDD21 GND19 EPROM_SO EPROM_CK VDD20 GND18 PCI_AD_0 PCI_AD_1 VDD19 GND17 PCI_AD_2 PCI_AD_3 GND16 VDD18 GND15 PCI_AD_4 PCI_AD_5 GND14 VDD17 GND13 PCI_AD_6 PCI_CBE_N_0 VDD16 PCI_AD_7 VDD15 GND12 PCI_AD_8 PCI_AD_9 PCI_AD_10 Figure 3: Pin Configuration of the S5N8952X 7 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 5. Pin Description Table 1: Pin Description of the S5N8952X No 178 168 169 Name RESET_N XTAL_IN XTAL_OUT I/O I I O 156 EXT_CLK I 172 PLL_FILT O 152 150 146 144 139 93 92 TEST_MODE_3 TEST_MODE_2 TEST_MODE_1 TEST_MODE_0 TEST_SCN_EN TEST_IN TEST_OUT I I O 182 TX_SHOW O 183 RX_SHOW O 158 157 165 GP_OUT_1 GP_OUT_0 BT_MODE_1 164 BT_MODE_0 161 NTR B 200 201 203 204 207 208 1 2 9 10 12 13 16 17 20 21 44 47 48 PCI_AD_31 PCI_AD_30 PCI_AD_29 PCI_AD_28 PCI_AD_27 PCI_AD_26 PCI_AD_25 PCI_AD_24 PCI_AD_23 PCI_AD_22 PCI_AD_21 PCI_AD_20 PCI_AD_19 PCI_AD_18 PCI_AD_17 PCI_AD_16 PCI_AD_15 PCI_AD_14 PCI_AD_13 B I O I Description System master reset (Active low) System master clock (17.664MHz) External clock for test (Float in normal mode) PLL pump out (A 320pF capacitor between the pin and GNDA) Chip test mode [0] Normal mode, [1-15] Test mode Scan enable (Set to ‘0’ in normal mode) Test input (Float in normal mode) Test output (Float in normal mode) Tx showtime indicator (Active high. Connect to LED) Rx showtime indicator (Active high. Connect to LED) General purpose outputs (Float if not needed) Boot mode [0] Reset, [1] Boot from host [2] Boot from JTAG, [3] Self-booting ATM network timing reference (8KHz. Float if not needed) PCI address data [31:0] 8 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 51 52 53 54 55 58 61 65 66 70 71 74 75 PCI_AD_12 PCI_AD_11 PCI_AD_10 PCI_AD_9 PCI_AD_8 PCI_AD_7 PCI_AD_6 PCI_AD_5 PCI_AD_4 PCI_AD_3 PCI_AD_2 PCI_AD_1 PCI_AD_0 B PCI address data [31:0] 5 23 43 60 27 30 32 33 36 37 41 191 40 186 196 195 187 190 6 PCI_CBE_N_3 PCI_CBE_N_2 PCI_CBE_N_1 PCI_CBE_N_0 PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N PCI_STOP_N PCI_PERR_N PCI_PAR PCI_GNT_N PCI_SERR_N PCI_INTA_N PCI_PME_N PCI_REQ_N PCI_RST_N PCI_CLK PCI_IDSEL B B B B B B B B B B B I OZ OZ OZ OZ I I I 79 82 83 78 EPROM_SO EPROM_SI EPROM_CS_N EPROM_CK I 87 88 AUX_PWR_ON PWR_ON I I Aux power detected (Active high) Main power detected (Active high) 95 94 LD_TX_PWDN LD_RX_PWDN O O Tx line driver power-down (Active high) Rx line driver power-down (Active high) 114 117 116 112 107 108 AFE_RESET_N AFE_SDI AFE_SDO AFE_SCK AFE_SEN_N AFE_BUSY O I O O O I AFE AFE AFE AFE AFE AFE O PCI command byte enable [3:0] PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI frame initiator ready target ready device select stop parity error parity bit grant system error interrupt A power management event request reset clock initialization device select EPROM EPROM EPROM EPROM scan out scan in chip select clock reset (Active low) serial interface data in serial interface data out serial interface clock serial interface data enable (Active low) serial interface busy (Active high. Float if not 9 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 106 AFE_PME I 105 AFE_NOISE I 155 151 145 140 136 134 130 128 118 AFE_DA_CLK AFE_DA_REF AFE_DA_DAT_6 AFE_DA_DAT_5 AFE_DA_DAT_4 AFE_DA_DAT_3 AFE_DA_DAT_2 AFE_DA_DAT_1 AFE_DA_DAT_0 O O needed) AFE power management event (Active high. Float if not needed) Audible noise detection for power cutback (Active high. Float if not needed) DAC sample reference 1 (8.832MHz) DAC sample reference 0 (4.416MHz) O DAC data [6:0] 135 131 129 125 123 124 115 119 113 AFE_AD_CLK AFE_AD_REF AFE_AD_DAT_6 AFE_AD_DAT_5 AFE_AD_DAT_4 AFE_AD_DAT_3 AFE_AD_DAT_2 AFE_AD_DAT_1 AFE_AD_DAT_0 I I ADC sample reference 1 (Float in normal mode) ADC sample reference 0 (Float in normal mode) I ADC Data [6:0] 104 103 100 99 98 TL_TMS TL_TCK TL_TDI TL_TDO TL_TINTP I I I OZ O JTAG test mode select (Float in normal mode) JTAG test clock (Float in normal mode) JTAG test input data (Float in normal mode) JTAG test output data (Float in normal mode) TJAM interrupt to host (Float in normal mode) 11 22 31 42 59 77 85 97 110 127 138 148 159 162 180 202 VDD3 VDD6 VDD9 VDD12 VDD16 VDD20 VDD22 VDD24 VDD26 VDD28 VDD30 VDD32 VDD34 VDD35 VDD40 VDD45 P1 1.8V supply voltage VDD1 VDD4 VDD5 P1 3.3V supply voltage 3 14 18 10 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 25 34 38 49 57 63 73 81 90 102 121 133 142 154 166 184 188 198 205 VDD7 VDD10 VDD11 VDD14 VDD15 VDD17 VDD19 VDD21 VDD23 VDD25 VDD27 VDD29 VDD31 VDD33 VDD36 VDD41 VDD42 VDD44 VDD46 P1 3.3V supply voltage 7 28 45 68 193 VDD2 VDD8 VDD13 VDD18 VDD43 P1 3.3V or 5V supply voltage for PCI only 4 8 15 19 24 26 29 35 39 46 50 56 62 64 67 69 72 76 80 84 86 89 91 96 101 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 P0 Ground 11 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 109 111 120 122 126 132 137 141 143 147 149 153 160 163 167 179 181 185 189 192 194 197 199 206 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 P0 Ground 170 174 176 VDDA37 VDDA38 VDDA39 P1 1.8V analog supply voltage 171 173 175 177 GNDA41 GNDA42 GNDA43 GNDA44 P0 Analog ground I O OZ B P1 P0 = = = = = = Input Output Tri-state output Bi-direction Power Ground 12 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 6. Functional Description The ADSL modem for customer premises consists of two main chips; ADSL transceiver chip (S5N8952) and analog front-end chip (S5N8951). The analog front-end provides an analog interface with line drivers and hybrid components for connecting to the PSTN. The ADSL Transceiver provides all the digital functions as depicted in Figure 4. DMT inherently transmits an optimized time-variable spectrum. This spectrum is adjusted according to the desired data rate and the transmission characteristics (transfer function and noise spectrum) on each and every subchannel. For this, CO and CPE transmit 256 4kHz-wide tone downstream and upstream respectively to each other during initialization. They measure the quality of each of these received tones and then decide whether a tone has sufficient quality to be used for further transmission and, if so, how much data this tone should carry relative to the other tones that are used. They inform the bit loading informations to each other. In FDM-based DMT (Discrete MultiTone) modulation, the frequency band, 0 to 1.104MHz, is divided into 256 equi-spaced subchannels with 4.3125KHz tone spacing. The frequency band, 26KHz (#6) to 134KHz (#31) is used for the upstream, and 142KHz (#33) to 1.1MHz (#255) for the downstream. The S5N8952 provides PCI bus interface for NIC application and 14-bit AD/DA interface. SAR (Segmentation and Reassembly) and ATM TC (Transmission Convergence) are implemented for ATM cell handling and especially on-chip hardware SAR provides more processing power by reducing the PCI bus traffic than the software SAR. Reed-Solomon error correction with/without interleaver and Trellis coded modulation increase channel noise immunity. Time/frequency-domain equalizers, echo canceller, and digital filters, of which coefficients are adaptively updated according to the channel conditions, enhance the performance of data recovery. ATM TC SAR PCI_BUS FRAMER/ RS CODEC TCM/ VITERBI/ QAM CODEC FFT/IFFT/ ROTER TEQ/FEQ/ FILTER/ ECHO ANALOG FRONT_END PCI HOST I/F TEAKLITE DSP RAM ROM Figure 4: Functional Block Diagram of the S5N8952X 13 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 7. I/O Timing Description AFE_DA_CLK (8.832MHz) AFE_DA_REF (4.416MHz) AFE_DA_DAT [6:0] t1 [6:0] [13:7] t3 AFE_AD_DAT [6:0] Parameter t1 t2 t3 t4 t2 [6:0] t4 [13:7] AFE_DA_DAT AFE_DA_DAT AFE_AD_DAT AFE_AD_DAT Description setup to AFE_DA_CLK ↑ hold after AFE_DA_CLK ↑ setup to AFE_DA_CLK ↓ hold after AFE_DA_CLK ↓ Min 15 15 30 1 Max Unit ns ns ns ns Figure 5: AFE Data I/F Timing Diagram t2 t3 AFE_SEN_N AFE_SCK (1.104MHz) AFE_SDO CS1 CS0 A4 A0 RW D15 D14 D0 t1 AFE_SDI Parameter t1 t2 t3 D15 D14 Description AFE_SDI setup to AFE_SCK↑ AFE_SEN_N ↓ before AFE_SCK ↑ AFE_SEN_N ↑ from AFE_SCK ↑ Min 30 30 15 D0 Max Unit ns ns ns Figure 6: AFE Control I/F Timing Diagram 14 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC t3 t4 t5 PCI_CLK (33MHz) Inputs Outputs t1 t2 t6 t7 Tri-state Outputs Parameter t1 t2 t3 t4 t5 t6 t7 t8 t8 Description Input setup to PCI_CLK ↑ Input hold after PCI_CLK ↑ PCI_CLK period PCI_CLK low time PCI_CLK high time PCI_CLK ↑ to signal valid delay Float to active delay Active to float delay Min 3 0 30 6 6 1 1 Max 6 14 Unit ns ns ns ns ns ns ns ns Figure 7: PCI I/F Timing Diagram 15 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 8. Electrical Characteristics Table 2: Absolute Maximum Ratings Symbol ILATCH TSTG Parameter Latch-up Current Storage Temperature Rating ±200 -65 to 150 Unit mA °C Table 3: Recommended Operating Conditions Symbol Parameter Rating 1.8V I/O 3.3V I/O 5V-tolerant I/O (3.3V Interface) DC Supply Voltage VDD TA Analog Core DC Supply Voltage Operating Temperature (Ambient) Unit 1.65 to 1.95 3.0 to 3.6 3.0 to 3.6 1.8V Core 1.8±5% Commercial 0 to 70 V °C Table 4: Power Dissipation Symbol PD Parameter Power Dissipation Min - Typ 0.3 Max - Unit W Table 5: DC Characteristics Symbol VIH VIL VOH VOL VT VT+ VT- Parameters Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Switching Threshold Schmitt Trigger, Positive-going Threshold Schmitt Trigger, Negativegoing Threshold IIH Input High Current (VIN=VDD) IIL Input Low Current (VIN=VSS) IOZ IDD CIN COUT Tri-state Output Leakage Current Quiescent Supply Current Input Capacitance Output Capacitance Min 2.0 2.4 - Typ 1.4 Max 0.8 0.4 - - - 2.0 0.8 - - -10 10* -10 -60* 33* -33* 10 60* 10 -10* -10 - 10 - - 100 4 4 Unit V µA pF NOTES: * - input buffer with pull-up(VIN=VSS) or pull-down(VIN=VDD). 16 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC 9. Package Description A B A A: 30.00±0.30 B: 28.00±0.20 B #208 (1.25) #1 0.50 +0.10 0.20 −0.05 0.08MAX 1.40±0.10 1.60MAX 0.10±0.05 0.10MAX 0~8° 0.50±0.20 Figure 8: 208-LQFP Package Diagram 17 Preliminary Information (Rev.2.0) S5N8952X ADSL Transceiver for NIC Revision History Revision No. 1.0 1.1 2000-09-15 2000-09-20 2.0 2000-11-15 Date Description First released. Pin configuration changed. T1.413 issue-2 added. PCI version upgraded from 2.1 to 2.2 IMPORTANT NOTICE The information furnished by Samsung Electronics in this document is belived to be accurate and reliable. However, no resposibility is assumed by Samsung Electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Samsung Electronics. Samsung Electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. For More Information Tel: (82)-(31)-209-8301, Fax: (82)-(31)-209-8309 E-mail: [email protected] http://www.intl.samsungsemi.com 18 Preliminary Information (Rev.2.0)