Ordering number :EN5847
P-Channel Silicon MOS FET
FW113
S/W Load Applications
Features
Package Dimensions
· 4V drive.
· Low ON resistance.
unit:mm
2129
[FW113]
5
4
0.2
1.8max
1
6.0
4.4
0.3
8
0.595
1.27
0.43
0.1
1.5
5.0
1:Source1
2:Gate1
3:Source2
4:Gate2
5:Drain2
6:Drain2
7:Drain1
8:Drain1
SANYO:SOP8
Specifications
Absolute Maximum Ratings at Ta = 25˚C
Parameter
Drain-to-Source Voltage
Gate-to-Source Voltage
Symbol
Conditions
Ratings
VDSS
VGSS
Drain Current (DC)
Unit
–30
V
±20
V
–5
A
ID
Drain Current (pulse)
Allowable Power Dissipation
Total Dissipation
IDP
PD
Channel Temperature
PT
Tch
Storage Temperature
Tstg
PW≤10µs, duty cycle≤1%
–32
A
Mounted on ceramic board (1000mm2×0.8mm) 1unit
1.7
W
Mounted on ceramic board (1000mm2×0.8mm)
2.0
W
150
˚C
–55 to +150
˚C
Electrical Characteristics at Ta = 25˚C
Parameter
D-S Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
Cutoff Current
Forward Transfer Admittance
Static Drain-to-Source ON-State Resistance
Symbol
V(BR)DSS
IDSS
| yfs |
VDS=–10V, ID=–5A
ID=–5A, VGS=–10V
RDS(on)1
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-ON Delay Time
td(on)
tr
td(off)
tf
Fall Time
Total Gate Charge
Qg
Ratings
min
typ
max
VDS=–10V, ID=–1mA
ID=–2A, VGS=–4V
VDS=–10V, f=1MHz
Unit
–30
V
VDS=–30V, VGS=0
VGS=±16V, VDS=0
RDS(on)2
Turn-OFF Delay Time
ID=–1mA, VGS=0
IGSS
VGS(off)
Input Capacitance
Rise Time
Conditions
–1.0
5
–100
µA
±10
µA
–2.5
V
8
S
42
53
mΩ
85
120
mΩ
820
pF
470
pF
230
pF
See specified Test Circuit
15
ns
See specified Test Circuit
150
ns
See specified Test Circuit
85
ns
See specified Test Circuit
90
ns
25
nC
5
nC
7
nC
VDS=–10V, f=1MHz
VDS=–10V, f=1MHz
Gate-to-Source Charge
Qgs
VDS=–10V, VGS=–10V, ID=–5A
VDS=–10V, VGS=–10V, ID=–5A
Gate-to-Drain ("Miller") Charge
Qgd
VDS=–10V, VGS=–10V, ID=–5A
Diode Forward Voltage
VSD
IS=–5A, VGS=0
–1.0
–1.5
V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
52698TS (KOTO) TA-1215 No.5847-1/3
FW113
Switching Time Test Circuit
0V
–10V
VDD=–15V
VIN
ID=–5A
RL=3Ω
VIN
PW=10µs
D
VOUT
D.C.≤1%
G
FW113
P.G
50Ω
S
I D - VDS
-8
A
–4
C
-3
-2
-1
-1
VGS=–2.5V
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
0
-1.0
0
| yfs | - I D
˚C
–25
Ta=
5˚C
C 2
75˚
3
2
1.0
7
5
3
2
2 3 5 7-1.0
2 3 5 7-10
120
100
40
20
0
-2
-6
-10
-12
-14
-16
-18
-20
I F - VSD
=–10V
3
2
-1.0
7
5
3
2
˚C
A, VGS
ID =–5
-8
-0.1
7
5
Ta=75
=–4V
Forward Current, IF - A
Static Drain-to-Source
ON-State Resistance, RDS (on) – mΩ
, V GS
=–2A
40
3
2
20
0
-60
-4
-10
7 VGS=0
5
80
60
-4.0
Gate-to-Source Voltage,VGS - V
120
ID
-3.5
60
0
2 3 5 7-100
R DS(on) - Tc
100
-3.0
80
Drain Current, ID - A
140
-2.5
Tc=25˚C
ID=–2A
3
2
0.1
7
-0.01 2 3 5 7-0.1
-2.0
R DS(on) - VGS
140
VDS=–10V
10
7
5
-1.5
Gate-to-Source Voltage, VDS - V
Static Drain-to-Source
ON-State Resistance, RDS (on) – mΩ
Forwaard Transfer Addmittance,|yfs| - S
5
-1.0
-0.5
Drain-to-Source Voltage, VDS - V
–25˚C
-0.2
25˚C
-0.1
ID=–5A
0
0
˚C
–3.0V
-4
75˚
-2
-5
–25
-3
-6
Ta=
V
–3.5
Drain Current, ID -
-7
-4
25˚C
–10
A
Drain Current, ID -
VDS =–10V
-9
.0V
.0V
-5
I D - VGS
-10
–8.
0
–6.0V
V
-6
-40
-20
0
20
40
60
80
Case Temperature, Tc - ˚C
100
120
140
-0.01
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
Diode Forward Voltage, VSD – V
No.5847-2/3
FW113
Ciss,Coss,Crss - VDS
10000
7
5
Gate-to-Source Voltage, VGS – V
Ciss,Coss,Crss - pF
3
2
1000
7
5
Ciss
Coss
3
2
Crss
100
7
5
3
2
10
0
-5
-10
-15
-20
-25
-8
-7
-6
-5
-4
-3
-2
Drain Current, I D - A
3
tr
tf
t d(o
7
ff)
5
3
2
15
20
25
A S O
t d(on)
,,,,,,,,,
,,,,,,,,,
,,,,,,,,,
,,,,,,,,,
,,,,,,,,,
,,,,,,,,,
,,,,,,,,,
-10
7
5
3
2
-1.0
7
5
3
2
100µs
1m
s
I D = –5A
DC
10
ms
10
op
0m
er
s
at
io
n
Operation in this area is
limited by RDS(on).
-0.1
7 Ta=25˚C
5
3 1pulse
2 1unit
Mounted on ceramic board (1000mm2 × 0.8mm)
7 -0.1
2
3
5
7 -1.0
2
3
5
7 -10
2
-0.01
-0.01 2 3
Drain Current, ID – A
5 7 -0.1
2 3
5 7 -1.0
2 3
5 7 -10
2 3
5
Drain -to-Source Voltage, VDS - V
P D (FET2) - P D (FET1)
2.0
P D - Ta
2.5
1.8
M
1.6
1.4
ou
nte
do
nc
era
1.2
mi
cb
oa
1.0
0.8
rd
(1
00
0m
m× 2
0.8
0.6
mm
Allowable Dissipation, PD – W
Allowable Dissipation, PD(FET 2) – W
10
-100
7
5 I DP = –32A
3
2
5
100
5
Total Gate Charge, Qg – nC
VDD =–15V
VGS=–10V
2
0
0
-30
Drain-to-Source Voltage,VDS – V
SW Time - I D
7
Switching Time, SW Time – ns
VDS=–10V
-9 ID =–5A
-1
1000
10
VGS - Qg
-10
f=1MHz
)
0.4
2.0
1.7
1.5
To
tal
Di
ss
1.0
1u
nit
ip
ati
on
0.5
0.2
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Allowable Dissipation, PD(FET 1) – W
1.8
2.0
0
0
Mounted on ceramic board (1000mm2×0.8mm)
20
40
60
80
100
120
140
160
Ambient Temperature, Ta – ˚C
No products described or contained herein are intended for use in surgical implants, life-support systems,
aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and
the like, the failure of which may directly or indirectly cause injury, death or property loss.
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates,
subsidiaries and distributors and all their officers and employees, jointly and severally, against any
and all claims and litigation and all damages, cost and expenses associated with such use:
Not impose any responsibilty for any fault or negligence which may be cited in any such claim or
litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of
their officers and employees jointly or severally.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees
are made or implied regarding its use or any infringements of intellectual property rights or other rights of
third parties.
This catalog provides information as of May, 1998. Specifications and information herein are subject to
change without notice.
PS No.5847-3/3