Ordering number : ENN*6744 CMOS IC LC86E5632 8-Bit Single Chip Microcontroller with the One-Time Programmable UVEPROM Preliminary Overview The LC86E5632 is a CMOS 8-bit single chip microcontroller with one-time UVEPROM for the LC865600 series. This microcontroller has the function and the pin description of the LC865600 series mask ROM version, and 32K-byte EPROM. The program data is rewritable. It is suitable to developing the program. Features (1) Option switching by EPROM data The option function of the LC865600 series can be specified by the EPROM data. LC86E5632 can be checked the function of the trial pieces using the mass production board. (2) Internal one-time EPROM capacity : 32768 bytes (3) Internal RAM capacity : 512 bytes Mask ROM version PROM capacity RAM capacity LC865632 32512 bytes 512 bytes LC865628 28672 bytes 512 bytes LC865624 24576 bytes 512 bytes LC865620 20480 bytes 384 bytes LC865616 16384 bytes 384 bytes LC865612 12288 bytes 384 bytes LC865608 8192 bytes 384 bytes Programming service We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping and the screening. Contact our representative for further information. Ver.1.02 30399 91400 RM (IM) HK No.6744-1/21 LC86E5632 (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 0.98µs to 400µs (6) Operating temperature : +10°C to +40°C (7) The pin compatible with mask ROM version (8) Applicable mask ROM version : LC865632/ LC865628/ LC865624/LC865620/LC865616/ LC865612/ LC865608 (9) Factory shipment : DIC64S, QFC64E Notice for use LC86E5632 is provided for the first release and small shipping of the LC865600 series. At using, take notice of the followings. (1) A point of difference LC86E5632 and LC865600 series Item LC86E5632 LC865632/28/24/20/16/12/08 Port form at reset Please refer “Port form at reset” on next page. Operation after reset releasing The option is specified until 3ms after going to a ‘H’ level to the reset terminal by dgrees. The program is executed from 00H of the program counter. The program is executed from 00H of the program counter immediately after going to a ‘H’ level to reset terminal. 4.5V to 6.0V 2.7V to 6.0V +10°C to +40°C -30°C to +70°C Operating supply voltage range (VDD) Operating temperature range (Topg) Total output current [∑IOAH(1)] [∑IOAH(2)] Power dissipation [IDDOP(1)] [IDDOP(2)] [IDDOP(3)] [IDDOP(4)] Refer to ‘electrical characteristics’ on the semiconductor news. • A kind of the option corresponding of the LC86E5632 A kind of option Pins, Circuits Contents of the option Input/output form of Input/output ports Port 0 (Specified in a bit) 1. Input Output 2. Input Output : No pull-up MOS Tr. : N-channel open drain : Pull-up MOS Tr. : CMOS Port 1,2 (Specified in a bit) 1. Input Output 2. Input Output : Programmable pull-up MOS Tr. : N-channel open drain : Programmable pull-up MOS Tr. : CMOS Port 3,4,5 (Specified in a bit) 1. Input Output 2. Input Output : No Programmable pull-up MOS Tr. : N-channel open drain : Programmable pull-up MOS Tr. : CMOS port7 (Specified in a bit) 1. Pull-up MOS Tr. not provided 2. Pull-up MOS Tr. provided * P74 has on pull-up resistor option. Pull-up MOS Tr. Of port7 The port operation related the option is different at reset. Refer to the next table. No.6744-2/21 LC86E5632 •Port form at reset Pin Contents of the option P0 Input : Not pull-up MOS Tr. Output : N-channel open drain (Same as the mask version) Input mode without pull-up MOS Tr. (Output is OFF) Input : Pull-up MOS Tr. Output : CMOS Input mode •The pull-up MOS Tr. is not provided during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS Tr. is provided. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) Input : Programmable pull-up MOS Tr. Output : N-channel open drain (Same as the mask version) Input mode without pull-up MOS Tr. (Output is OFF) Input : Programmable pull-up MOS Tr. Output : CMOS (Same as the mask version) Input mode without pull-up MOS Tr. (Output is OFF) Input : Not Programmable pull-up MOS Tr. Output : N-channel open drain (Same as the mask version) Input mode without pull-up MOS Tr. (Output is OFF) Input : Programmable pull-up MOS Tr. Output : CMOS (Same as the mask version) Input mode without pull-up MOS Tr. (Output is OFF) Pull-up MOS Tr. not provided (Same as the mask version) Input mode without pull-up MOS Tr. Pull-up MOS Tr. provided Input mode •The pull-up MOS Tr. is not provided during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS Tr. is provided. Input mode without pull-up MOS Tr. P1, P2 P3, P4, P5 P7 LC86E5632 LC865632/28/24/20/16/12/08 (2) Option LC86E5632 uses 256 bytes which is addressed on 7F00H to 7FFFH in the program memory as option data area. This area does not affect the execution of program but the program memory capacity of LC865632 is 32512 bytes which is addressed on 0000H to 7EFFH. The option data is created by the option specified program “SU865000.EXE”. The created option data is linked to the program area by linkage loader “L865000.EXE”. No.6744-3/21 LC86E5632 (3) ROM space 7FFFH 7F00H 7EFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH Opt ion data Area 256 bytes Opt ion Data Area Opt ion Data Area Opt ion Data Area Opt ion Data Area Opt ion Data Area Opt ion Data Area Program area Program area Program area Program area Program area Program area Program area 32K bytes 28K bytes 24K bytes 20K bytes 16K bytes 12K bytes 8K bytes LC865632 LC865628 LC865624 LC865620 LC865616 LC865612 LC865608 0000H How to use (1) Specification of option Programming data for EPROM of the LC86E5632 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P5632. (2) How to program for the EPROM LC86E5632 can be programmed by the EPROM programmer with attachment ; W86EP5032D, W86EP5032Q. • Recommended EPROM programmer Productor EPROM programmer Advantest R4945, R4944, R4943 Andou AF-9704 AVAL PKW-1100, PKW-3000 Minato electronics MODEL 1890A • “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0000H to 7FFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming. (3) How to use the data security function “Data security” is the disabled function to read the data of the EPROM. The following is the process in order to execute the data security. 1. Set ‘ON’ the jumper of attachment. 2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the EPROM programmer or the LSI. Notes • Data security is not executed when the data of all address have ‘FF’ at the sequence 2 above. • The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the sequence 2 above. • Set to ‘OFF’ the jumper after executing the data security. No.6744-4/21 LC86E5632 (4) How to eliminate The programming data can be erased by using the EPROM eraser. (5) Shielding The UVEPROM (ultraviolet erasable programmable ROM) is in it. Data security Data security Not data security 1 pin W86EP5032D Put the seal on the window in use. 1 pin 1 pin mark of LSI Not data security W86EP5032Q No.6744-5/21 LC86E5632 Pin Assignment SANYO:DIC64S P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM TEST1 RES XT1/P74 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P07 P06 P05 P04 P03 P02 P01 P00 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VSS P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P17/PWM P16/BUZ P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P07 P06 P05 P04 P03 P02 P01 P00 SANYO:QFC64E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VSS P51 P50 P47 P46 P45 P44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 TEST1 RES XT1/P74 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 No.6744-6/21 LC86E5632 System Block Diagram Interrupt Control IR Standby Control PLA A15-A0 D7-D0 TA CE OE DASEC VDDVPP EPROM Control RC Clock Generator CF EPROM (32KB) X’tal PC Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 7 C Register Timer 0 Port 8 ALU Timer 1 Port 2 ADC Port 3 PSW INT0 to 3 Noise Filtter Port 4 RAR Real Time Service Port 5 RAM RAM (128 bytes) Stack Pointer Port 0 Watch Dog Timer No.6744-7/21 LC86E5632 LC86E5632 Pin description Pin name VSS I/O - Function description Option Power pin (-) - PROM mode - VDD - Power pin (+) - - VDDVPP - Power pin (+) - Power for programming PORT0 P00 to P07 I/O •8-bit input/output port •Input for port 0 interrupt •Input/output in nibble units •Input for HOLD release •Pull-up resistor : Provided/Not provided •Output form : CMOS/N-channel open drain - PORT1 P10 to P17 I/O •8-bit input/output port •Input/output can be specified in a bit unit •Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM0 output) Output form : CMOS/N-channel open drain Data line D0 to D7 PORT2 P20 to P27 I/O •8-bit input/output port •Input/output can be specified in a bit unit Output form : CMOS/N-channel open drain PORT3 P30 to P37 I/O •8-bit input/output port •Input/output can be specified in a bit unit •15V withstand at N-channel open drain output Output form : CMOS/N-channel open drain Address input A7 to A0 PORT4 P40 to P47 I/O •8-bit input/output port •Input/output can be specified in a bit unit •15V withstand at N-channel open drain output Output form : CMOS/N-channel open drain Address input A14 to A8 (*5) P47 : TA (*4) PORT5 P50 to P51 I/O •2-bit input/output port •Input/output can be specified in a bit unit •15V withstand at N-channel open drain output Output form : CMOS/N-channel open drain •5-bit input port •Other pin functions P70 : INT0 input/HOLD release/N-channel Tr. output for watchdog timer P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input P74 : 32.768kHz crystal oscillation terminal XT1 •Pull-up resistor : Provided/Not provided (P70,71,72,73) • P74 has no pull-up PORT7 P70 P71 to P74 I/O I •Interrupt received forms, the vector addresses high low rising falling rising & level falling level resistor. Input of PROM control signals DASEC (*1) OE (*2) CE (*3) vector INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH Continue. No.6744-8/21 LC86E5632 Pin name I/O Function description Option PROM mode PORT8 P80 to 87 I •8-bit input port •Other function AD input port (AN7 to AN0) - - RES I Reset pin - - TEST1 O Test pin Should be left unconnected. - - XT1/ P74 I •Input pin for 32.768kHz crystal oscillation •Other function : Input port P74 - - - - In case of non use, connect to VDD. XT2 O •Output pin for 32.768kHz crystal oscillation •Other function In case of non use, should be left unconnected. CF1 I Input pin for the ceramic resonator oscillation - - CF2 O Output pin for the ceramic resonator oscillation - - ♦ All of port options can be specified in bit unit. *1 *2 *3 *4 *5 Memory select input for data security Output enable input Chip enable input TA ! PROM control signal input A14 ! Address input * Connect like the following figure to reduce noise into a VDD terminal. Short-circuit the VDD terminal to the VDDVPP terminal. Short-circuit the VSS terminal to the VSS terminal. LSI VDD Power Supply VDDVPP VSS VSS No.6744-9/21 LC86E5632 1. Absolute Maximum Ratings at VSS=0V and Ta=25°C Parameter Supply voltage Input voltage Input/Output voltage High level output current Low level output current Peak output current Total output current Peak output current Total output current Maximum power dissipation Operating Temperature range Storage Temperature range Symbol Pins VDDMAX VDD,VDDVPP VI(1) •Ports 71,72,73, 74 •Port 8 • RES VIO(1) •Ports 0,1,2 •Ports 3,4,5 at CMOS output VIO(2) Ports 3,4,5 at N-ch open drain output option IOPH(1) •Ports 0,1,2,3,4,5 Conditions VDD=VDDVPP VDD[V] min. Ratings typ. max. -0.3 -0.3 +7.0 VDD+0.3 -0.3 VDD+0.3 -0.3 15 •CMOS output •At each pins -4 V mA ΣIOAH(1) Ports 0,1,2 The total of all pins -25 ΣIOAH(2) Ports 3,4,5 The total of all pins -20 IOPL(1) Ports 0,1,2,3,4,5 At each pins 20 IOPL(2) Port 70 At each pins 15 ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pdmax(1) Pdmax(2) Topr Ports 0,1,70 Port 2 Ports 3,4,5 DIP64S QFP64E The total of all pins The total of all pins The total of all pins Ta=+10 to+40°C Ta=+10 to+40°C 10 40 40 80 720 420 40 -65 150 Tstg unit mW °C No.6744-10/21 LC86E5632 2. Recommended Operating Range at Ta=+10°C to +40°C, VSS=0V Parameter Symbol Pins Operating Supply voltage Hold voltage VDD(1) VDD VHD VDD Input high voltage VIH(1) Port 0 VIH(2) •Ports 1,2 •Ports 72,73 (Schmitt) •Port 70 (Port input/interrupt) •Port 71 (Schmitt) • RES Port 70 (Watchdog timer) •Port 74 •Port 8 Ports 3,4,5 of CMOS output (Schmitt) Ports 3,4,5 of open drain output (Schmitt) Port 0 (Schmitt) •Ports 1,2,3,4,5 •Ports 72,73 (Schmitt) •Port 70 (Port input/interrupt) •Port 71 (Schmitt) • RES Port 70 (Watchdog timer) •Port 74 •Port 8 VIH(3) VIH(4) VIH(5) VIH(6) VIH(7) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4) VIL(5) Operation tCYC cycle time Oscillation FmCF(1) frequency range (Note 1) FmCF(2) FmRC FsXtal CF1, CF2 CF1, CF2 XT1, XT2 (Schmitt) Conditions VDD[V] 0.98µs ≤ tCYC tCYC ≤ 400µs RAMs and the registers hold voltage at HOLD mode. Output disable 4.5 to 6.0 Output disable min. Ratings typ. max. 4.5 6.0 2.0 6.0 VDD 4.5 to 6.0 0. 4VDD +0.9 0.75VDD Output N-channel Tr. OFF 4.5 to 6.0 0.75VDD VDD Output N-channel Tr. OFF Output N-channel Tr. OFF Output disable 4.5 to 6.0 0.9VDD VDD 4.5 to 6.0 0.75VDD VDD 4.5 to 6.0 0.75VDD VDD Output disable 4.5 to 6.0 0.75VDD 13.5 Output disable Output disable 4.5 to 6.0 4.5 to 6.0 VSS VSS 0.2VDD 0.25VDD N-channel Tr.OFF 4.5 to 6.0 VSS 0.25VDD N-channel Tr.OFF 4.5 to 6.0 VSS N-channel Tr.OFF 4.5 to 6.0 VSS 0.8VDD -1.0 0.25VDD 4.5 to 6.0 0.98 400 •6MHz (ceramic resonator oscillation) •Refer to figure 1 •1.5MHz (ceramic resonator oscillation) •Refer to figure 1 RC oscillation •32.768kHz (crystal oscillation) •Refer to figure 2 6 4.5 to 6.0 1.5 0.3 V VDD 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 unit 0.8 32.768 µs MHz 3.0 kHz Continue. No.6744-11/21 LC86E5632 Parameter Oscillation stabilizing time period (Note 1) Symbol Pins Conditions •6MHz (ceramic resonator oscillation) VDD[V] tmsCF(1) CF1, CF2 4.5 to 6.0 tmsCF(2) CF1, CF2 •Refer to figure 3 •1.5MHz (ceramic resonator oscillation) 4.5 to 6.0 tssXtal XT1, XT2 •Refer to figure 3 •32.768kHz (crystal oscillation) •Refer to figure 3 4.5 to 6.0 min. Ratings typ. max. unit ms s (Note 1) The oscillation constant is shown on table 1 and table 2. No.6744-12/21 LC86E5632 3. Electrical Characteristics at Ta=+10°C to +40°C, VSS=0V Parameter Input high current Input low current Symbol IIH(1) Ports 3,4,5 at open drain output IIH(2) •Port 0 without pull-up MOS Tr. •Ports 1,2,3,4,5 IIH(3) •Ports 70,71,72,73 without pull-up MOS Tr. •Port 8 RES •Ports 1,2,3,4,5 •Port 0 without pull-up MOS Tr. IIH(4) IIL(1) IIL(2) Output high voltage Output low voltage Pull-up MOS Tr. resistor Hysteresis voltage Pins IIL(3) VOH(1) VOH(2) VOL(1) VOL(2) VOL(3) VOL(4) Rpu VHIS Pin capacitance CP •Ports 70,71,72,73 without pull-up MOS Tr. •Port 8 RES Ports 0,1,2,3,4,5 at CMOS output Ports 0,1,2,3,4,5 Port 70 •Ports 0,1,2,3,4,5 •Ports 70,71,72,73 •Ports 0,1,2,3,4,5 •Ports 70,71,72,73 • RES All pins Conditions •Output disable •VIN=13.5V (including off-leakage current of the output Tr.) •Output disable •Pull-up MOS Tr. OFF. •VIN=VDD (including off-leakage current of the output Tr.) VIN=VDD VDD[V] min. Ratings typ. max. 4.5 to 6.0 5 4.5 to 6.0 1 4.5 to 6.0 1 unit µA VIN=VDD •Output disable •Pull-up MOS Tr. OFF. •VIN=VSS (including off-leakage current of the output Tr.) VIN=VSS 4.5 to 6.0 4.5 to 6.0 -1 1 4.5 to 6.0 -1 VIN=VSS IOH=-1.0mA IOH=-0.1mA IOL=10mA IOL=1.6mA IOL=1mA IOL=0.5mA 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 -1 VDD-1 VDD-0.5 VOH=0.9VDD 4.5 to 6.0 15 Output disable 4.5 to 6.0 0.1VDD V •f=1MHz •VIN=VSS for all unmeasured terminals. •Ta=25°C 4.5 to 6.0 10 pF V 1.5 0.4 0.4 0.4 40 70 kΩ No.6744-13/21 LC86E5632 4. Serial Input/Output Characteristics at Ta=+10°C to +40°C, VSS=0V Serial output Serial input Input clock Output clock Serial clock Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Symbol tCKCY(1) tCKL(1) Pins SCK0, SCK1 Conditions Refer to figure 5 VDD[V] min. 4.5 to 6.0 2 1 tCKH(1) tCKCY(2) tCKL(2) tICK Data hold time tCKI Output delay time (External clock using for serial transfer clock) Output delay time (Internal clock using for serial transfer clock) tCKO(1) tCKO(2) max. unit tCYC 1 SCK0, SCK1 tCKH(2) Data set-up time Ratings typ. •SI0,SI1 •SB0,SB1 •SO0,SO1 •SB0,SB1 •Use pull-up resistor (1kΩ) in the open drain output. •Refer to figure 5 4.5 to 6.0 •Data set-up to SCK0,1 •Data hold from SCK0,1 •Refer to figure 5 •Use pull-up resistor (1kΩ) in the open drain output. •Data hold from SCK0,1 •Refer to figure 5 4.5 to 6.0 2 1/2tCKCY 1/2tCKCY µs 0.1 0.1 4.5 to 6.0 7/12 tCYC +0.2 1/3 tCYC +0.2 No.6744-14/21 LC86E5632 5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS=0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIL(4) Pins •INT0, INT1 •INT2/T0IN •INT3 INT3 (The noise rejection clock selected to 1/1.) INT3 (The noise rejection clock selected to 1/16.) RES Conditions VDD[V] min. •Interrupt acceptable •Timer0-countable 4.5 to 6.0 1 •Interrupt acceptable •Timer0-countable 4.5 to 6.0 2 •Interrupt acceptable •Timer0-countable 4.5 to 6.0 32 Reset acceptable 4.5 to 6.0 200 Ratings typ. max. unit tCYC µs 6. AD Converter Characteristics at Ta=+10°C to + 40°C, VSS=0V Parameter Symbol Resolution Absolute precision (Note 2) Conversion time N ET Analog input voltage range Analog port input current VAIN Pins VDD[V] min. 4.5 to 6.0 4.5 to 6.0 tCAD IAINH IAINL Conditions AD conversion time = 16 × tCYC (ADCR2=0) (Note 3) AD conversion time = 32 × tCYC (ADCR2=1) (Note 3) AN0 to AN7 VAIN=VDD VAIN=VSS max. 8 ±1.5 4.5 to 6.0 15.68 (tCYC= 0.98µs) 31.36 (tCYC= 0.98µs) VSS 4.5 to 6.0 4.5 to 6.0 -1 4.5 to 6.0 Ratings typ. unit bit LSB 65.28 (tCYC= 4.08µs) 130.56 (tCYC= 4.08µs) VDD µs 1 µA V (Note 2) Absolute precision excepts the quantizing error (±1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register. No.6744-15/21 LC86E5632 7. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS=0V Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) Pins VDD Conditions •FmCF=6MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •FmCF=1.5MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : 32.768kHz •Internal RC oscillation stops Ratings typ. max. 4.5 to 6.0 13 26 4.5 to 6.0 7 14 4.5 to 6.0 4 10 4.5 to 6.0 4 8 VDD[V] min. unit mA Continue. No.6744-16/21 LC86E5632 Parameter Symbol Current dissipation in HALT mode (Note 4) IDDHALT(1) Pins IDDHALT(2) IDDHALT(3) IDDHALT(4) Current dissipation in HOLD mode (Note 4) IDDHOLD(1) IDDHOLD(2) VDD Conditions •HALT mode •FmCF=6MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •HALT mode •FmCF=1.5MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •HALT mode FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •HALT mode FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : 32.768kHz •Internal RC oscillation stops HOLD mode Ratings typ. 5 max. 10 4.5 to 6.0 2.2 4.6 4.5 to 6.0 550 1000 4.5 to 6.0 25 100 4.5 to 6.0 0.05 30 2.5 to 4.5 0.02 20 VDD[V] 4.5 to 6.0 min. unit mA µA (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. No.6744-17/21 LC86E5632 Table 1. Ceramic resonator oscillation recommended constant (main clock) Oscillation type Maker Oscillator 12MHz ceramic resonator oscillation Murata 3MHz ceramic resonator oscillation Murata CSA12.0MTZ CSA12.0MTZ CST12.0MTW CSA3.00MG040 CST3.00MGW040 C1 C2 33pF 33pF 39pF 30pF on chip 100pF 100pF on chip Rf Rd OPEN OPEN OPEN OPEN OPEN 560Ω 0Ω 560Ω 1.5Ω 1.5Ω * Both C1 and C2 must use K rank (±10%) and SL characteristics. Table 2. Crystal oscillation recommended constant (sub clock) Oscillation type Maker Oscillator C3 C4 32.768kHz crystal oscillation Kyocera Seiko Epson KF-38G-13P0200 MC-306,C-002RX,32.768kHz 18pF 4pF 18pF 4pF * Both C3 and C4 must use J rank (±5%) and CH characteristics. (It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 XT1 XT2 Rf Rd X’tal C1 Figure 1 CF C2 Main-clock circuit Ceramic oscillation circuit C3 Figure 2 C4 Sub-clock circuit Crystal oscillation No.6744-18/21 LC86E5632 VDD VDD limit Power supply OV Reset time RES Interrnal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution mode < Reset time and oscillation stabilizing time. > HOLD release signal Valid Interrnal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution mode < HOLD release signal and oscillation stabilizing time. > Figure 3 Oscillation stable time No.6744-19/21 LC86E5632 VDD RRES (Note) Fix the value of CRES, RRES that is sure to reset until 200µs, after Power supply has been over inferior limit of supply voltage. RES CRES Figure 4 Reset circuit 0.5VDD <AC timing point> tCKCY tCKL VDD tCKH SCK0 SCK1 1KΩ tICK tCKI SI0 SI1 tCKO 50pF SO0, SO1 SB0, SB1 <Timing> Figure 5 tPIL Figure 6 <Test load> Serial input / output test condition tPIH Pulse input timing condition No.6744-20/21 LC86E5632 PS No.6744-21/21