SANYO LC86E7148

Ordering number : ENN*6748
CMOS IC
LC86E7148
8-Bit Single Chip Microcontroller
with the UVEPROM
Preliminary
Overview
The LC86E7148 is a CMOS 8-bit single chip microcontroller with UVEPROM for the LC867100 series. This
microcontroller has the function and the pin description of the LC867100 series mask ROM version, and 48K-byte EPROM.
The program data is rewritable. It is suitable to develop the program.
Features
(1) Option switching by EPROM data
The option function of the LC867100 series can be specified by the EPROM data.
LC86E7148 can be checked the functions of the trial pieces using the mass production board.
(2) Internal EPROM capacity
: 49152 bytes
(3) Internal RAM capacity
: 1152 bytes
Used EPROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86E7148.
Mask ROM version
LC867148
LC867140
LC867132
LC867128
LC867124
LC867120
LC867116
LC867112
LC867108
EPROM capacity
49152 bytes
40960 bytes
32768 bytes
28672 bytes
24576 bytes
20480 bytes
16384 bytes
12288 bytes
8192 bytes
RAM capacity
1152 bytes
1152 bytes
768 bytes
768 bytes
768 bytes
640 bytes
640 bytes
512 bytes
512 bytes
(4) Operating supply voltage
: 4.5V to 6.0V
(5) Instruction cycle time
: 1µs to 366µs
(6) Operating temperature
: +10°C to +40°C
(7) The pin compatible with the LC867100 series mask ROM devices
(8) Applicable mask ROM version
: LC867148/LC867140/LC867132/LC867128/LC867124/LC867120
/LC867116/LC867112/LC867108
(9) Factory shipment
: QIC80S
Ver.1.01A
D1694
91400 RM (IM) HK No.6748-1/20
LC86E7148
Notice for use
At using, take notice of the followings.
(1) A point of difference LC86E7148 and LC867100 series
Item
LC86E7148
LC867148/40/32/28/24/20/16/12/08
Port form at reset
Please refer ‘Port form at reset’ on next page.
Operation after reset
The option is specified until 3ms after The program is executed from 00H of the
releasing
going to a ‘H’ level to the reset terminal program counter immediately after going
by degrees. The program is executed from to a ‘H’ level to the reset terminal.
00H of the program counter.
Operating supply
4.5V to 6.0V
2.5V to 6.0V
voltage range (VDD)
Refer to ‘electrical characteristics’ on the semiconductor news.
Total output current
[∑IOAL(2)]
[∑IOAL(3)]
Power dessipation
LC86E7148 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data
area. This option configuration can execute all options which LC867100 series have. Next tables show the options that
correspond and not correspond to LC86E7148.
• A kind of the option corresponding of the LC86E7148
A kind of option
Pins, Circuits
Input/output form of
Port 0
input/output ports
(specified in a bit)
Port 1
(specified in a bit)
Pull-up MOS Tr. of
input port
*1) Specified in a bit.
*2) Specified in nibble unit.
*1
Port 7
(specified in a bit) *1
Each of P74 and P75 has no
option
Contents of the option
1. Input : No Pull-up MOS Tr.
Output : N-channel open drain
*1
2. Input : Pull-up MOS Tr.
Output : CMOS
*2
1. Input : Programmable pull-up MOS Tr.
Output: N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output
: CMOS
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
Pull-up MOS Tr. is not provided in N-channel open drain output port.
The port operation related the option is different at reset.
Refer to the next table.
No.6748-2/20
LC86E7148
(2) Option
The option data is created by the option specified program “SU86K.EXE”.
program area by linkage loader “L86K.EXE”.
The created option data is linked to the
(3) ROM space
LC86E7148 and LC867100 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Program area
48K bytes
Program area
40K bytes
Program area
32K bytes
Program area
28K bytes
Program area
24K bytes
LC867148
LC867140
LC867132
LC867128
LC867124
Option data
area 256 bytes
Option
Data Area
Option
Data Area
Option
Data Area
Program area
20K bytes
Program area
16K bytes
Program area
12K bytes
Program area
8K bytes
LC867120
LC867116
LC867112
LC867108
No.6748-3/20
LC86E7148
How to use
(1) Specification of option
The LC86E7148 must be programmed after specifying option data. The option is specified by “SU86K.EXE”. The
specified option file and the file created by our macro assembler “M86K.EXE” are linked by our linkage loader
“L86K.EXE” which creates .HEX file, then the option code is put in the option specified area (0FF00H to 0FFFFH) of
its .HEX file.
(2) How to program for the EPROM
The LC86E7148 can be programmed by EPROM programmer with attachment ; W86EP7148Q
• Recommended EPROM programmer
Productor
Advantest
Andou
AVAL
Minato electronics
EPROM programmer
R4945, R4944, R4943
AF-9704
PKW-1100, PKW-3000
MODEL1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available.
jumper (DASEC) must be set to ‘OFF’ at programming.
The address must be set to “0 to 0FFFFH” and a
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK=>PROGRAM=>VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
(4) How to eliminate
The programming data can be erased by using the EPROM eraser.
(5) Shielding
The UVEPROM (ultraviolet erasable programmable ROM) is in it.
Put the seal on the window in use.
Data security
Not data security
W86EP7148Q
No.6748-4/20
COM1/PL1
COM2/PL2
COM3/PL3
VSS2
VDD2
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM0
P70/INT0
RES
XT1/P74
XT2/P75
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P90/DA0
P91/DA1
P92/DA2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COM0/PL0
V1/PL4
V2/PL5
V3/PL6
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S13/PB5
S12/PB4
VSS3
VDD3
LC86E7148
Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
S0/PA0
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P93/DA3
No.6748-5/20
LC86E7148
System Block Diagram
Interrupt Control
IR
Stand-by Control
PLA
A15-A0
D7-D0
TA
CE
OE
DASEC
EPROM
Control
RC
Clock
Generator
CF
EPROM(48KB)
X’tal
PC
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
Port 8
ALU
Timer 1
Port 9
Real Time Service
ADC
PSW
RAM
128 bytes
INT0 - 3
Nose Filter
RAR
LCD
Controller
DAC
RAM
S0 – S7 (PA)
Stack Pointer
S8 – S13 (PB)
S16 – S23 (PC)
Port 0
S24 – S31 (PD)
COM0 – COM3(PL)
Watchdog Timer
No.6748-6/20
LC86E7148
Pin Description
Pin name
VSS1 *1
VSS2 *1
VSS3 *1
VDD1 *1
VDD2 *1
VDD3 *1
PORT0
P00 - P07
I/O
I/O
Function description
Power pin (–)
Power pin (–)
Power pin (–)
Power pin (+)
Power pin (+)
Power pin (+)
• 8-bit input/output port
Input/output in nibble units
• Input for port 0 interrupt
• Input for HOLD release
PORT1
P10 - P17
I/O
• 8-bit input/output port
Input/output can be specified in bit unit
• Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM output)
• 6-bit input port
Pull-up resistor :
• Other pin functions
Provided/Not provided
P70 : INT0 input/HOLD release input/
(specified in a bit)
N-channel Tr. output for watchdog timer
(P70, P71, P72, P73)
P71 : INT1 input/HOLD release input
* P74 , P75 don’t have the pull-up
P72 : INT2 input/timer 0 event input
resistor option.
P73 : INT3 input with noise filter/timer 0
event input
• Interrupt received form, vector address
rising falling rising
high
low
vector
&
level
level
falling
INT0
enable enable disable enable enable
03H
INT1
enable enable disable enable enable
0BH
INT2
enable enable enable disable disable
13H
INT3
enable enable enable disable disable 1BH
P74 : XT1 terminal for crystal oscillation
P75 : XT2 terminal for crystal oscillation
• 8-bit input port
• Other function
AD input port (8 port pins)
• 4-bit input/output port
• Other function
DA output port (4 port pins)
AD input port (4 port pins)
PORT7
P70
I/O
P71 - P73
I
P74 - P75
I
Port8
P80 – P87
I
PORT9
P90 - P93
I/O
Option
• Pull-up resistor :
Provided/Not provided
(specified in nibble units)
• Output form (P00 – P07) :
CMOS/N-channel open drain
(specified in a bit)
• Output form :
CMOS/N-channel open drain
(specified in a bit)
PROM mode
Data line
D0 to D7
Power for
programming
PROM control
signals
DASEC(*2)
OE(*3)
CE(*4)
No.6748-7/20
LC86E7148
Pin name
PORT A
(S0/PA0 –
S7/PA7)
PORT B
(S8/PB0 –
S13/PB5)
PORT C
(S16/PC0 –
S23/PC7)
I/O
I/O
Function description
• Segment output terminal for LCD display
• Can be used as a general input/output port
Option
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output port
-
Address input
A8 to A13
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output port
-
PROM control
signal input
•TA(*5)
Address input
•A14,A15
PORT D
(S24/PD0 –
S31/PD7)
PORT L
(COM0/PL0 –
COM3/PL3)
V1/PL4 –
V3/PL6
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output port
-
I/O
• Common output terminal for LCD display
• Can be used as a general input port
-
-
PROM mode
Address input
A0 to A7
I
• Bias power terminal for LCD drive
• Can be used as a general input port
I
Reset pin
RES
I
• Input pin for 32.768kHz crystal oscillation
XT1/ P74
In case of non use, connect to VDD.
• Other function
A general input port P74
XT2/P75
O
• Output pin for 32.768kHz crystal oscillation
In case of non use, should be left unconnected
( I ) • Other function
A general input port P75
CF1
I
Input pin for ceramic resonator oscillation
CF2
O
Output pin for ceramic resonator oscillation
* All of port options can be specified in bit unit except the pull-up resistor of port 0.
[Notes] • The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other.
• The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
LSI
VDD1
Power
Supply
VDD2
VDD3
VSS1 VSaS2 VSS3
*2
*3
*4
*5
Memory select input for data security
Output enable input
Chip enable input
TA ! PROM control signal input
No.6748-8/20
LC86E7148
1. Absolute Maximum Ratings at Ta=25°C, VSS=VSS1=VSS2=VSS3=0V
Parameter
Symbol
Supply voltage
VDDMAX
LCD display
voltage
Input voltage
VLCD
VI
Input/output
voltage
VIO
High
level
output
current
IOPH(1)
IOPH(2)
IOPH(3)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
IOPL(1)
IOPL(2)
IOPL(3)
IOPL(4)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
Pdmax
Low
level
output
current
Peak
output
current
Total
output
current
Peak
output
current
Total
output
current
Maximum power
dissipation
Operating
temperature
range
Storage
temperature
range
Pins
VDD1, VDD2
VDD3
V1/PL6, V2/PL5
V3/PL4
•Ports 71, 72, 73
•Ports 74 , 75
•Port 8, Port L
• RES
•Ports 0, 1
•Port 9
•Ports A, B, C, D
Ports 0, 1
Ports A, B, C, D
Port 9
Ports 0, 1
Ports A, B
Ports C, D
Port 9
Ports 0, 1
Ports A, B, C, D
Port 9
Port 70
Ports 0, 1
Ports A, B
Ports C, D
Port 9
Port 70
QIC80S
Conditions
VDD1=VDD2=
VDD3
VDD1=VDD2=
VDD3
•CMOS output
•At each pins
Total all pins
Total all pins
Total all pins
Total all pins
At each pins
At each pins
At each pins
At each pins
Total all pins
Total all pins
Total all pins
Total all pins
Total all pins
Ta=+10 to+40°C
VDD[V]
min.
-0.3
Ratings
typ.
max.
+7.0
-0.3
VDD
-0.3
VDD+0.3
-0.3
VDD+0.3
-4
-4
-4
-30
-20
-20
-20
unit
V
mA
20
20
20
15
40
24
24
15
10
515
mW
°C
Topr
+10
+40
Tstg
-65
+150
Notes •The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
•After pre-baking a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6748-9/20
LC86E7148
2. Recommended Operating Range at Ta=+10°C to +40°C, VSS=0V
Parameter
Symbol
Pins
Operating
supply voltage
range
VDD(1)
Hold voltage
VHD
VDD1,VDD2,VDD3
Input high
voltage
VIH(1)
Port 0
VDD(2)
VIH(2)
VIH(3)
VIH(4)
VIH(5)
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
Operation
cycle time
VDD1,VDD2,VDD3
tCYC
•Ports 1, 9
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
•Port 70
Port input/interrupt
•Port 71
• RES (Schmitt)
Port 70
Watchdog timer
•Port 8
Port 0
•Ports 1, 9
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
•Port 70
Port input/interrupt
•Port 71
• RES (Schmitt)
Port 70
Watchdog timer
•Port 8
Conditions
0.98µs ≤ tCYC
≤ 400µs
3.9µs ≤ tCYC
≤ 400µs
RAMs and the
registers hold
voltage at HOLD
mode.
Output disable
VDD[V]
min.
4.5
Ratings
typ.
max.
6.0
2.5
6.0
2.0
6.0
4.5-6.0
0.4VDD
VDD
Output disable
4.5-6.0
+0.9
0.75VDD
VDD
Output N-channel
Tr. OFF
4.5-6.0
0.75VDD
VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Output disable
Output disable
4.5-6.0
0.9VDD
VDD
4.5-6.0
0.75VDD
VDD
4.5-6.0
4.5-6.0
VSS
VSS
0.2VDD
0.25VDD
Output N-channel
Tr. OFF
4.5-6.0
VSS
0.25VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
4.5-6.0
VSS
0.8VDD
4.5-6.0
VSS
-1.0
0.25VDD
4.5-6.0
4.5-6.0
0.98
3.9
400
400
unit
V
µs
No.6748-10/20
LC86E7148
Parameter
Symbol
Oscillation
FmCF(1)
frequency
range
(Note 1) FmCF(2)
FmRC
FsXtal
Oscillation
tmsCF(1)
stabilizing
time period
(Note 1)
tmsCF(2)
tssXtal
Pins
CF1, CF2
CF1, CF2
XT1, XT2
CF1, CF2
CF1, CF2
XT1, XT2
Conditions
•6MHz (ceramic
resonator oscillation)
•Refer to figure 1
•3MHz (ceramic
resonator oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
(crystal oscillation)
•Refer to figure 2
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•32.768kHz
(crystal oscillation)
•Refer to figure 3
VDD[V]
4.5-6.0
min.
5.88
Ratings
typ.
6
max.
6.12
4.5-6.0
2.94
3
3.06
4.5-6.0
4.5-6.0
0.4
0.8
32.768
3.0
4.5-6.0
unit
MHz
kHz
ms
4.5-6.0
4.5-6.0
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6748-11/20
LC86E7148
3. Electrical Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter
Input high
current
Symbol
IIH(1)
•Port 1
•Port 0 without
pull-up MOS Tr.
IIH(2)
•Port 7 without
pull-up MOS Tr.
•Port 8
Port 9
Ports A, B, C, D, L
IIH(3)
IIH(4)
IIH(5)
IIH(6)
Input low
current
•Port 1
•Port 0 without
pull-up MOS Tr.
IIL(2)
•Port 7 without
pull-up MOS Tr.
•Port 8
Port 9
Ports A, B, C, D, L
VOH(1)
VOH(2)
Output low
voltage
RES
Ports 74 ,75
IIL(1)
IIL(3)
IIL(4)
IIL(5)
IIL(6)
Output high
voltage
Pins
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
VOL(6)
VOL(7)
RES
Ports 74 ,75
Ports 0,1 of
CMOS output
•Port 9 of CMOS
output
•Ports A, B, C, D
of CMOS output
Ports 0, 1
Port 70
Port 9
Ports A, B, C, D
of CMOS output
Conditions
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VDD
(including the offleak current of the
output Tr.)
VIN=VDD
VDD[V]
4.5-6.0
min.
Ratings
typ.
max.
1
4.5-6.0
1
VIN=VDD
VIN=VDD
VIN=VDD
Using as port
VIN=VDD
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VSS
(including the offleak current of the
output Tr.)
VIN=VSS
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
1
1
1
1
4.5-6.0
-1
4.5-6.0
-1
VIN=VSS
VIN=VSS
VIN=VSS
Using as port
VIN=VSS
IOH=-1.0mA
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
-1
-1
-1
-1
4.5-6.0
VDD-1
IOH=-1.0mA
4.5-6.0
VDD-1
IOL=10mA
IOL=1.6mA
IOL=1mA
IOL=6mA
IOL=1.2mA
IOL=8mA
IOL=1.6mA
Continue.
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
unit
µA
V
1.5
0.4
0.4
1.5
0.4
1.5
0.4
No.6748-12/20
LC86E7148
Parameter
LCD output
regulation
LCD ladder
resistor
Symbol
Pins
VODLS
S0 to S13,
S16 to S31
VODLC
COM0 to COM3
Conditions
RLCD(1)
RLCD(2)
Pull-up MOS
Tr. resistor
Rpu
Hysteresis
voltage
VHIS
Pin capacitance
CP
•Ports 0, 1
•Ports A, B, C, D
•Ports 70, 71, 72, 73
•Ports 0, 1
•Ports 70, 71, 72, 73
• RES
All pins
•Deference voltage
to ideal value
•VLCD, 2/3VLCD,
1/3VLCD
•Deference voltage
to ideal value
•VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
Resistance at a
ladder resistor
•Resistance at a
ladder resistor
•1/2R mode
VOH=0.9VDD
VDD[V]
4.5-6.0
min.
0
4.5-6.0
0
Ratings
typ.
60
4.5-6.0
30
15
unit
V
±0.2
4.5-6.0
4.5-6.0
max.
±0.2
kΩ
40
70
Output disable
4.5-6.0
0.1VDD
V
•f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
4.5-6.0
10
pF
4. Serial Input / Output Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Pins
Input clock
Symbol
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set up time
tCKCY(1) SCK0,
SCK1
tCKL(1)
Output clock
Serial output
Serial input
Serial clock
Parameter
tCKCY(2) SCK0,
SCK1
tCKL(2)
Data hold time
tCKI
Output delay time
(Serial clock is
external clock)
tCKO(1)
Output delay time
(Serial clock is
internal clock)
tCKO(2)
Conditions
Refer to figure 5.
tCKH(1)
tCKH(2)
tICK
•SI0,SI1
•SB0,SB1
•SO0, SO1
•SB0, SB1
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Refer to figure 5.
•Data set-up to
SCK0, 1
•Data hold from
SCK0, 1
•Refer to figure 5.
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Data hold from
SCK0, 1
•Refer to figure 5.
VDD[V]
4.5-6.0
4.5-6.0
min.
2
1
4.5-6.0
1
4.5-6.0
4.5-6.0
2
Ratings
typ.
max.
unit
tCYC
1/2
tCKCY
1/2
tCKCY
4.5-6.0
4.5-6.0
0.1
4.5-6.0
0.1
µs
4.5-6.0
7/12tCYC
+0.2
4.5-6.0
1/3tCYC
+0.2
No.6748-13/20
LC86E7148
5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter
High/low level
pulse width
Symbol
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Pins
Conditions
VDD[V]
4.5-6.0
min.
1
4.5-6.0
2
•Interrupt acceptable
•Timer0-countable
4.5-6.0
32
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
4.5-6.0
128
RES
Reset acceptable
4.5-6.0
200
Ratings
typ.
max.
unit
tCYC
µs
6. AD Converter Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Resolution
NAD
Absolute precision ETAD
(Note 2)
Conversion time
tCAD
Analog input
voltage range
Analog port
input current
VAIN
IAINH
IAINL
Conditions
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
AN0 - AN11
VAIN=VDD
VAIN=VSS
Ratings
typ.
8
max.
unit
VDD[V]
4.5-6.0
4.5-6.0
min.
4.5-6.0
15.68
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
4.5-6.0
VSS
VDD
V
4.5-6.0
4.5-6.0
1
µA
-1
±1.5
bit
LSB
µs
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6748-14/20
LC86E7148
7. DA Converter Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter
Symbol
Resolution
Total error
NDA
Settling time
Analog output
voltage range
tSAD
VAOUT
Output resistor
RODA
Pins
DA0 to DA3
Conditions
8 bit mode
9 bit mode
9.5 bit mode
(Note 4)
8 bit mode
9 bit mode (1)
9 bit mode (2)
9.5 bit mode
(Note 5)
VDD[V]
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
min.
Ratings
typ.
8
max.
1.0
0.8
0.7
0.5
VDD
1/2VDD
VDD
2/3VDD
VSS
VSS
1/2VDD
1/3VDD
4.5-6.0
4
unit
bit
%
µs
V
kΩ
(Note 4) Settling time means the time from executing the DA conversion instruction to generating the analog voltage output
corresponding to the digital data on the specific port.
(Note 5) DA data = 80H
8. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter
Current dissipation
during basic
operation
(Note 6)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
Pins
VDD1=
VDD2=
VDD3
Conditions
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Ratings
typ.
15
max.
30
4.5-6.0
6
15
4.5-6.0
4
13
4.5-6.0
4
9
VDD[V]
4.5-6.0
min.
unit
mA
Continue.
No.6748-15/20
LC86E7148
Parameter
Symbol
Current dissipation
IDDHALT(1)
in HALT mode
(Note 6)
Pins
VDD1=
VDD2=
VDD3
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
Current dissipation
IDDHOLD(1) VDD1=
in HOLD mode
VDD2=
(Note 6)
VDD3
Conditions
•HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
HOLD mode
Ratings
typ.
6
max.
11
4.5-6.0
2.2
9
4.5-6.0
500
1700
4.5-6.0
25
100
4.5-6.0
0.05
30
VDD[V]
4.5-6.0
min.
unit
mA
µA
(Note 6) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6748-16/20
LC86E7148
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type
Maker
Oscillator
C1
C2
6MHz ceramic resonator
Murata
CSA6.00MG
33pF
33pF
oscillation
CST6.00MGW
on chip
KBR-6.0MSA
33pF
33pF
Kyocera
PBRC6.00A(chip
33pF
33pF
type)
KBR-6.0MKS
on chip
PBRC6.00B(chip
type)
3MHz ceramic resonator
Murata
CSA3.00MG
33pF
33pF
oscillation
CST3.00MGW
on chip
Kyocera
KBR-3.0MS
47pF
47pF
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub clock)
Oscillation type
Maker
Oscillator
C3
32.768kHz crystal
oscillation
C4
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL
characteristics.)
(Notes)
•Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation
pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
X’tal
CF
C1
Figure 1
C2
Ceramic oscillation circuit
C3
C4
Figure 2
Crystal oscillation circuit
No.6748-17/20
LC86E7148
VDD
VDD limit
Power supply
0V
Reset time
RES
Internal RC
resonator oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed
Reset
Instruction
execution mode
OCR6=1
Instruction execution mode
<Reset time and oscillation stable time>
HOLD release signal
Valid
Internal RC
resonator oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3
Oscillation stable time
No.6748-18/20
LC86E7148
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4
Reset circuit
0.5VDD
<AC timing point>
tCKCY
tCKL
VDD
tCKH
SCK0
SCK1
1kΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 5
<Test load>
Serial input / output test condition
tPIL
Figure 6
tPIH
Pulse input timing condition
No.6748-19/20
LC86E7148
PS No.6748-20/20