VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION FEATURES The SC1103 is a versatile, low-cost, voltagemode PWM controller designed for use in single ended DC/DC power supply applications. A simple, fixed-voltage buck regulator can be implemented using the SC1103 with a minimum of external components. Internal level shift and drive circuitry eliminates the need for an expensive pchannel, high-side switch. The small device footprint allows for compact circuit design. • • • • • • SC1103 features include a temperature compensated voltage reference, triangle wave oscillator, current limit comparator, frequency shift overcurrent protection, and an internally compensated error amplifier. Pulse by pulse current limiting is implemented by sensing the differential voltage across an external resistor, or an appropriately sized PC board trace. The SC1103 operates at a fixed frequency of 200kHz, providing an optimum compromise between efficiency, external component size, and cost. PIN CONFIGURATION SC1103 Low cost / small size Switch mode efficiency (90%) 1% reference voltage accuracy Over current protection 500mA output drive 5V to 12V Input power source APPLICATIONS • • • • • Pentium® P55 Core Supply Low Cost Microprocessor Supplies Peripheral Card Supplies Industrial Power Supplies High Density DC/DC Conversion ORDERING INFORMATION (1) DEVICE SC1103CS PACKAGE TEMP RANGE (T J) SO-8 0° to 125°C Note: (1) Add suffix ‘TR’ for tape and reel. BLOCK DIAGRAM Top View (SO-8) Pentium is a registered trademark of Intel Corporation © 2000 SEMTECH CORP. 1 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER SC1103 PRELIMINARY - February 29, 2000 PIN DESCRIPTION Pin # Pin Name Pin Function 1 VCC Device Input Voltage 2 Cs(-) Current Sense Input (Negative) 3 Cs(+) Current Sense Input (Positive) 4 PGND Device Power Ground 5 DH High Side Driver Output 6 BST High Side Driver VBST (Boost) 7 FB 8 GND Error Amplifier Input (-) Small Signal Ground ABSOLUTE MAXIMUM RATINGS Parameter Input Voltage Symbol VCC to GND Maximum -0.3 to 14 Units V Ground Differential PGND to GND ±1 V Boost Input Voltage BST to GND -0.3 to +26 V Operating Temperature TA 0 to +70 °C Storage Temperature TS -45 to +125 °C Lead Temperature (Soldering) 10 seconds TL 300 °C Thermal Resistance, Junction to Ambient θ JA 165 °C/W Thermal Resistance, Junction to Case θ JC 40 °C/W 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER SC1103 PRELIMINARY - February 29, 2000 ELECTRICAL CHARACTERISTICS VCC = 11.50V to 12.50V; GND = PGND = 0V; VO = 3.3V; TA = 25°C; BST = 24+1V; Output current = 2A. Per test circuit, unless otherwise specified. PARAMETER SYMBOL Reference CONDITIONS VREF Over Temp MIN TYP MAX UNITS 1.238 1.250 1.263 V 1.225 1.250 1.275 V 2.0 8.0 uA Feedback Bias Current IFB Quiescent Current IQ Current into VCC pin 5.0 8.0 mA Regulation Load REGLOAD IO = 1A to 10A 0.5 1.0 % Regulation Line REGLINE IO = 10A 0.5 % Current Limit Threshold CLT CS(+) to CS(-) Oscillator Frequency OSC Oscillator Frequency Shift OFS Max Duty Cycle d.c. DH Sink/Source Current 70 80 mV 180 200 220 kHz VFB < VREF/2 90 50 kHz 95 % 500 VBST - VDH = 4.5V (VDH - VPGND = 2V) IO UVLO Threshold 60 mA VUVLO 3.8 V TEST CIRCUIT L1 5.6uH Q1 IRL3103S +12V R5 0.01 Vout(+) R6 *see note C1 0.1 C2 820/16V C3 820/16V C9 1500/6.3 C4 820/16V D1 MBRB1530CT C10 1500/6.3 C11 1500/6.3V C12 0.1 R7 124 Vout(-) GND R1 10 U1 SC1103 1 R2 1k C5 0.1 R3 1k 2 C6 0.1 3 4 VCC GND 8 Cs(-) FB 7 Cs(+) BST PGND DH R4 2.7 C7 0.01 6 5 C8 0.1 * NOTE: R6 = 124 x (Vout/1.25 - 1) rounded to nearest 1%value + 20 to 24V 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER SC1103 PRELIMINARY - February 29, 2000 40 180 35 0.050 30 135 Phase (deg) Gain (dB) 20 90 15 Gain Phase 10 45 5 Voltage Change (V) Normalized to 0 at Io=2A. 0.040 25 0.030 0.020 0.010 0.000 -0.010 0 0 -0.020 0 -5 2 4 6 8 10 Current (Amps) -10 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 -45 10.0E+6 Frequency (Hz) Fig.1: Error Amplifier, Gain and Phase Fig. 2: Load Regulation @ VO = 3.3V, VIN = 12V 1.0% 0.8% Load Regulation 0.6% 0.4% Vo= 1.8V 2.5V 3.3V 5.0V 0.2% 0.0% -0.2% -0.4% -0.6% -0.8% -1.0% 0 2 4 6 8 10 12 14 Output Current, (A) Fig. 4: Load Regulation @ VIN = 12V Fig. 3: VRIPPLE @ VIN = 12V, VO = 3.3V, IO = 10A 0.5% 100% 0.4% 90% 0.3% Efficiency 1.8V 2.5V 3.3V 5V 70% 60% Line Regulation 0.2% 80% 0.1% 0.0% -0.1% -0.2% -0.3% 50% -0.4% 40% 0 2 4 6 8 Output Current, (A) Fig. 5: Efficiency @ VIN = 12V 10 12 14 -0.5% 11.4 11.6 11.8 12.0 12.2 12.4 12.6 Input Voltage, (V) Fig. 6: Line Regulation @ VO = 3.3V, IO = 10A 4 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER SC1103 PRELIMINARY - February 29, 2000 LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1103 PWM controller. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom Schottky ground. and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1103 is best placed over an isolated ground plane area. GND and PGND should be returned to this 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Schottky (D1) must be kept isolated ground. This isolated ground area should be connected to the main ground by a trace that runs as small as possible. This loop contains all the high current, fast transition switching. Connections should from the GND pin to the ground side of (one of) the be as wide and as short as possible to minimize loop output capacitor(s). If this is not possible, the GND pin inductance. Minimizing this loop area will reduce EMI, may be connected to the ground path between the lower ground injection currents, resulting in electrically Output Capacitor(s) and the Cin, Q1, D1 loop. Under “cleaner” grounds for the rest of the system and mini- no circumstances should GND be returned to a ground inside the Cin, Q1, D1 loop. mize source ringing, resulting in more reliable gate switching signals. 6) Vcc for the SC1103 should be supplied from the VIN supply through a 10Ω resistor, the Vcc pin should 3). The connection between the junction of Q1, D1 12V 24V IN 10 0.1uF 2.32k Cin Q1 SC1103CS 1 2 3 0.1uF 4 VCC GND CS(-) FB CS(+) BST PGND DH + 1.00k 8 5mOhm Vout 7 4uH Rb 6 + D1 Cout 5 Ra Heavy lines indicate high current paths. Fig. 7 Layout diagram for the SC1103 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER SC1103 PRELIMINARY - February 29, 2000 Under Voltage Lockout The under voltage lockout circuit of the SC1103 assures that the high-side MOSFET driver outputs remain 7) The Current Sense resistor and the divider across it in the off state whenever the supply voltage drops beshould form as small a loop as possible, the traces runlow set parameters. Lockout occurs if VCC falls below ning back to CS(+) and CS(-) on the SC1103 should 3.8V. Normal operation resumes once VCC rises above run parallel and close to each other. The 0.1µF capaci3.8V. tor should be mounted as close to the CS(+) and CS(-) pins as possible. be decoupled directly to GND by a 0.1µF ceramic capacitor, trace lengths should be as short as possible. 8) To minimize noise pickup at the sensitive FB pin, the feedback resistors should both be close to the SC1103 with the bottom resistor (Rb) returned to ground at the GND pin. TYPICAL APPLICATIONS L1 5.6uH Q1 IRL3103S +5V R5 0.012 +3.3V R6 205 C1 0.1 C2 1500/6.3V D1 MBRB1530CT C3 1500/6.3V C9 1500/6.3 C10 1500/6.3 C11 1500/6.3V C12 0.1 R7 124 GND GND R1 10 U1 SC1103 1 R2 1k C5 0.1 R3 1k C6 0.1 VCC GND 8 2 Cs(-) FB 7 3 Cs(+) BST 6 4 PGND DH 5 R4 2.7 C7 0.01 C8 0.1 +12V Fig. 8: 5V to 3.3V @ 8A 6 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER SC1103 PRELIMINARY - February 29, 2000 TYPICAL APPLICATIONS (cont.) D2 C6 0.1 LL42 L1 6.8uH Q1 Si4420DY +5V R5 0.012 +2.5V R6 124 C1 0.1 C7 1500/6.3V C2 1500/6.3V C8 0.1 D1 MBRD340 R7 124 GND GND R1 10 U1 SC1103 1 VCC GND 8 2 Cs(-) FB 7 3 Cs(+) BST 6 4 PGND DH 5 R4 2.7 C5 0.01 R2 1k C4 0.1 C3 0.1 Fig. 9: 5V to 2.5V @ 4A with “flying capacitor” boost voltage. D2 LL42 C8 0.1 L1 5.6uH Q1 IRL3103S +12V R5 0.01 Vout(+) R6 205 C1 0.1 C2 820/16V C3 820/16V C9 1500/6.3 C4 820/16V D1 MBRB1530CT C10 1500/6.3 C11 1500/6.3V C12 0.1 3.3V R7 124 Vout(-) GND R1 10 U1 SC1103 1 R2 1k C5 1.0 R3 1k C6 0.1 R4 2.7 8 VCC GND 2 Cs(-) FB 7 3 Cs(+) BST 6 4 PGND DH 5 C7 0.01 Fig. 10: 12V to 3.3V @ 10A with “flying capacitor” boost voltage. 7 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER SC1103 PRELIMINARY - February 29, 2000 OUTLINE DRAWING JEDEC REF: MS-012AA LAND PATTERN SO-8 ECN00-899 8 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA