PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS PRELIMINARY - October 3, 2000 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION FEATURES •= Low cost / full featured •= Synchronous operation •= 5 Bit VID programmable output •= On-chip power good and OVP functions •= Designed to meet Intel VRM 8.4 (Pentium® IlI) •= 1.3V to 3.5V Range, 1% tolerance The SC1153 is a low-cost, full featured, synchronous voltage-mode controller designed for use in single ended power supply applications where efficiency is of primary concern. Synchronous operation allows for the elimination of heat sinks in many applications. The SC1153 is ideal for implementing DC/DC converters needed to power advanced microprocessors, such as Pentium® lll, in both single and multiple processor configurations. Internal level-shift, high-side drive circuitry, and preset shoot-thru control, allows for use of inexpensive n-channel power switches. APPLICATIONS •= Pentium® IlI Core Supply •= Multiple Microprocessor Supplies •= Voltage Regulator Modules (VRM) •= Programmable Power Supplies •= High Efficiency DC/DC Conversion SC1153 features include an integrated 5-bit VID DAC, temperature compensated voltage reference, triangle wave oscillator, current limit comparator, frequency shift over-current protection, and an accessible, internally compensated error amplifier. Power good signaling, logic compatible shutdown, and over voltage protection are also provided. ORDERING INFORMATION (1) DEVICE PACKAGE TEMP. RANGE (TJ) SO-20 0 - 125°C SC1153CSW.TR The SC1153 operates at a fixed 200KHz, providing an optimum compromise between efficiency, external component size, and cost. PIN CONFIGURATION SC1153 Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. BLOCK DIAGRAM Top View VCC CS- CS+ SHUTDOWN BSTH CURRENT LIMIT 1.25V REF UPPER FET LEVEL SHIFT AND DRIVE 70mV DH VID4 D/A VID3 R VID2 PGNDH Q OSCILLATOR VID1 S VID0 200kHz VOSENSE SHOOT-THRU CONTROL OPEN COLLECTORS PWRGOOD VCC BSTL ERROR AMP SYNCHRONOUS FET DRIVE DL (20-Pin SOIC) OVP PGNDL GND Pentium is a registered trademark of Intel Corporation © 2000 SEMTECH CORP. 1 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS SC1153 PRELIMINARY - October 3, 2000 ABSOLUTE MAXIMUM RATINGS Parameter Symbol VIN VCC to GND PGND to GND BST to GND Thermal Resistance θJC Junction to Case Thermal Resistance θJA Junction to Ambient Operating TA Temperature Range Storage TSTG Temperature Range Lead Temperature TLEAD (Soldering) 10 sec Maximum -0.3 to 7 ±1 -0.3 to 15 Units V V V 30 °C/W 90 °C/W 0 to 70 °C -65 to +150 °C 300 °C ELECTRICAL CHARACTERISTICS Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC PARAMETER CONDITIONS MIN (1) TYP MAX Output Voltage IO = 2A See Output Voltage Table. Supply Voltage VCC 4.2 Supply Current VCC = 5.0 Load Regulation IO = 0.3A to 15A(1) Line Regulation All VID codes Gain (AOL) VOSENSE to VO 7 (1) UNITS V 5 mA 1 % 0.5 % 35 dB Current Limit Voltage 60 70 80 mV Oscillator Frequency 180 200 220 kHz Oscillator Max Duty Cycle 90 95 % DH Sink/Source Current BSTH - DH = 4.5V, DH - PGNDH = 2V 1 A DL Sink/Source Current BSTL - DL = 4.5V, DL - PGNDL = 2V 1 A OVP Threshold Voltage OVP Source Current 120 VOVP = 3V % 10 Power Good Threshold Voltage 90 Dead Time 50 mA 110 100 % ns NOTE: (1) Specification refers to application circuit (Figure 1.). (2) This part is ESD sensitive. Use of standard ESD handling precautions is required. 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS SC1153 PRELIMINARY - October 3, 2000 PIN DESCRIPTION Pin # Pin Name Pin Function 1 GND Small Signal Analog and Digital Ground 2 VCC Chip Supply Voltage 3 OVP High Signal Out if VO > Setpoint + 20% (1) 4 PWRGOOD 5 CS(-) Current Sense Input (negative) 6 CS(+) Current Sense Input (positive) 7 PGNDH Power Ground for High Side Switch 8 DH High Side Driver Output 9 NC Not Connected 10 PGNDL Power Ground for Low Side Switch 11 DL Low Side Driver Output 12 BSTL Vcc for Low Side Driver (Boost) 13 BSTH Open collector logic output, high if VO within 10% of setpoint Vcc for High Side Driver (Boost) (1) 14 SHUTDOWN 15 VOSENSE 16 (1) Programming Input (MSB) 17 (1) VID3 Programming Input 18 VID2(1) Programming Input 19 (1) Programming Input (1) Programming Input (LSB) 20 VID4 VID1 VID0 Logic Low shuts down the converter Top end of internal feedback chain NOTE: (1) All logic level inputs and outputs are open collector TTL compatible. PIN CONFIGURATION 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS SC1153 PRELIMINARY - October 3, 2000 APPLICATION CIRCUIT L1 Q1 R1 5mOhm 5V IN C6 1000uF C8 1000uF C10 1000uF VCCP 4 uH + C3 1000uF C1 0.1uF + + R2 10k Q2 C2 1000uF C4 1000uF + + D1 1N5817 + + R5 10 C5 1000uF + + C7 1000uF C9 1000uF C12 0.1uF 12V IN R4 1.00k R3 2.32k U1 2 OVP 3 VID0 20 VID1 19 VID2 18 VID3 17 VID4 14 VCC OVP CS- VID0 VOSENSE VID1 PWRGOOD VID2 VID4 VID3 BSTH SHUTDOWN 1 GND 10 C13 0.1uF CS+ PGNDL 9 NC DH PGNDH DL BSTL C11 6 0.1uF 5 15 4 16 13 8 7 11 12 SC1153CS SHUTDOWN PWRGOOD ® Pentium ll Power Supply Figure 1. MATERIALS LIST Quantity Reference Part/Description Vendor Notes 4 C1,C11-C13 0.1µF Ceramic Various 9 C2-C10 1000µF/6.3V SANYO 1 D1 1N5817 Various 1 L1 4µH 2 Q1, Q2 See notes See notes FET selection requires trade-off between efficiency and cost. Absolute maximum RDS(ON) = 22 mΩ 1 R1 5mΩ IRC OAR-1 Series 1 R2 10kΩ, 5%, 1/8W Various 1 R3 2.32kΩ, 1%, 1/8W Various 1 R4 1kΩ, 1%, 1/8W Various 1 R5 10Ω, 5%, 1/8W Various 1 U1 SC1153CS SEMTECH MV-GX or equiv. Low ESR 8 Turns 16AWG on MICROMETALS T50-52D core 4 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS SC1153 PRELIMINARY - October 3, 2000 OUTPUT VOLTAGE TABLE Unless specified: VCC = 5.00V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25°C PARAMETER Output Voltage CONDITIONS IO = 2A in Application Circuit (Figure 1) VID 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 MIN TYP MAX 1.287 1.336 1.386 1.435 1.485 1.534 1.584 1.633 1.683 1.732 1.782 1.832 1.881 1.931 1.980 2.030 1.980 2.079 2.178 2.277 2.376 2.475 2.574 2.673 2.772 2.871 2.970 3.069 3.168 3.267 3.366 3.465 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 2.050 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200 3.300 3.400 3.500 1.313 1.364 1.414 1.465 1.515 1.566 1.616 1.667 1.717 1.768 1.818 1.868 1.919 1.969 2.020 2.070 2.020 2.121 2.222 2.323 2.424 2.525 2.626 2.727 2.828 2.929 3.030 3.131 3.232 3.333 3.434 3.535 UNITS V 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS SC1153 PRELIMINARY - October 3, 2000 CHARACTERISTIC CURVES SC1153 Efficiency in Application Circuit (Figure 1). 100% 95% Efficiency 90% Vo=3.5V 85% 3.0V 2.5V 80% 1.8V 2.0V 75% 70% 0 2 4 6 8 10 Output Current (Amps) 12 14 16 12 14 16 SC1153 Regulation in Application Circuit (Figure 1). 0 ∆ Vout (mV) -5 -10 -15 -20 -25 0 2 4 6 8 10 Output Current (Amps) 6 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS SC1153 PRELIMINARY - October 3, 2000 OUTLINE DRAWING SO-20 Ref. MS-013AC THEORY OF OPERATION The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200kHz. The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has turned off, and visa-versa. The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an overcurrent condition. The latch is reset at the start of each oscillator period. The PWRGOOD and OVP signals are derived from the voltage at the VOSENSE pin by comparators fed from the internal feedback chain. ECN00-1346 7 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320