TDA7429L 3 BAND EQUALIZER AUDIO PROCESSOR WITH SUBWOOFER CONTROL ■ 3 STEREO INPUTS ■ AUXILIARY MONO INPUT ■ INPUT ATTENUATION CONTROL IN 0.5dB STEP ■ TREBLE MIDDLE AND BASS CONTROL ■ FOUR SPEAKERS ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ■ SUBWOOFER OUTPUT (L+R) CONTROLLED IN 1dB STEP INPUTS ■ ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS SDIP42 ORDERING NUMBER: TDA7429L an additional subwoofer control. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. DESCRIPTION The TDA7429L is volume tone (bass middle and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems, providing also Figure 1. Test Circuit 2.2µF 2.2µF 0.47µF BASSO_R VAR_R 14 BASSO_L 13 12 0.47µF MONO INPUT VAR_L 10 11 0.47µF R_IN3 R_IN2 40 39 L+R OUTPUT 9 N.C. 1 N.C. 2 N.C. 3 N.C. 4 N.C. 7 34 5 33 LP 100nF 100nF 5.6nF LP1 TREBLE_R TREBLE_L 36 35 42 6 MIDDLE_LO 2.7K L_IN3 MIDDLE_RO MIDDLE_RI 0.47µF 0.47µF VS 100nF CREF 220nF HP2 37 15 19 100nF BASS_LO 100nF 16 20 17 21 BASS_LI BASS_RO 5.6K 100nF 100nF 18 22 32 31 30 AUXOUT_L AUXOUT_R L_OUT March 2000 L_IN2 0.47µF 22µF 41 24 22nF 18nF L_IN1 10µF 18nF MIDDLE_LI 0.47µF MONITOR_L 8 MONITOR_R 2.7K R_IN1 23 100nF 22nF 38 29 R_OUT 28 27 DIG_GND SCL 26 SDA 25 AGND BASS_RI 5.6K D99AU1029 1/16 TDA7429L Figure 2. Pin Connection N.C. N.C. N.C. N.C. LP LP1 N.C. HP2 L+R OUTPUT MONO INPUT VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VS CREF R_IN3 R_IN2 R_IN1 MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND SCL SDA AGND TREBLE_L TREBLE_R MIDDLE_RI D99AU1028 Table 1. Quick Reference Data Symbol Parameter Min. Typ. Max. Unit 9 10.2 V VS Supply Voltage 7 VCL Max. input signal handling 2 THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 dB SC Channel Separation f = 1KHz 90 dB 0.1 % Treble Control (2db step) -14 +14 dB Middle Control (2db step) -14 +14 dB Bass Control (2dB step) -14 +14 dB Balance Control 1dB step (LCH, RCH) -79 0 dB Mute Attenuation 2/16 Vrms 100 dB R_IN3 0.47µF R_IN2 0.47µF R_IN1 0.47µF L_IN3 0.47µF L_IN2 0.47µF L_IN1 50K 50K 50K 50K 50K 50K 37 MONITOR_R 42 31.5dB control 31.5dB control VS 25 41 SUPPLY + HP2 22µF 8 Vref LP1 6 LPF 1 100nF LP 5 LPF 2 THE SWITCHES POSITION MATCHES THE RESET CONDITION 40 39 38 33 34 35 36 AGND MONITOR_L CREF 10 0.47µF L+R OUTPUT 9 L+R CONTROL OFF 23 5.6nF 2.7K 18nF 21 22nF RM MIDDLE TREBLE REAR SURR 3BAND FIX 5.6K 100nF RB 100nF 17 SURR REAR FIX 3BAND BASSO_R 79dB CONTROL MUTE REC ATT MUTE REC ATT 12 BASSO_L 79dB CONTROL I 2C BUS DECODER + LATCHES BASS 18 RB 15 BASS_LO 100nF BASS_LI BASS 16 5.6K 22nF 100nF 19 RM MIDDLE 22 20 TREBLE TREBLE_R 50K OFF OFF 24 TREBLE_L MIDDLE_LI MIDDLE_RI 0.47µF REARIN 2.7K 18nF BASS_RI MIDDLE_LO MIDDLE_RO 5.6nF BASS_RO 100nF 2.2µF 14 VAR_R 30K FIX VAR 30K VAR_L 13 VAR FIX 11 2.2µF - - + + 79dB CONTROL MUTE 31 29 28 26 27 30 AUXOUT_R R_OUT DIG GND SDA SCL L_OUT AUXOUT_L D99AU1030 SPKR ATT MUTE SPKR ATT 79dB CONTROL 32 TDA7429L Figure 3. Block Diagram. 3/16 TDA7429L Table 2. Thermal Data Symbol R th j-pins Description Thermal Resistance Junction-pins Value Unit 85 °C/W Max. Table 3. Absolute Maximum Ratings Symbol VS Parameter Value Unit 11 V -10 to 85 °C -55 to +150 °C Operating Supply Voltage Tamb Operating Ambient Temperature Tstg Storage Temperature Range Table 4. Electrical Characteristics (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified). Symbol Parameter Test Conditio n Min. Typ. Max. Unit SUPPLY VS Supply Voltage 7 9 10.2 V IS Supply Current 10 18 26 mA 60 80 35 50 2 2.5 Vrms 31.5 dB SVR Ripple Rejection LCH / RCH out, Mode = OFF dB INPUT STAGE RIN Input Resistance VCL Clipping Level CRANGE Control Range THD = 0.3% 65 KΩ AVMIN Min. Attenuation -1 0 1 dB AVMAX Max. Attenuation 31 31.5 32 dB A STEP Step Resolution 0.5 1 dB ±11.5 ±14.0 ±16.0 dB BASS CONTROL Gb Control Range B STEP Step Resolution 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ ±11.5 ±14.0 ±16.0 dB 1 2 3 dB 17.5 25 32.5 KΩ ±13.0 ±14.0 ±15.0 dB 1 2 3 dB RB Max. Boost/cut MIDDLE CONTROL Gm Control Range M STEP Step Resolution RM Max. Boost/cut Internal Feedback Resistance TREBLE CONTROL Gt Control Range TSTEP Step Resolution 4/16 Max. Boost/cut TDA7429L Table 4. Electrical Characteristics (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified). Symbol Parameter Test Conditio n Min. Typ. Max. Unit +4 dB 1.5 dB CONTROL L+R CRANGE Control Range - 11 S STEP Step Resolution 0.5 1 SPEAKER & AUX ATTENUATORS CRANGE Control Range S STEP Step Resolution EA VDC AMUTE RVEA 79 dB -0.5 1 1.5 dB -1.5 0 1.5 dB Av = -20 to -79dB -3 0 2 dB adjacent att. steps -3 0 3 mV Output Mute Condition +70 100 Input Impedance 21 30 Attenuation set error DC Steps Av = 0 to -20dB dB 39 KΩ AUDIO OUTPUTS NO(OFF) d SC Output Noise (OFF) Output Mute, Flat BW = 20Hz to 20KHz Distorsion Av = 0 ; Vin = 1Vrms Channel Separation VOCL Clipping Level ROUT Output Resistance VOUT DC Voltage Level d = 0.3% µVrms µVrms 4 5 0.01 0.1 % 70 90 dB 2 2.5 Vrms 20 40 70 3.8 Ω V MONITOR OUTPUTS d SC Distorsion Av = 0 ; Vin = 1Vrms Channel Separation VOCL Clipping Level ROUT Output Resistance VOUT DC Voltage Level d = 0.3% 0.01 0.1 % 70 90 dB 2 2.5 Vrms 20 50 70 4.5 Ω V BUS INPUTS VIL Input Low Voltage VIH Input High Voltage 3 IIN Input Current -5 VO Output Voltage SDA Acknowledge 1 IO = 1.6mA V V +5 mA 0.4 V 5/16 TDA7429L 1.0 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7429L and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 1.1 Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 1.2 Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 1.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 1.4 Acknowledge The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 1.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 4. Data validity on the 2I C bus SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 5. Timing Diagram of I2C bus SCL I2 CBUS SDA START 6/16 D99AU1032 STOP TDA7429L Figure 6. Acknowledge on the I2C bus SCL 1 2 3 7 8 9 SDA MSB START ACKNOWLEDGMENT FROM RECEIVER D99AU1033 2.0 SOFTWARE SPECIFICATION 2.1 Interface Protocol The interface protocol comprises: ■ A start condition (S) ■ A chip address byte, containing the TDA7429L address ■ A subaddress bytes ■ A sequence of data (N byte + achnowledge) ■ A stop condition (P) CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK DATA 1 to DATA n LSB B DATA MSB ACK LSB DATA ACK P D95AU226A ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment 3.0 EXAMPLES 3.1 No Incremental Bus The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK 0 DATA LSB X X MSB X D3 D2 D1 D0 ACK LSB DATA ACK P D95AU306 3.2 Incremental Bus The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from ”1XXX1010” to ”1XXX1111” of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK 1 DATA 1 to DATA n LSB X X X D3 D2 D1 D0 ACK MSB LSB DATA ACK P D95AU307 7/16 TDA7429L Table 5. Function Selection The first byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 B1 X2 X X 0 0 0 0 INPUT ATTENUATION B X X X 0 0 0 1 CONTROL OUT L+R & SUBWOOFER B X X X 0 0 1 0 NOT USED B X X X 0 0 1 1 BASS & NATURAL BASE B X X X 0 1 0 0 MIDDLE & TREBLE B X X X 0 1 0 1 SPEAKER ATTENUATION ”L“ B X X X 0 1 1 1 AUX ATTENUATION ”L” B X X X 1 0 0 0 AUX ATTENUATION”R” B X X X 1 0 0 1 INPUT MULTIPLEXER, & AUX OUT LSB INPUT ATTENUATION <1> <2> B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 Table 6. Input Attenuation Selection MSB D7 D6 D5 D4 D3 D2 D1 D0 0.5 dB STEPS X 0 0 0 0 X 0 0 1 -0.5 X 0 1 0 -1 X 0 1 1 -1.5 X 1 0 0 -2 X 1 0 1 -2.5 X 1 1 0 -3 X 1 1 1 -3.5 4 dB STEPS X 0 0 0 0 X 0 0 1 -4 X 0 1 0 -8 X 0 1 1 -12 X 1 0 0 -16 X 1 0 1 -20 X 1 1 0 -24 X 1 1 1 -28 INPUT ATTENUATION = 0 ~ -31.5dB D7 D6 X 0 8/16 D5 D4 D3 D2 D1 D0 L+R OUTPUT SWITCH (L+R) OUTPUT PIN ACTIVE TDA7429L Table 7. Out & (L+R) & Subwoofer Selection MSB D7 LSB D1 D0 SUBWOOFER CONTROL X D6 D5 D4 D3 D2 0 0 SUBWOOFER ON X 0 1 NOT ALLOWED X 1 0 SUBWOOFER OFF X 1 1 NOT ALLOWED OUT X 0 X 1 VAR FIX L+R CONTROL X 0 0 0 0 +4 X 0 0 0 1 +3 X 0 0 1 0 +2 X 0 0 1 1 +1 X 0 1 0 0 0 X 0 1 0 1 -1 X 0 1 1 0 -2 X 0 1 1 1 -3 X 1 0 0 0 -4 X 1 0 0 1 -5 X 1 0 1 0 -6 X 1 0 1 1 -7 X 1 1 0 0 -8 X 1 1 0 1 --9 X 1 1 1 0 -10 X 1 1 1 1 -11 Table 8. Bass Selection MSB LSB BASS D7 D6 D5 D4 D3 D2 D1 D0 2 dB STEPS X X X 1 0 0 0 0 -14 X X X 1 0 0 0 1 -12 X X X 1 0 0 1 0 -10 X X X 1 0 0 1 1 -8 X X X 1 0 1 0 0 -6 X X X 1 0 1 0 1 -4 X X X 1 0 1 1 0 -2 X X X 1 0 1 1 1 0 X X X 1 1 1 1 1 0 X X X 1 1 1 1 0 2 X X X 1 1 1 0 1 4 X X X 1 1 1 0 0 6 X X X 1 1 0 1 1 8 X X X 1 1 0 1 0 10 X X X 1 1 0 0 1 12 X X X 1 1 0 0 0 14 9/16 TDA7429L Table 9. Speaker/Aux Att. R & L Selection MSB D7 D6 D5 D4 D3 LSB SPEAKER/AUX ATT D2 D1 D0 1 dB STEPS X 0 0 0 0 X 0 0 1 -1 X 0 1 0 -2 X 0 1 1 -3 X 1 0 0 -4 X 1 0 1 -5 X 1 1 0 -6 X 1 1 1 -7 8 dB STEPS X 0 0 0 0 0 X 0 0 0 1 -8 X 0 0 1 0 -16 X 0 0 1 1 -24 X 0 1 0 0 -32 X 0 1 0 1 -40 X 0 1 1 0 -48 X 0 1 1 1 -56 X 1 0 0 0 -64 X 1 0 0 1 -72 MUTE X 1 0 1 X X 1 1 X X Notes: 1. X = INDIFFERENT 0.1 2. SPAEAKER/AU X ATTENUATI ON = 0dB to 79dB 10/16 TDA7429L Table 10. Middle & Treble Selection MSB D7 D6 D5 D4 LSB MIDDLE D3 D2 D1 D0 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 TREBLE 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 11/16 TDA7429L Table 11. Input/recout L & R Selection MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 INPUT MULTIPLEXER X 1 1 0 IN1 X 0 0 0 IN2 X 0 1 0 IN3 AUX OUT ”L” X 0 0 0 VAR 1 (3BAND) X 0 1 0 NOT ALLOWED X 1 0 0 VAR 3 (REAR) X 1 1 0 FIX AUX OUT ”R” X 0 0 0 VAR 1 (3BAND) X 0 1 0 NOT ALLOWED X 1 0 0 VAR 3 (REAR) X 1 1 0 FIX Table 12. Power on reset BASS & MIDDLE 2dB TREBLE 0dB SURROUND & OUT CONTROL + (L+R) CONTROL OFF + FIX + MAX. ATTENUATION SPEAKER/AUX ATTENUATION L & R MUTE INPUT ATTENUATION + (L+R) SWITCH MAX. ATTENUATION + ON NATURAL BASE OFF INPUT IN1 12/16 TDA7429L Figure 7. Pin: TREBLE-L, TREBLE-R Figure 10. Pin: CREF VS VS 20µA 20µA 20K 42K 25K 20K GND D95AU336 GND D95AU309 Figure 8. Pin: VOUT REF Figure 11. Pin: VAR-L, VAR-R VS VS 20µA 20µA SW GND 30K D95AU233A 10K GND Vref D95AU227 GND Figure 9. Pin: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4 Figure 12. Pin: LP1, LP VS VS 20µA 20µA 50K GND 10K GND VREF D94AU200 HP1 D94AU211 13/16 TDA7429L Figure 16. Pin: BASS-LI, BASS-RI, MIDDLE-LI, MIDDLE-R Figure 13. Pin: SCL, SDA VS 20µA 20µA GND 45K : Bass or 25K : MIDDLE GND D94AU205 BASS-LO BASS-RO,MIDDLE-LO,MIDDLE-RO Figure 14. Pin: MONO INPUT D95AU231A Figure 17. Pin: BASS-LO, BASS-RO, MIDDLELO,MIDDLE-RO VS VS 20µA 20µA SW (*) 50K GND GND Vref D95AU229 BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI (*) 45K : Bass 25K : MIDDLE Figure 15. Pin: L-OUT, R-OUT, MONITOR-L, MONITOR-R, LTR OUTPUT, BASSO-L, BASSO-R, AUXOUT_L, AUXOUT_R VS 20µA GND D95AU230 14/16 D95AU232 TDA7429L mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 5.08 0.20 A1 0.51 A2 3.05 3.81 4.57 0.120 B 0.38 0.46 0.56 0.0149 0.0181 0.0220 B1 0.89 1.02 1.14 0.035 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 D 36.58 36.83 37.08 1.440 E 15.24 16.00 0.60 E1 12.70 14.48 0.50 0.020 13.72 0.150 0.040 1.450 0.180 0.045 1.460 0.629 0.540 e 1.778 0.070 e1 15.24 0.60 0.570 e2 18.54 0.730 e3 1.52 0.060 L 2.54 OUTLINE AND MECHANICAL DATA MAX. 3.30 3.56 0.10 0.130 SDIP42 (0.600”) 0.140 E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 Gage Plane 1 e3 21 e2 SDIP42 15/16 TDA7429L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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