HCF4099B 8 BIT ADDRESSABLE LATCH ■ ■ ■ ■ ■ ■ ■ ■ SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT STORAGE REGISTER CAPABILITY MASTER CLEAR CAN FUNCTION AS DEMULTIPLEXER QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4099B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4099B, an 8-bit addressable latch, is a serial-input, parallel output storage register that can perform a variety of functions. Data is input to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4099BEY HCF4099BM1 HCF4099M013TR WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer ; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level. PIN CONNECTION October 2002 1/14 HCF4099B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 5, 6, 7 9, 10, 11, 12, 13, 14, 15, 1 3 2 A0 to A2 Address Inputs Q0 to Q7 Latch Outputs Data Inputs Reset Input 8 DATA RESET WRITE DISABLE VSS 16 VDD 4 NAME AND FUNCTION Write Disable Input Negative Supply Voltage Positive Supply Voltage FUNCTIONAL DIAGRAM TRUTH TABLE SELECT INPUTS LATCH ADDRESSED C B A L L L L H H H H L L H H L L H H L H L H L H L H INPUTS WRITE DISABLE RESET OUTPUTS OF ADDRESSED LATCH L L H H L H L H D Qi0 D L Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 EACH OTHER OUTPUT FUNCTION Qi0 Qi0 L L ADDRESSABLE LATCH MEMORY DEMULTIPLEXER CLEAR ALL BITS TO "0" D: The level at the data input ; Qi0 The level before the indicated steady state input conditions were established, (i=0, 1,...7) 2/14 HCF4099B LOGIC DIAGRAM TIMING CHART 3/14 HCF4099B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/14 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4099B DC SPECIFICATIONS Test Conditions Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value IO VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 any input any input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 µA V 3.5 7 11 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 5/14 HCF4099B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time (Data to Output) tPLH tPHL Propagation Delay Time (Write Disable to Output) tPLH tPHL Propagation Delay Time (Address to Output) tPHL Propagation Delay Time (Reset to Output) tTHL tTLH Transition Time (any output) tW tW tW tsetup thold Pulse WIdth (Data) Pulse WIdth (Address) Pulse WIdth (Reset) Setup Time (Data to Write Disable) Hold Time (Data to Write Disable) VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. 6/14 See Timing Chart Value (*) Min. Typ. Max. 400 150 100 400 160 120 450 200 150 350 160 130 200 100 80 200 100 80 400 200 125 150 75 50 100 50 35 150 75 50 200 75 50 200 80 60 225 100 75 175 80 65 100 50 40 100 50 40 200 100 65 75 40 25 50 25 20 75 40 25 (1) (2) (9) (3) (4) (8) (5) (6) (7) Unit ns ns ns ns ns ns ns ns ns ns HCF4099B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/14 HCF4099B WAVEFORM 2 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : MINIMUM PULSE WIDTH, SETUP AND HOLD TIME (f=1MHz; 50% duty cycle) 8/14 HCF4099B WAVEFORM 4 : MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) WAVEFORM 5 : SETUP AND HOLD TIME (f=1MHz; 50% duty cycle) 9/14 HCF4099B WAVEFORM 6 : INPUT WAVEFORMS (f=1MHz; 50% duty cycle) TIPICAL APPLICATIONS 10/14 HCF4099B TIPICAL APPLICATIONS 11/14 HCF4099B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 12/14 HCF4099B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 13/14 HCF4099B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 14/14