L6997S STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONS 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 Figure 1. Package Features FROM 3V TO 5.5V VCC RANGE MINIMUM OUTPUT VOLTAGE AS LOW AS 0.6V 1V TO 35V INPUT VOLTAGE RANGE CONSTANT ON TIME TOPOLOGY VERY FAST LOAD TRANSIENTS 0.6V, ±1% VREF SELECTABLE SINKING MODE LOSSLESS CURRENT LIMIT, AVAILABLE ALSO IN SINKING MODE REMOTE SENSING OVP,UVP LATCHED PROTECTIONS 600µA TYP QUIESCENT CURRENT POWER GOOD AND OVP SIGNALS PULSE SKIPPING AT LIGTH LOADS 94% EFFICIENCY FROM 3.3V TO 2.5V TSSOP20 Table 1. Order Codes 3 Applications NETWORKING ■ DC/DC MODULES ■ DISTRIBUTED POWER ■ MOBILE APPLICATIONS ■ CHIP SET, CPU, DSP AND MEMORIES SUPPLY Figure 2. Minimum Component Count Application ■ Part Number Package L6997S TSSOP20 L6997STR Tape & Reel Description The device is a high efficient solution for networking dc/dc modules and mobile applications compatible with 3.3V bus and 5V bus. It's able to regulate an output voltage as low as 0.6V. The constant on time topology assures fast load transient response. The embedded voltage feed-forward provides nearly constant switching frequency operation in spite of a wide input voltage range. An integrator can be introduced in the control loop to reduce the static output voltage error. The remote sensing improves the static and dynamic regulation, recovering the wires voltage drop. Pulse skipping technique reduces power consumption at light loads. Drivers current capability allows output currents in excess of 20A. 3.3V Rin2 Rin1 VCC VDR Cin OSC Dboot BOOT HGATE HS Cboot L 0.6V PHASE PGOOD Ro1 OVP LGATE ILIM L6997SPGND LS DS Cout Ro2 GND GNDSENSE Rilim SS Css VSENSE INT VFB SHDN Vref Cvref June 2004 REV. 1 1/30 L6997S Table 2. Absolute Maximum Ratings Symbol Parameter VCC VDR VPHASE BOOT, HGATE and PHASE PINS Value Unit VCC to GND -0.3 to 6 V VDR to GND -0.3 to 6 V HGATE and BOOT, to PHASE -0.3 to 6 V HGATE and BOOT, to PGND -0.3 to 42 V PHASE -0.3-to 36 V LGATE to PGND -0.3 to VDR+0.3 V ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF, INT, GNDSENSE to GND -0.3 to VCC+0.3 V ±750 V Maximum Withstanding Voltage Range Test Condition:CDF-AEC-Q100-002 “Human Body Model” Accepatance Criteria: “Normal Performance” OTHER PINS Ptot Power dissipation at Tamb = 25°C Tstg Storage temperature range ±2000 V 1 W -40 to 150 °C Value Unit 125 °C/W -40 to 125 °C Table 3. Thermal Data Symbol Rth j-amb Tj Parameter Thermal Resistance Junction to Ambient Junction operating temperature range Figure 3. Pin Connection (Top View) NOSKIP 1 20 BOOT GNDSENSE 2 19 HGATE INT 3 18 PHASE VSENSE 4 17 VDR VCC 5 16 LGATE GND 6 15 PGND VREF 7 14 PGOOD VFB 8 13 OVP OSC 9 12 SHDN 11 ILIM SS 10 TSSOP20 Table 4. Pin Function N° Name 1 NOSKIP 2 GNDSENSE 3 INT 4 VSENSE 2/30 Description Connect to VCC to force continuous conduction mode and sink mode. Remote ground sensing pin Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the integrator in the control loop. If the integrator is not used, short this pin to VREF. This pin must be connected to the remote output voltage to detect overvoltage and undervoltage conditions and to provide integrator feedback input. L6997S Table 4. Pin Function (continued) N° Name 5 VCC IC Supply Voltage. Description 6 GND Signal ground 7 VREF 0.6V voltage reference. Connect a ceramic capacitor (max. 10nF) between this pin and ground. This pin is capable to source or sink up to 250uA 8 VFB PWM comparator feedback input. Short this pin to INT pin to enable the integrator function, or to VSENSE to disable the integrator function. 9 OSC Connect this pin to the input voltage through a voltage divider in order to provide the feedforward function don’t leave floating. 10 SS Soft Start pin. A 5µA constant current charges an external capacitor. Itsvalue sets the softstart time don’t leave floating. 11 ILIM 12 SHDN Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left floating. 13 OVP Open drain output. During the over voltage condition it is pulled up by an external resistor. 14 PGOOD An external resistor connected between this pin and GND sets the current limit threshold don’t leave floating.. Open drain output. It is pulled down when the output voltage is not within the specified thresholds. Otherwise is pulled up by external resistor. If not used it can be left floating. 15 PGND Low Side driver ground. 16 LGATE Low Side driver output. 17 VDR Low Side driver supply. 18 PHASE 19 HGATE High side driver output. 20 BOOT Bootstrap capacitor pin. High Side driver is supplied through this pin. Return path of the High Side driver. Table 5. Electrical Characteristics (VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY SECTION Vin Input voltage range Vout=Vref Fsw=110Khz Iout=1A 1 35 V 3 5.5 V Turn-onvoltage 2.86 2.97 V Turn-off voltage 2.75 2.9 V VCC, VDR VCC Hysteresis 90 mV IqVDR Drivers Quiescent Current VFB > VREF 7 20 µA IqVcc Device Quiescent current VFB > VREF 400 600 µA SHUTDOWN SECTION SHDN Device On 1.2 V Device Off ISHVDR Drivers shutdown current SHDN to GND ISHVCC Devices shutdown current SHDN to GND 0.6 V 5 µA 1 15 µA 6 µA 400 500 mV SOFT START SECTION ISS ∆VSS Soft Start current Active Soft start and voltage VSS = 0.4V 4 300 3/30 L6997S Table 5. Electrical Characteristics (continued) (VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 4.6 5 5.4 µA 2 mV CURRENT LIMIT AND ZERO CURRENT COMPARATOR ILIM KILIM Input bias current RILIM = 2KΩ to 200KΩ Zero Crossing Comparator offset Phase-gnd -2 Current limit factor 1.6 1.8 2 µA VREF=VSENSE OSC=125mV 720 800 880 ns VREF=VSENSE OSC=250mV 370 420 470 ns VREF=VSENSE OSC=500mV 200 230 260 ns VREF=VSENSE OSC=1000mV 90 115 140 ns 600 ns ON TIME Ton On time duration OFF TIME TOFFMIN Minimum off time KOSC/TOFFMIN OSC=250mV 0.20 0µA < IREF < 100µA 0.594 0.40 VOLTAGE REFERENCE VREF Voltage Accuracy 0.6 0.606 V +2 mV PWM COMPARATOR Input voltage offset IFB -2 Input Bias Current 20 nA INTEGRATOR Over Voltage Clamp VSENSE = VCC 0.62 0.75 0.88 V Under Voltage Clamp VSENSE = GND 0.45 0.55 0.65 V -4 mV -4 Integrator Input Offset Voltage VSENSE-VREF IVSENSE Input Bias Current 20 nA GATE DRIVERS High side rise time High side fall time Low side rise time Low side fall time VDR=3.3V; C=7nF HGATE - PHASE from 1 to 3V 50 90 ns 50 100 ns VDR=3.3V; C=14nF LGATE from 1 to 3V 50 90 ns 50 90 ns 121 124 % PGOOD UVP/OVP PROTECTIONS OVP UVP VPGOOD 4/30 with respect to VREF 118 67 70 73 % Upper threshold (VSENSE-VREF) VSENSE rising 110 112 116 % Lower threshold (VSENSE-VREF) VSENSE falling 85 88 91 % 0.2 0.4 V Over voltage threshold Under voltage threshold ISink=2mA V IN 5 uA 0.6V VREF OSC SENSEGND Gm + + - VREF soft-start control IC enable power management 1.236V bandgap HS control pwm comparator 1.416 - + + Reference chain VREF 0.05 + positive current limit comparator PHASE VREF VSENSE INT FB ILIM SS NOSKIP OVP R one-shot Ton Ton min one-shot Toff min delay S 1.12 VREF - VSENSE 0.6 VREF 0.925 VREF VSENSE VSENSE 1.075 VREF LS control PHASE S R VCC Q GND zero-cross comparator - + no-skip mode Ton= Kosc V(VSENSE)/V(OSC) - + - + pgood comparators + - undervoltage comparator VSENSE + overvoltage comparator OSC PGOOD VSENSE no-skip mode R S - + - + Q S R one-shot Ton Q level shifter OSC LS driver HS driver 0.05 ILIM negative current limit comparator Ton= Kosc V(VSENSE)/V(OSC) PHASE V(PHASE)<0.2V comp V(LGATE)<0.5V comp LS and HS anti-cross-conduction comparators VCC VSENSE SHDN PGND LGATE VDR PHASE HGATE BOOT Vcc V IN V OUT L6997S Figure 4. Functional & Block Diagram 5/30 L6997S 4 DEVICE DESCRIPTION 4.1 Constant On Time PWM topology Figure 5. Loop block schematic diagram Vin R1 One-shot generator OSC R2 FFSR R Q Vsense HS Vout HGATE S Vref Q LS + - DS LGATE PWM comparator FB R4 R3 The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time duration forced by the one-shot generator. The On Time is directly proportional to VSENSE pin voltage and inverse to OSC pin voltage as in Eq1: V SENSE T ON = K OSC ---------------------- + τ V OSC (1) where KOSC = 180ns and τ is the internal propagation delay time (typ. 40ns). The system imposes in steady state a minimum On Time corresponding to VOSC = 1V. In fact if the VOSC voltage increases above 1V the corresponding Ton will not decrease. Connecting the OSC pin to a voltage partition from VIN to GND, it allows a steady-state switching frequency FSW independent of VIN. It results: V OUT 1 α OSC 1 f SW = --------------- ----------- = --------------- --------------- → α OSC = f SW K OSC α OUT (2) V IN T ON α OUT K OSC where V OSC R2 - = -------------------α OSC = -------------V IN R 2 + R1 (3) R4 V FB α OUT = -------------- = -------------------V OUT R3 + R 4 (4) The above equations allow setting the frequency divider ratio αOSC once output voltage has been set; note that such equations hold only if VOSC<1V. Further the Eq2 shows how the system has a switching frequency ideally independent from the input voltage. The delay introduces a light dependence from VIN. A minimum Off-Time constraint of about 500ns is introduced in order to assure the boot capacitor charge and to 6/30 L6997S limit the switching frequency after a load transient as well as to mask PWM comparator output against noise and spikes. The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit value). The voltage at the OSC pin must range between 50mV and 1V to ensure the system linearity. 4.2 Closing the loop The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin is internally conncted to the comparator negative pin while the positive pin is connected to the reference voltage (0.6V Typ.) as in Figure 5. When the FB goes lower than the reference voltage, the PWM comparator output goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise. After the On-Time (calculated as described in the previous section) the system resets the flip-flop, turns off the high side MOSFET and turns on the low side MOSFET. For more details refers to the Figure 4. The voltage drop along ground and supply metal paths connecting output capacitor to the load is a source of DC error. Further the system regulates the output voltage valley value not the average, as shown in Figure 6. So, the voltage ripple on the output capacitor is a source of DC static error (well as the PCB traces). To compensate the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 7. The internal integrator amplifier with the external capacitor CINT1 introduces a DC pole in the control loop. CINT1 also provides an AC path for output ripple. Figure 6. Valley regulation Vout DC Error Offset <Vout> Vref Time The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance voltage in order to compensate the total static error. A voltage clamp within the device forces anINT pin voltage range (VREF-50mV, VREF+150mV). This is useful to avoid or smooth output voltage overshoot during a load transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peakto-peak amplitude is less than 150mV in steady state. In case the ripple amplitude is larger than 150mV, a capacitor CINT2 can be connected between INT pin and ground to reduce ripple amplitude at INT pin, otherwise the integrator will operate out of its linear range. Choose CINT1 according to the following equation: g INT ⋅ α OUT C INT1 = -----------------------------2 ⋅ π ⋅ Fu (5) where gINT=50 µs is the integrator transconductance, αOUT is the output divider ratio given from Eq4 and FU is the close loop bandwidth. This equation holds if CINT2 is connected between INT pin and ground. CINT2 is given by: 7/30 L6997S C INT2 ∆V OUT ---------------- = -----------------C INT1 ∆V INT (6) Where ∆VOUT is the output ripple and ∆VINT is the required ripple at the INT pin (100mV typ). Figure 7. Integrator loop block diagram Vin R1 One-shot generator PCB TRACES OSC FFSR R Q R2 From Vsense S Vref HS Q LS FB Vout HGATE + - DS LOAD LGATE PWM comparator + INT Vref + Cint2 Vsense Gndsense Integrator amplifier Cint1 Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hysteretic system the frequency can change with some parameters. For example, while in a standard fixed switching frequency topology, the increase of the losses (increasing the output current, for example) generates a variation in the On Time and Off Time, in a fixed On Time topology , the increase of the losses generates only a variation on the Off Time, changing the switching frequency. In the device is implemented the voltage feedforward circuit that allows constant switching frequency during steady-sate operation and withinthe input range variation. Any way there are many factors affecting switching frequency accuracy in steady-state operation. Some of these are internal as dead times, which depends on high side MOSFET driver. Others related to the external components as high side MOSFET gate charge and gate resistance, voltage drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance. During a positive load transient, (the output current increases), the converter switches at its maximum frequency (the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output current decreases), the device stops to switch (high side MOSFET remains off). 4.3 Transition from PWM to PFM/PSK To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM mode essentially for the off phase; the on phase is the same. In PFM after a On cycle the system turns-on the low side MOSFET until the inductor current goes down zero, when the zero-crossing comparator turns off the low side MOSFET. In PWM mode, after On cycle, the system keeps the low side MOSFET on until the next turnon cycle, so the energy stored in the output capacitor will flow through the low side MOSFET to ground. The PFM mode is naturally implemented in an hysteretic controller enabling the zero current comparator by enabling, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when the output voltage goes down to reference value. The device works in discontinuous mode 8/30 L6997S at light load and in continuous mode at high load. The transition from PFM to PWM occurs when load current is around half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the inductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the transient response is. The PFM waveforms may appear more noisy and asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. If the PFM is not compatible with the application it can be disabled connecting to VCC the NOSKIP pin. 4.4 Softstart After the device is turned on the SS pin voltage begins to increase and the system starts to switch. The softstart is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start range for the VSS voltage (where the output current limit increase linearly) is from 0.6V to 1V. In this range an internal current source (5µA Typ) charges the capacitor on the SS pin; the reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5µA (Typ.). When SS voltage is close to 1V the maximum current limit is active. Output protections OVP & UVP are disabled until the SS pin voltage reaches 1V (see figure 8). Once the SS pin voltage reaches the 1V value, the voltage on SS pin doesn't impact the system operation anymore. If the SHDN pin is turned on before the supplies, the power section must be turned on before the logic section. While if the supplies are applied with the SHND pin off, the start up sequence doesn't meter. Figure 8. Soft -Start Diagram Vss 4.1V 1V Soft-start active range 0.6V Time Ilim current 5µA Maximum current limit Time Because the system implements the soft start by controlling the inductor current, the soft start capacitor should be selected based on of the output capacitance, the current limit and the soft start active range (∆VSS). In order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before the soft start voltage reaches the under voltage value (1V). After this UVP and OVP are enable. The time necessary to charge the SS capacitor up to 1V is given by: 1V T SS ( C SS ) = -------- ⋅ C SS Iss (7) In order to calculate the output voltage chargin time it should be considered that the inductor current function can be supposed linear function of the time. ( R ilim /R dson ⋅ K ILIM ⋅ I SS ⋅ t ) I L ( t,C SS ) = -------------------------------------------------------------------------( ∆V SS ⋅ C SS ) (8) 9/30 L6997S so considering zero the output load the output voltage is given by: 2 ( R ilim /R dson ⋅ K ILIM ⋅ I SS ⋅ t ) Q ( t,C SS ) - = ----------------------------------------------------------------------------V out ( t,C SS ) = -----------------------( C out ⋅ ∆V SS ⋅ C SS ⋅ 2 ) C out (9)) indicating with Vout the final value, the output charging time can be estimated as: ( V out ⋅ C out ⋅ ∆V SS ⋅ C SS ⋅ 2 ) 0.5 V out ( C SS ) = ---------------------------------------------------------------------------( R ilim /R dson ⋅ K ILIM ⋅ I SS ) (10) the minimum CSS value is given imposing this condition: Tout =TSS (11) 4.5 Current limit The current limit comparator senses the inductor current through the low side MOSFET RDSON drop and compares this value with the ILIM pin voltage value. While the current is above the current limit value, the control inhibits the high side MOSFET Turn On. To properly set the current limit threshold, it should be noted that this is a valley current limit. The Average current depends on the inductor value, VIN VOUT and switching frequency. The average output current in current limit is given by: I OUT CL ∆I = I max valley + ----- (12) 2 Thus, to set the current threshold, choose RILIM according to the following equation: R ILim I max valley = ----------------- ⋅ K ILIM (13) Rds on In overcurrent conditions the system keeps the current constant until the output voltage meets the undervoltage threshold. The negative valley current limit, for the sink mode, is set automatically at the same value of the positive valley current limit. The average negative current limit differs from the positive average current limit by the ripple current; this difference is due to the valley control technique. The current limit system accuracy is function of the precision of the resistance connected to the ILIM pin and the low side MOSFET RDSON accuracy. Moreover the voltage on ILIM pin must range between 10mV and 1V to ensure the system linearity. Figure 9. Current limit schematic To inductor LS RILIM PHASE PGN D Current Comparator 5µA Positive and negative current limit 10/30 To logic L6997S 4.6 Protection and fault The load protection is realized by using the VSENSE pin. Both OVP and UVP are latched, and the fault condition is indicated by the PGOOD and the OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low side MOSFET and, high side MOSFET are turned off and PGOOD goes low. In case the system detects an overvoltage the OVP pin goes high. To recover the functionality the device must be shut down and restarted the SHDN pin, or by removing the supply, and restarting the devicewith the correct sequence. 4.7 Drivers The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching transitions. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The drivers have the adaptive anti-cross-conduction protection, which prevents from having bothhigh side and low side MOSFET on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET is turned off the voltage on the PHASE pin begins to fall; the low side MOSFET is turned on only when the voltage on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage reaches 500mV. This is important since the driver can work properly with a large range of external power MOSFETS. The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the MOSFET gate charge the switching frequency and the driver voltage. So the power dissipation of the device is function of the external power MOSFET gate charge and switching frequency. P driver = V cc ⋅ Q gTOT ⋅ F SW (14) The maximum gate charge values for the low side and high side are given by: f SW0 Q MAXHS = ------------- ⋅ 75nC (15) f SW f SW0 Q MAXLS = ------------- ⋅ 125nC (16) f SW Where fSW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG can be higher. For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation; in this case the maximum value is QMAXLS = 125nC. The low side driver has been designed to have a low resistance pull-down transistor, approximately 0.5 ohms. This prevents undesired LS MOSFET Turn On during the fast rise-time of the pin PHASE, due to the Miller effect. When the 3.3V bus is used to supply the drivers, ULTRA LOGIC LEVEL MOSFETs should be selected , to be sure that the MOSFETs work in properly way. 11/30 L6997S 5 APPLICATION INFORMATION 5.1 5A Demo board description The demo board shows the device operation in this condition: VIN from 3.3V to 5V, IOUT=5A VOUT=1.25V. The evaluation board let use the system with 2 different voltages (VCC the supply for the IC and VIN the power input for the conversion) so replacing the input capacitors the power input voltage could be also 35V. When instead the input voltage (VIN) is equal to the VCC it should be better joining them with a 10Ω resistor in order to filter the device input voltage. On the topside demo there are two different jumpers: one jumper, near the OVP and POWER GOOD test points, is used to shut down the device; when the jumper is present the device is in SHUTDOWN mode, to run the device remove the jumper. The other jumper, near the VREF test point, is used to set the PFM/ PSK mode. When the jumper is present, at light load, the system will go in PFM mode; if there is not the jumper, at light load, the system will remain in PWM mode. In the demo bottom side there are two others different jumpers. They are used to set or remove the INTEGRATOR configuration. When the jumpers named with INT label are closed AND the jumpers named with the NOINT label are open the integrator configuration is set. Sometimes the integrator configuration needs a low frequency filter the to reduce the noise interaction. In this case instead close the INT jumpers put there a resistor and after a capacitor to ground (as in the schematic diagram); the pole value is around 500Khz but it should be higher enough than the switching frequency (ten times). On the opposite when the jumpers named with the NOINT are closed and the jumpers named with INT are open the NON INTEGRATOR configuration is selected. Refer to the Table 1 and 2 for the jumpers connection. Figure 10. Demoboard Schematic Diagram Vcc R7 C8 J1 R6 C7,C13 VIin C11 C10 VDR VCC R4 GNDin OSC BOOT D1 C4 HGATE R5 Q1 L1 VOUT R10 PHASE TP1 R3 PGOOD OVP LGATE ILIM L6997S PGND Q2 D2 C14,C15 R1 TP2 R2 GND R8 C12 GNDOUT NOSKIP VSENSE GNDSENSE SS NOINT C9 C3 INT INT R9 VFB SHDN C1 VREF C6 NOINT SD TP3 C5 12/30 INT C2 NS Cn Rn L6997S 5.2 Jumper Connection Table 6. Jumper connection with integrator Component Connection C1 Mounted C2 Mounted * INT Close NOINT Open * This component is not necessary, depends from the output ESR capacitor. See the integrator section. Table 7. Jumper connection without integrator Component Connection C1 Not mounted C2 Not Mounted INT Open NOINT Close 5.3 DEMOBOARD LAYOUT Real dimensions: 4,7 cm X 2,7 cm (1.85 inch X 1. 063 inch) Figure 11. Top side components placement Figure 13. Top side layout Figure 12. Bottom side Jumpers distribution Figure 14. Bottom side layout 13/30 L6997S Table 8. PCB Layout guidelines Goal Suggestion To minimize radiation and magnetic coupling with the adjacent circuitry. 1) Minimize switching current loop areas. (For example placing CIN, High Side and Low side MOSFETS, Shottky diode as close as possible). 2) Place controller placed as close as possible to the power MOSFETs. 3) Group the gate drive components (Boot cap and diode) near the IC. To maximize the efficiency. Keep power traces and load connections short and wide. To ensure high accuracy in the current sense system. Make Kelvin connection for Phase pin and PGND pin and keep them as close as possible to the Low Side MOSFETS. To reduce the noise effect on the IC. 1) Put the feedback component (like output divider, integrator network, etc) as close as possible to the IC. 2) Keep the feedback traces parallel and as close as possible. Moreover they must be routed as far as possible from the switching current loops. 3) Make the controller ground connection like the figure 8. Table 9. Component list The component list is shared in two sections: the first for the general-purpose component, the second for power section: Part name Value Dimension Notes GENERAL-PURPOSE SECTION RESISTOR R1, R5, R9, R10 33kΩ 0603 Pull-up resistor R2 1kΩ 0603 Output resistor divider (To set output voltage) R3 1.1kΩ 0603 R4 0603 R6 470kΩ R7 0Ω R8 Input resistor divider (To set switching frequency) 0603 0603 0603 Current limit resistor CAPACITOR C1 330pF 0603 First integrator capacitor C2 N.M. 0603 Second integrator capacitor C3 1nF 0603 C4 100nF 0603 C5 1µF Tantalum C6 10nF 0603 C9 10nF 0603 C10 100nF 0603 C11 100nF 0603 C8, C12 47pF 0603 Softstart capacitor DIODE D1 BAR18 POWER SECTION INPUT CAPACITORS C7, C13 14/30 47µF ECJ4XF0J476Z PANASONIC L6997S Table 9. Component list (continued) The component list is shared in two sections: the first for the general-purpose component, the second for power section: Part name Value Dimension 220µF 2R5TPE220M POSCAP 2.7 µH DO3316P-272HC COILCRAFT Notes OUTPUT CAPACITORS C14, C15 INDUCTOR L1 POWER MOS Q1,Q2 STS5DNF20V STMicroelectronics Double mosfet in sigle package DIODE D2 STPS340U STMicroelectronics 3 Notes: 1. N.M.=Not Mounted 2. The demoboard with this component list is set to give: VOUT = 1.25V, FSW = 270kHz with an input voltage around VIN = VCC = 3.3V-5V and with the integrator feature. 3. The diode efficiency impact is very low; it is not a necessary component. 4. All capacitors are intended ceramic type otherwise specified. 5.4 EFFICIENCY CURVES Source mode VIN = 3.3V VOUT = 1.25V FSW = 270kHz Figure 15. Efficiency vs output current Eff [%] 100,0 90,0 80,0 70,0 60,0 50,0 40,0 30,0 20,0 10,0 0,0 0,0 1,0 2,0 PFM mode 3,0 Current [A] 4,0 5,0 6,0 PWM mode 15/30 L6997S 6 STEP BY STEP DESIGN Application conditions: VIN = 3.3V, ±10% VOUT = 1.25V IOUT = 5A FSW = 270kHz 6.1 Input capacitor. A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC component of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor: 2 Vin ⋅ ( Vin – Vout ) P CIN = ESR CIN ⋅ Iout ⋅ -----------------------------------------------2 Vin (17) The RMS current, which the capacitor must provide, is given by: Icin rms = 2 2 δ Iout δ ( 1 – δ ) + ------ ( ∆I L ) (18) 12 Where δ is the duty cycle of the application Neglecting the last term, the equation reduces to: Icin rms = Iout δ ( 1 – δ ) (19) which maximum value corresponds to to δ = 1/2 and is equal Iout/2 Therefore, in worst case, the input capacitors should be selected with a RMS ripple current rating as high as half the respective maximum output current. Electrolytic capacitors are the most used because theyare the cheapest ones and are available with a wide range of RMS current ratings. The only drawback is that, for a givenripple current rating, they are physically larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR and small size. The only problem is that they occasionally can burn if subjected to very high current during the charge. So, it is better avoid this type of capacitors for the input filter of the device. In fact, they can be subjected to high surge current when connected to the power supply. If available for the requested capacitance value and voltage rating, the ceramic capacitors have usually a higher RMS current rating for a given physical dimension (due to the very low ESR). The drawback is the quite high cost. Possible solutions: 10µF C34Y5U1E106ZTE12 TOKIN 22µF JMK325BJ226MM TAIYO-YUDEN 47µF ECJ4XF0J476Z PANASONIC 33µF C3225X5R0J476M TDK With our parameter from the equation 3 it is found: Icinrms = 2.42A 6.2 Inductor To define the inductor, it is necessary to determine firstly the inductance value. Its minimum value is given by: V o ⋅ ( Vin max – V o ) Lmin ≥ --------------------------------------------------------------F SW ⋅ I out ⋅ RF ⋅ Vin max where RF = ∆I/IOUT (basically it is approximately 30%). 16/30 (20) L6997S With our parameters: Lmin ≥ 2µH The saturation current must be higher then 5A 6.3 Output capacitor and ripple voltage The output capacitor is selected based on both static and dynamic output voltage accuracy. The static output voltage accuracy depends mostly on the ERS of the output capacitor, while the dynamic accuracy usually depends both on the ESR and capacitance value. If the static precision is ±1% for the 1.25V output voltage, the output ripple is ±12.5mV. To determine the ESR value from the output precision is necessary to calculate the ripple current: Vin – Vo Vo ∆I = ----------------------- ⋅ --------- ⋅ T sw (21) L Vin Where FSW = 270kHz. From the Eq. above the ripple current is around 1.25A. So the ESR is given by: ∆V ripple 25mV ESR = --------------------- = ---------------- = 20mΩ (22) ∆I 1.25 ----2 The dynamic specifications are sometimes more relaxed than the static requirements, Anyway a minimum output capacitance must be ensured to avoid output voltage variation due to the charge and discharge of Cout during load transients. To allow the device control loop to work properly, the zero introduced by the output capacitor ESR (τ = ESR · Cout) must be at least ten times smaller than switching frequency. Low ESR tantalum capacitors, which ESR zero is close to ten kHz, are suitable for output filtering. Output capacitor value COUT and its ESR, ESRCOUT, should be large enough and small enough, respectively, to keep output voltage within the accuracy range during a load transient, and to give the device a minimum signal to noise ratio. The current ripple flows through the output capacitors, so the should be calculated also to sustain this ripple: the RMS current value is given by Eq. 18. 1 Icout rms = ----------- ∆I L (23) 2 3 But this is usually a negligible constrain. Possible solutions: 330µF EEFUE0D331R PANASONIC 220µF 2R5TPE220M POSCAP Multilayer capacitors can not be used because their very low ESR. 6.4 MOSFET’s and Schottky Diodes A 3.3V bus powers the gate drivers of the device, the use ultra low level MOSFET is highly recommended, especially for high current applications. The MOSFET breakdown voltage VBRDSS must be greater than VINMAX with a certain margin. The RDSON can be selected once the allowable power dissipation has been established. By selecting identical 17/30 L6997S Power MOSFET for us and ls, the total power they dissipate does not depend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required RDSON (@ 25 °C) can be derived from: P ON - (24) RDS ON = -----------------------------------------------2 Iout ⋅ ( 1 + α ⋅ ∆T ) α is the temperature coefficient of RDSON (typically, α = 510-3 °C-1 for these low-voltage classes) and T the admitted temperature rise. It is worth noticing, however, that generally the lower RDSON, the higher is the gate charge QG, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge QG moves from the input source to ground, resulting in an equivalent drive current: Iq = Qg ⋅ FSW (25) A SCHOTTKY diode can be added to increase the system efficiency at high switching frequency (where the dead times could be an important part of total switching period). This optional diode must be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM greater than VINMAX. The current size of the diode must be selected in order to keep it in safe operating conditions. In order to use less space than possible, a double MOSFET in a single package is chosen: STS5DNF20V 6.5 Output voltage setting The first step is choosing the output divider to set the output voltage. To select this value there isn't a criteria, but a low divider network value (around 100Ω) decries the efficiency at low current; instead a high value divider network (100KΩ) increase the noise effects. A network divider values from 1KΩ to 10KΩ is right. We chose: R3 = 1KΩ R2 = 1.1KΩ The device output voltage is adjustable by connecting a voltage divider from output to VSENSE pin. Minimum output voltage is VOUT=VREF=0.6V. Once output divider and frequency divider have been designed as to obtain the required output voltage and switching frequency, the following equation gives the smallest input voltage, which allows L6997S to regulate (which corresponds to TOFF=TOFFMIN): α OSC 1 δ < 1 – --------------- ⋅ ---------------------------------------------α OUT K OSC -------------------------- MAX T OFF,MIN (26) 6.6 Voltage Feedforward From the equations 1,2 and 3, choosing the switching frequency of 270kHz the resistor divider can be selected. For example: R3 = 470KΩ R4 = 8.5KΩ 6.7 Current limit resistor From the equation 8 the valley current limit can be set considering the RDSON STS5DNF20V and ICIR = 5A: R8 = 120KΩ 6.8 Integrator capacitor Let’s assume FU = 15kHz, VOUT = 1.25V. Since VREF = 0.6V, from equation 2, of the device description, it follows αOUT = 0.348 and, from equation 5 it follows C = 250pF. The output ripple is around 22mV, so the system doesn't need the second integrator capacitor. 18/30 L6997S 6.9 Soft start capacitor Considering the soft start equations (Eq. 11) at page 10, it can be found: CSS = 150pF The equations are valid without load. When an active load is present the equations result more complex; further some active loads have unexpected effect, as higher current than the expected one during the soft start, can change the start up time. In this case the capacitor value can be selected on the application; anyway the Eq11 gives an idea about the CSS value. 6.10 Sink mode Figure 16. Efficiency vs output current Eff [%] 100,0 90,0 80,0 70,0 60,0 50,0 40,0 30,0 20,0 10,0 0,0 0,0 1,0 2,0 3,0 4,0 5,0 Current [A] 7 15A DEMO BOARD DESCRIPTION The evaluation board shows the device operation in these conditions: VIN = 3.3V VOUT = 1.8V IOUT = 15A, FSW = 200KHz without the integrator feature. The evaluation board has two different input voltages: VCC [from 3V to 5.5V] used to supply the device and the VIN [up to 35V] for the power conversion. In this way, changing the power components configuration (CIN, COUT, MOSFETs, L) it is possible evaluate the device performance in different conditions. It is also possible to mount a linear regulator on board used to generate the VCC. On the top side are also present two switches and four jumpers. The two switches have different goals: the one nearest to the VCC is used to turn on/off the device when the VCC and VIN are both present; the other one, near to R11 is used to turn on/off the PFM feature. The device can be turned on also with the power supply, but a correct start up sequence is mandatory. VIN has to be raised first and then the VCC can be applied too. If the correct sequence is not respected the device will not start up. The jumpers are used to set the integrator feature and to use the remote sensing; for more information refers to the Jumpers table. Sometimes when using the integrator configuration a low frequency filter is required in order to reduce the noise interaction. The pole value should be at least five times higher than the switching frequency. The low pass filter should be inserted in this way: the resistor, in the place of the INT jumper position and the capacitor between the resistor and ground (refers to the schematic). 19/30 L6997S Figure 17. L6997S Schematic diagram VCC R5 Vin C2 C22 R3 C3 D1 OSC SS C5 R4 C13, C14, C15, C16, C17, C18 VCC VDR BOOT C20 Q1, Q2, Q3 HGATE C21 R8 C19 L R11 R7 VOUT PHASE R12 R6 L6997S L6997 SHDN Q4, Q5, Q6 LGATE NOSKIP C7 C8 C9 C10, C11 C12 D2 R9 C23 OVP SW1 R10 PGOOD PGND GND TP2 TP1 R13 VSENSE GNDSENSE C24 C4 NOINT INT INT FB NOINT C7 INT VREF RN TP3 C6 C25 7.1 UMPERS CONNECTION Table 10. Jumper connection with integrator Component Connection C4 Mounted C7 Mounted* INT Close NOINT Open *This component is not necessary, depends from the output ESR capacitor. See the integrator section. Table 11. Jumper connection without integrator Component 20/30 Connection C4 Not mounted C7 Not Mounted INT Open NOINT Close CN L6997S 7.2 DEMO BOARD LAYOUT Real dimensions: 5.7cm x 7.7cm (2.28inch x 3. 08inch) Figure 18. PCB layout: bottom side Figure 20. Internal ground plane Figure 19. PCB Layout: Top side Figure 21. Power & signal plane Table 12. PCB Layout guidelines Goal Suggestion To minimize radiation and magnetic coupling with the adjacent circuitry. 1) Minimize switching current loop areas. (For example placing CIN, High Side and Low side MOSFETS, Shottky diode as close as possible). 2) Place controller placed as close as possible to the power MOSFETs. 3) Group the gate drive components (Boot cap and diode) near the IC. To maximize the efficiency. Keep power traces and load connections short and wide. To ensure high accuracy in the current sense system. Make Kelvin connection for Phase pin and PGND pin and keep them as close as possible to the Low Side MOSFETS. To reduce the noise effect on the IC. 1) Put the feedback component (like output divider, integrator network, etc) as close as possible to the IC. 2) Keep the feedback traces parallel and as close as possible. Moreover they must be routed as far as possible from the switching current loops. 3) Make the controller ground connection like the figure 8. 21/30 L6997S Table 13. Component list The component list is shared in two sections: the first for the general-purpose component, the second for power section: Part name RESISTOR R1 R2 R3 R4 R5 R6, R7, R11, R12 R8 R9 R10 R13 CAPACITOR C1 C2 C3 C4 C5 C6 C7 C19 C20 C21 C22 C23 C24 C25 DIODES D1 Value Dimension GENERAL-PURPOSE SECTION N.M. N.M. 560kΩ 5.6kΩ 47Ω 33kΩ 62kΩ 2.7kΩ 1.3kΩ 220Ω 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 220nF 47µF 220nF 150pF 47pF 10nF N.M. 220nF 220nF 47pF 220nF 0805 KEMET-16V 0805 0603 0603 0603 0603 0805 0603 0603 0805 0603 0603 Tantalum 1nF 1µF BAT54 Notes Output resistor divider for the linear regulator. Input resistor divider (To set switching frequency) Current limit resistor (To set current limit) Output resistor divider (To set output voltage) First integrator capacitor Second integrator capacitor Softstart capacitor N.M. 25V POWER SECTION OUTPUT CAPACITORS C11-C12 2X680µF INPUT CAPACITORS C13, C14, C16, C17, 100µF C15 C18 47µF INDUCTOR L1 1.8µH POWER MOS Q1,Q2 SI4442DY Q5,Q6 SI4442DY INTEGRATED CIRCUIT U1 L6997S 22/30 T510x687(1)004AS KEMET Output capacitor C8, C9, C10 N.M. ECJ5YF0J1072 PANASONIC ECJ5YF1A4767 PANASONIC Input capacitor ETQF6F1R8BFA PANASONIC VISHAY Siliconix VISHAY Siliconix Q3 N.M. Q4 N.M. L6997S 7.3 EFFICIENCY CURVES Figure 22. Efficiency vs output Current 100 Efficiency (%) 95 Vout=2.5V Vout=1.8V 90 Vout=1.5V 85 Vout=1.2V Vcc=Vin=3.3V Fsw=200KHz 80 Vout=0.9V 75 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Output Current (A) Table 14. Efficiency Curves For Different Applications (VIN up to 25V) Part name Value Dimension Notes GENERAL-PURPOSE SECTION RESISTOR R1 100Ω 0603 R2 300Ω 0603 Output resistor divider for the linear regulator. R3 560kΩ 0603 R4 10kΩ 0603 R5 47Ω 0603 R6, R7, R11, R12 33kΩ 0603 R8 47kΩ 0603 Current limit resistor (To set current limit) R9 2,7kΩ 0603 Output resistor divider (To set output voltage) R10 1kΩ 0603 R13 220Ω 0603 C1 220 nF 0805 C2 47µF KEMET-16V C3 220nF 0805 C4 150pF 0603 C5 47pF 0603 C6 10nF 0603 C7 330pF 0603 Input resistor divider (To set switching frequency) CAPACITOR C19 220nF 0805 C20 10nF 0603 C21 47pF 0603 C22 220nF 0805 C23 0603 First integrator capacitor Second integrator capacitor Softstart capacitor N.M. 23/30 L6997S Table 14. Efficiency Curves For Different Applications (VIN up to 25V) (continued) Part name Value Dimension C24 1nF 0603 C25 1µF Tantalum Notes DIODES D1 BAT54 25V POWER SECTION OUTPUT CAPACITORS C11-C12 2X100µF B45197-A3107K409 EPCOS Output capacitor C8, C9, C10 N.M. 10µF C34Y5U1E106Z TOKIN Input capacitor 10µF C3225Y5V1E106Z TDK 10µF ECJ4XF1E106Z PANASONIC 10µF TMK325F106ZH TAIYO YUDEN 3 µH T50-52 Core, 7T AWG15 INPUT CAPACITORS C13, C14, C16, C17, C15 C18 INDUCTOR L1 POWER MOS Q1,Q2 STS11NF3LL STMicroelectronics Q3 N.M. Q5,Q6 STS11NH3LL STMicroelectronics Q4 N.M. STPS2L25U STMicroelectronics 25V DIODES D2 INTEGRATED CIRCUIT U1 L6997S NOTE: For the 25V to 12V conversion the inductor used is: 77120A core 7T. 7.4 EFFICIENCY CURVES Figure 23. Efficiency vs output Current Figure 24. Efficiency vs output Current 100 100 Vo = 5V 95 Vo = 3.3V 95 85 2.5V 85 1.8V 80 1.5V 80 1.2V 75 0.9V Vin = Vcc = 5V Fsw = 200KHz 70 Efficiency (%) Efficiency (%) 90 90 3.3V 2.5V 1.8V 1.5V 1.2V 0.9V 75 70 65 Vin = 12V Vcc = 5V Fsw = 200KHz 60 55 65 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Output Current (A) 50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Output Current (A) 24/30 L6997S Figure 25. Efficiency Vs Output Current Figure 26. Efficiency Vs Output Current 100 100 V OUT = 12V 95 90 VOUT = 5V 90 80 70 85 V OUT = 3.3V 60 Eff [%] Eff [%] 80 75 50 40 70 30 65 60 VIN = 25V VCC = 5V 20 55 FSW = 200KHz 10 VIN = 33V VOUT = 12V 0 50 0 1 2 3 4 5 6 7 8 9 10 Output Current [A] 11 12 13 14 15 0 16 1 2 3 4 5 6 7 8 9 10 Output Current [A] 11 12 13 14 15 16 7.5 DDR MEMORY AND TERMINATION SUPPLY Double data rate (DDR) memories require a particular Power Management Architecture. This is due to fact that the trace between the driving chipset and the memory input must be terminated with resistors. Since the Chipset driving the Memory has a push pull output buffer, the Termination voltage must be capable of sourcing and sinking current. Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the memory is a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory Supply is 2.5V and the Termination voltage is 1.25Vwhile for the DDRII the Memory Supply is 1.8V and the Termination voltage is 0.9V. Figure 27 shows a complete DDRII Memory and Termination Supply realized by using 2 x L6997S. The 1.8V section is powering the memory, while the 0.9V section is providing the termination voltage. Figure 27. Application Idea: DDRII Memory Supply VCC VIN OSC VCC MEMORY SUPPLY VCCDR SS BOOT STS11NF3LL HGATE ILIM U1 PHASE L6997S L6997 2R LGATE STS11NF3LL Vddq 1.8V@15A TERMINATION NETWORK R PGND NOSKIP BUS VSENSE INT VREF GNDSENSE SHDN PGOOD OVP GND VCC OSC SS VCC VREF FB CHIPSET VCCDR BOOT HGATE ILIM STS8DNF3LL U2 PHASE L6997S L6997 R Vtt 0.9V@-+ 5A LGATE 2R NOSKIP PGND FB VSENSE INT VREF GNDSENSE SHDN PGOOD OVP GND + 25/30 L6997S The current required by the Memory and Termination supply, depends on the memory type and size. The figures 28 and 29 show the efficiency for the termination section of the application shown in fig. 27. 8 Typical Operating Characteristics Figure 30. Load transient response from 0A to 5A.. Figure 28. Eff. vs. Output Current Source Mode 100 Efficiency (%) 95 90 85 Vin=1.8V 80 Vout = 0.9V Vcc = 5V Fsw = 200KHz 75 Vin = 12V 70 0 1 2 3 4 5 Output Current (A) 6 7 Ch1-> Inductor current Ch2-> Phase Node Ch3-> Output voltage Figure 29. Eff. vs Output Current sink mode Figure 31. Normal functionality in SINK mode.. 100 Efficiency (%) 95 90 85 Vin = 1.8V 80 Vout=0.9V Vcc=5V Fsw=200KHz 75 70 65 Vin=12V Vin = 12V 60 0 1 2 3 4 5 6 7 Output current (A) Ch1-> Inductor current Ch2-> Phase Node Ch3-> Output voltage 26/30 L6997S Figure 32. Normal functionality in PWM mode. Ch1-> Inductor current Ch2-> Phase Node Ch3-> Output voltage Figure 33. Normal functionality in PFM mode. Ch1-> Inductor current Ch2-> Phase Node Ch3-> Output voltage Figure 34. Start up waveform with 0A load. Ch1-> Inductor current Ch2-> Soft start Voltage Ch3-> Output voltage Figure 35. Start up waveform with 5A load.. Ch1-> Inductor current Ch2-> Soft start Voltage Ch3-> Output voltage 27/30 L6997S Figure 36. TSSOP20 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.20 A1 0.050 A2 0.800 b MAX. 0.047 0.150 0.002 1.050 0.031 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 D (1) 6.400 6.500 6.600 0.252 0.256 0.260 E 6.200 6.400 6.600 0.244 0.252 0.260 E1 (1) 4.300 4.400 4.500 0.170 0.173 0.177 e L L1 k aaa 1.000 0.650 0.450 0.600 OUTLINE AND MECHANICAL DATA 0.006 0.039 0.041 0.026 0.750 0.018 1.000 0.024 0.030 0.039 0˚ (min.) 8˚ (max.) 0.100 0.004 Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. TSSOP20 Thin Shrink Small Outline Package 0087225 (Jedec MO-153-AC) 28/30 L6997S Table 15. Revision History Date Revision June 2004 1 Description of Changes First Issue. 29/30 L6997S Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 30/30