STMICROELECTRONICS L9380

L9380
TRIPLE HIGH-SIDE MOSFET DRIVER
OVERVOLTAGE CHARGE PUMP SHUT OFF
FOR VVS > 25V
REVERSE BATTERY PROTECTION (REFERRING TO THE APPLICATION CIRCUIT DIAGRAM)
PROGRAMMABLE OVERLOAD PROTECTION FUNCTION FOR CHANNEL 1 AND 2
OPEN GROUND PROTECTION FUNCTION
FOR CHANNEL 1 AND 2
CONSTANT GATE CHARGE/DISCHARGE
CURRENT
SO20
DESCRIPTION
The L9380 device is a controller for three external
N-channel power MOS transistors in "High-Side
Switch" configuration. It is intended for relays replacement in automotive electric control units.
ORDERING NUMBER: L9380
PIN CONNECTION (Top view)
T1
1
20
CP
VS
2
19
D1
N.C.
3
18
N.C.
T2
4
17
D2
PR
5
16
G1
IN3
6
15
S1
IN2
7
14
S2
IN1
8
13
N.C.
EN
9
12
G2
10
11
G3
GND
D98AT391
April 1998
1/12
L9380
BLOCK DIAGRAM
VS
CHARGE PUMP
CP
OVERVOLTAGE
GND
VSI
T1
≥1
VSI
D1
IPR
+
S1
CP
IN1
ENN
≥1
G1
DRIVER 1
VSI
T2
≥1
VSI
D2
IPR
+
S2
CP
IN2
ENN
≥1
G2
DRIVER 2
VSI
CP
ENN
IN3
≥1
G3
DRIVER 3
EN
ENN
VS
REG.
REFERENCE
VSI
2V
PR
IPR
D98AT390
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
VS
∆VS/dt
VIN,EN
VT
VD, G, S
VD, G, S
ID, G, S
Tj
Tstg
Value
Unit
DC Supply Voltage
Supply Voltage pulse (t ≤ 400ms)
Parameter
-0.3 to +27
45
V
V
Supply Voltage slope
Input / Enable Voltage
Timer Voltage
Drain, gate, source voltage
Drain, gate, source voltage pulse (t ≤ 400ms)
Drain, gate, source current (t ≤ 2ms)
-10 to +10
-0.3 to +7
-0.3 to 27
-15 to +27
45
0 to +4
V/µs
V
V
V
V
mA
Operating Junction Temperature
Storage Temperature
-40 to 150
-65 to 150
°C
°C
Note: ESD for all pins, except the timer pins, are according to MIL 883C, tested at 2KV, corresponds to a maximum energy dissipation of 0.2mJ.
The timer pins are tested with 800V
2/12
L9380
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to Ambient
Value
100
Unit
°C/W
LIFETIME
Symbol
tB
tb
Parameter
Useful life time
Operating life time
Condition
VS = 0V
VS = 7 to 18.5V
Value
20
5000
Unit
years
hours
PIN FUNCTIONS
N.
Name
1
T1
Function
2
4
VS
T2
5
PR
Programming resistor for overload detetcion threshold; the resistor from this pin to ground
defines the drain pin current and the charging of the timer capacitor.
6
7
IN3
IN2
Input 3; equal to IN1.
Input 2; equal to IN1.
8
IN1
9
10
11
EN
GND
G3
Input 1; logic signal applied to this pin controls the driver 1; this pin features a current source to
assure defined high status when the pin is open.
Enable logic signal high on this pin enables all channels
Ground
Gate 3 driver output; current source from CP or ground
12
G2
Gate 2 driver output; current source from CP or ground
14
S2
Source 2 sense input; monitors the source voltage.
15
16
17
S1
G1
D2
19
D1
20
CP
3, 13, 18
NC
Source 1 sense input; monitors the source voltage.
Gate 1 driver output; current source from CP or ground
Drain 2 sense input; a programmable input bias current defines the drop across the external
resistor RD1; this drop fixes the overload threshold of the external MOS.
Drain 1 sense input; a programmable input bias current defines the drop across the external
resistor RD1; this drop fixes the overload threshold of the external MOS.
Charge pump capacitor; a alternating current source at this pin charges the connected
capacitor CCP to a voltage 10V higher than VS; the charge stored in this capacitor is thanused
to charge all the three gates of the power MOS transistors.
Not connected
Timer capacitor; the capacitor defines the time for the channel 1 shut down, after overload of
the external MOS transistor has been detected.
Supply Voltage.
Timer capacitor; the capacitor defines the time for the channel 2 shut down, after overload of
the external MOS transistor has been detected.
3/12
L9380
ELECTRICAL CHARACTERISTICS (7V ≤ VS ≤ 18.5V; -40°C ≤ TJ ≤ 150°C, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
2.5
mA
8
17
V
20
200
30
µs
V
SUPPLY
Static Operating Supply Current VS = 14V
IVS
CHARGE PUMP
VCP
Charge Pump Voltage Above VS
tCP
VSCP off
VSCP hys
Charging Time
Overvoltage Shut down
VCP = VS + 8V CCP = 100pF
Overvoltage Shut down
Hysteresis 1)
Charge Pump frequency 1)
fCP
GATE DRIVERS
IGSo
Gate Source Current
Gate Sink Current
IGSi
DRAIN - SOURCE SENSING
VPR
Bias Current Programming
voltage
50
200
1000
mV
100
250
400
KHz
VG = VS
-5
-3
-1
mA
VG ≥ 0.8V
1
3
5
mA
1.8
2
2.2
V
0
5
µA
0.9 IPR
10
1.1 IPR
60
10µA ≤ IPR ≤ 100µA; VD ≥ 4V
ID Leak
Drain pin leakage current
VS = 0V; VD =14V
ID
Drain pin bias current
Source pin input current
Comparator Hysteresis
VS ≥ VD + 1V; VD ≥ 5V
VS ≥ VD + 1V; VD ≥ 7V
ISmax
VHYST
20
µA
mV
TIMER
VTHi
VTLo
IT
Timer threshold high
4
4.4
4.8
V
Timer threshold low
0.3
0.4
0.5
V
Timer Current
IN = 5V; VT = 2V
IN = 0V; VS < VD;
VD ≥ 5V; VT = 2V
0.4 IPR
-0.6 IPR
0.6 IPR
-0.4 IPR
1
7
V
V
500
-5
30
2.5
mV
INPUTS
VLOW
VHIGH
Input Enable low voltage
Input Enable high voltage
-0.3
3
VINhys
IIN
IEN
td
Input Enable Hysteresis(1)
Input source current
Enable sink current
Transfer time IN/ENABLE
50
-30
5
VIN ≤ 3V
VEN ≥ 1V
VS = 14V VG = VS; OPEN GATE
200
µA
µA
µs
NOTE: Not measured guaranteed by design
Function is given for supply voltage down to 5.5V. Function means: The channels are controlled from the
inputs, some other parameters may exceed the limit. In this case the programming voltage and timer
threshold will be lower. This leads to a lower protection threshold and time.
FUNCTIONAL DESCRIPTION
The Triple High-Side Power-MOS Driver features
all necessary control and protection functions to
switch on three Power-MOS transistors operating
as High-Side switches in automotive electronic
control units. The key application field is relays replacement in systems where high current loads,
usually motors with nominal currents of about 40A
connected to ground, has to be switched.
A high signal at the EN pin enables all three
channels. With enable low gates are clamped to
ground. In this condition the gate sink current is
higher than the specified 3mA. An enable low sig4/12
nal makes also a reset of the timer.
A low signal at the inputs switch on the gates of
the external MOS. A short circuit at the input
leads to permanent activation of the concerned
channel. In this case the device can be disabled
with the enable pin. The charge pump loading is
not influenced due to the enable input.
An external N-channel MOS driver in high side
configuration needs a gate driving voltage higher
than VS. It is generated by means of a charge
pump with integrated charge transfer capacitors
and one external charge storage capacitor CCP.
The charge pump is dimensioned to load a ca-
L9380
Figure 4. Timing Characteristic.
VIN
VG
td
td
VDSmin
VS
VT
4.4V
0.4V
D98AT392
Toff
Figure 5. Drain, source input current.
ID
IPR + IDmax
VD
VS
>
=
VD
VS
VS
>
VD
pacitor CCP of 33nF in less than 20ms up to 8V
above VS. The value of CCP depends on the input
capacitance of the external MOS and the decay
of the charge pump voltage down to that value
where no significant influence on the application
occurs.
The necessary charging time for CCP has to be
respected in the sequence of the input control signals. As a consequence the lower gate to source
voltage can cause a higher drop across the
Power-MOS and get into overload condition. In
this case the overload protection timer will start.
After the protection time the concerned channel
will be switched off. Channel 3 is not equipped
with an overload protection. The same situation
can occur due to a discharge of the storage capacitor caused by the gate short to ground. The
gate driver that is supplied from the pin CP, which
is the charge pump output, has a sink and source
current capability of 3mA. For a short-circuit of the
load (source to ground) the L9380 has no gate to
source limitation. The gate source protection must
be done externally.
Channel 1 and 2 provide drain to source voltage
sensing possibility with programmable shut-off
delay when the activation threshold was exceeded. This threshold VDSmin is set by the external resistor RD. The bias current flowing through
this resistor is determined by the programming re-
IPR
0
D98AT393
ISmax
IS
sistor RPR. This external resistor RPR defines also
the charge and discharge current of the timer capacitor CCT. The drain to source threshold VDSmin
and the timer shut off delay time Toff can be calculated:
VDSmin = VPR (RD /RPR)
Toff = 4.4 CT RPR
5/12
L9380
In application which don’t use the overload protection or if one channel is not used, the Timer pin
of this channel must be connected to ground and
the drain pin with a resistor to Vbat.
The timing characteristic illustrates the function
and the meaning of VDSmin and Toff (see figure 4).
The input current of the overload sense comparator is specified as ISmax. The sum IPR + IDmax generates a drop across the external resistor RD if
the drain pin voltage is higher than the source pin
(see Fig. 5). In the switching point the comparator
input source pin currents are equal and the half of
the specified current ISmax. For an offset compensation equal external resistors (RD = RS) at drain
and source pin are imperative. The drain sense
comparator, which detects the overload, has a
symmetrical hysteresis of 20mV (see Fig. 6). Exceeding the source pin voltage by 10mV with respect to the drain voltage forces the timer capacitor to discharge. Decreasing the source pin
voltage 10mV lower than the drain pin voltage an
overload of the external MOS is detected and the
timer capacitor will be loaded. After reaching a
voltage at pin CT higher than the timer threshold
VThi the influenced channel is switched off. In this
case the overload is stored in the timer capacitor.
The timer capacitor will be discharged with a
’High’ signal at the input (see Fig. 4). After reaching the lower timer threshold VTLo the overload
protection is reset and the channel is able to
switch on again.
The application diagram is shown in Fig. 7. Because of the transients present at the power lines
during operation and possible disturbances in the
system the external resistors are necessary.
Positive ISO-Pulses at Drain, Gate Source are
clamped with an active clamping structure. The
clamping voltage is less than 60V. Negative
Pulses are only clamped with the ESD-Structure
less than -15V. This transients lower than -15V
can influence the other channels.
In order to protect the transistor against overload
and gate breakdown protection diodes between
gate and source and gate and drain has to be
connected. In case of overvoltage into VS (VS >
20V) the charge pump oscillation is stopped.
Then the charge pump capacitor will be loaded by
6/12
Figure 6. Comparator hysteresis.
VT
D98AT394
-10mV
VDr
+10mV
VSo
a diode and a resistor in series up to VS (see
Block Diagram). In this case the channels are not
influenced. In reverse battery condition the pins
D1, D2, S1, S2 follow the battery potential down
to -13V (high impedance) and the gate driver pins
G1, G2 is referred to S1, S2. In this way it is assured that M1 and M2 will not be driven into the
linear conductive mode. This protection function
is operating for VS1, VS2 down to -15V. The gate
driver output G3 is referred to the D1 in this case.
This function guarantees that the source to
source connected N-Channel MOS transistors M3
and M4 remains OFF.
All the supplies and the in- and output of the PCBoard are supplied with a 40 wires flat cable (not
used wires are left open). This cable is submitted
to the RF in the strip-line like described in DIN
40839-4 or ISO 11456-5.
The measured circuit was build up on a PCB
board with ground plane. In the frequency range
from 1MHz to 400MHz and 80% AM-modulation
of 1KHz with field strength of 200V/m no influence
to the basic function was detected on a typical device. The failure criteria is an envelope of the output signal with 20% in the amplitude and 2% in
the time.
L9380
Figure 7. Application Circuit.
D1
VBAT
VS
D2
CHARGE PUMP
OVERVOLTAGE
C1
VSI
T1
C2
C4
GND
D1
≥1
VSI
CP
IPR
+
R1
D3
G1
CP
M1
R2
D4
IN1
ENN
S1
≥1
R3
DRIVER 1
VSI
≥1
VSI
C3
D2
-
T2
IPR
+
R4
D5
G2
CP
M2
R5
D6
MICROCONTROLLER
IN2
ENN
S2
≥1
M
M1
R6
DRIVER 2
VSI
CP
ENN
IN3
D7
≥1
G3
M3
R7
DRIVER 3
D8
EN
ENN
VS
REG.
REFERENCE
VSI
IPR
M4
R8
2V
M
M2
PR
L1
L2
L3
L4
LOAD CONTROL
VALUE DRIVER
U405
D98AT395
Recommendations to the application circuit: The timer and the charge capacitors are loaded with an alternating current source. A short ground connection of the charge capacitor is indispensable to avoid
electromagnetic emigrations. The dimension of the resistors RD, RG and RS have to respect the maximum current during transients at each pin.
7/12
L9380
TYPICAL CHARACTERISTICS
Depending on production spread, certain deviations may occure. For limits (see pag. 4)
Figure 8. Charge Loading Time as function of VS
(Vcp = 8V +VS)
tCH
(ms)
Figure 9. Charge Pump Current as function of
the Charge Voltage
D98AT397
ICP
(µA)
D98AT396
100
20
12V
16V
10V
68nF
10
50
7V
33nF
10nF
0
0
6
8
10
12
14
16
Figure 10. Ground Loss Protection Gate Discarge Current for Source Voltage
D98AT398
IG
(µA)
7
VS(V)
17
27
VC(V)
Figure 11. Input Current as function of the Input
Voltage
D98AT399
IC
(µA)
-200
-5
-400
-10
-600
-15
-800
-1000
-20
-15
-10
-5
VS(V)
Figure 12. Overvoltage Shutdown of the Charge
Pump with Hysteresis
VCH
(V)
D98AT400
30
20
24
8/12
24.5
25
25.5
VS(V)
0
1
2
3
4
VI(V)
L9380
Figure 13. Measured Circuit.
The EMS of the device was verified in the below described setup.
3.125Hz 9
3
4
5
10
1
2
f
2
8
6.25Hz
f
U(t)
2
7
12.5Hz
+
f
CAR-BATTERY
2
6
25Hz
ANECHOIC CHAMBER
2m
STRIPLINE
2 BNC SMB7W01-200
SMT_39A
VS
100nF
CHARGE PUMP
33µF
OVERVOLTAGE
VSI
10nF
≥1
VSI
33nF
GND
D1
-
T1
CP
2KΩ
IPR
+
STD17N06
33V
G1
CP
10KΩ
18V
IN1
1KΩ
6
2.2nF
IN1
ENN
5.6V
S1
≥1
2KΩ
1KΩ
VSI
D2
-
T2
10nF
10KΩ
3
DRIVER 1
4.7nF
≥1
VSI
STD17N06
G2
33V
10KΩ
18V
1KΩ
7
2.2nF
IN2
ENN
5.6V
4.7nF
4
2KΩ
DRIVER 2
2.2nF
5Ω
10KΩ
S2
≥1
OUT1
2KΩ
IPR
+
CP
IN2
5Ω
B60N06
VS
1 BNC
B60N06
VBAT
1KΩ
OUT2
2.2nF
VSI
CP
IN3
1KΩ
8
2.2nF
EN
5.6V
2.2nF
ENN
5.6V
4.7nF
33V
G3
B60N06
10KΩ
10KΩ
18V
EN
10
STD17N06
≥1
DRIVER 3
4.7nF
1KΩ
9
ENN
IN3
VS
REG.
REFERENCE
VSI
OUT3
2.2nF
20KΩ
2V
IPR
5
1KΩ
PR
PC-BOARD IN RF BOX
D98AT401
9/12
L9380
Figure 14: PCB Board
Electromagnetic Emission Classification (EME)
Electromagnetic Emission classes presented below are typical data found on bench test. For detailes
test description please refer to "Electromagnetic Emission (EME) Measurement of Integrated Circuits,
DC to 1GHz" of VDE/ZVEI work group 767.13 and VDE/ZVEI work group 767.14 or IEC project number
47A 1967Ed. This data is targeted to board designers to allow an estimation of emission filtering effort
required in application. All measurements are done with the EMS-board (See pages 9, 10)
Pin
VCP
EME class
G
-
Remark
w
Electromagnetic Emission and Susceptivity is not tested in production.
10/12
L9380
SO20 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
0 (min.)8 (max.)
L
h x 45˚
A
B
e
A1
K
C
H
D
20
11
E
1
10
SO20MEC
11/12
L9380
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1998 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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12/12